A new gate voltage bootstrap switch sampling circuit

Abstract

The present invention belongs to the field of power electronics and integrated circuits, and specifically provides a new gate voltage bootstrap switch sampling circuit to solve the problem that the traditional gate voltage bootstrap switch sampling circuit cannot start up too quickly due to the overly complex working path. The present invention includes a bootstrap circuit, a holding circuit and a sampling tube. The bootstrap circuit includes a bootstrap capacitor and a digital switching circuit; the bootstrap capacitor is used to obtain a signal source according to the digital switching circuit and output a bootstrap voltage to the gate of the sampling tube according to the signal source; the holding circuit is used to control the charging of the bootstrap capacitor and the reset of the sampling tube gate potential according to two opposite clock signals; the digital switching circuit is used to control the discharge of the bootstrap capacitor C1 according to two opposite clock signals, and control the holding circuit to control the gate voltage of the sampling tube. The present invention can complete the gate voltage boosting work of the switching tube through fewer component loops, effectively reducing the working time of the gate voltage bootstrap switch sampling circuit.

Description

Technical Field

[0001] The present invention belongs to the field of power electronics and integrated circuits, and specifically provides a novel gate voltage bootstrap switch sampling circuit. Background Art

[0002] With the rapid development of modern communications and microelectronics technology, analog-to-digital converters (ADCs) are used in various fields. The sample-and-hold circuit is located at the front end of the ADC and is a key component that determines the input bandwidth and sampling frequency of the ADC. The key circuit that determines its sampling is the gate voltage bootstrap circuit. With the continuous improvement of the requirements for sampling speed and accuracy, the research on related gate voltage bootstrap circuits is becoming increasingly important.

[0003] In order to meet the requirements of sampling accuracy, gate voltage bootstrap switch technology is generally used to complete the design of the switch tube. The gate voltage bootstrap switch sampling circuit based on traditional technology is as follows: Figure 1 As shown, the present invention includes: a bootstrap circuit, a sampling tube, and a holding control circuit. By controlling the clock signals of the MOS tubes M1, M6, and M7, the charging and discharging of the bootstrap capacitor C1 is completed, thereby increasing the gate voltage of the switch tube, and further realizing a high-performance switch tube with a high gate voltage. However, due to the excessively complex working path of the general gate voltage bootstrap switch sampling circuit, its working start speed is often not too fast. Summary of the Invention

[0004] The present invention aims to address the problem in conventional gate voltage bootstrap switch sampling circuits, which suffer from a limited turn-on speed due to overly complex operating paths. By providing a novel gate voltage bootstrap switch sampling circuit, the present invention can boost the gate voltage of a switching transistor using fewer components and loops, effectively reducing the operating time of the gate voltage bootstrap switch sampling circuit.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A novel gate voltage bootstrap switch sampling circuit includes a bootstrap circuit, a holding circuit, and a sampling tube; the characteristics are:

[0007] The sampling tube is a first MOS tube M1, the drain of the first MOS tube M1 is connected to the input signal Vin, and the source of the first MOS tube M1 is connected to the output signal Vout;

[0008] The bootstrap circuit includes: a transmission gate circuit, a bootstrap capacitor C1, a third MOS transistor M3 and a twelfth MOS transistor M12, wherein the transmission gate circuit is composed of a first transmission gate switch and a second transmission gate switch; the first transmission gate switch is composed of a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein the source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6 and is also connected to the gate of the third MOS transistor M3, and the drain of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and is also connected to the input signal Vin; the second transmission gate switch is composed of a seventh MOS transistor M7 and an eighth MOS transistor M8, wherein the seventh MOS transistor M The source of the fifth MOS transistor M5 is connected to the drain of the eighth MOS transistor M8 and is also connected to the first end of the bootstrap capacitor C1. The drain of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and is also connected to the input signal Vin. The gates of the fifth MOS transistor M5 and the seventh MOS transistor M7 are both input with the first clock signal CLK. The gates of the sixth MOS transistor M6 and the eighth MOS transistor M8 are both input with the second clock signal CLKN. The second clock signal CLKN is opposite to the first clock signal CLK. The second end of the bootstrap capacitor C1 is connected to the source of the third MOS transistor M3. The drain of the third MOS transistor M3 is connected to the gate of the first MOS transistor M1.

[0009] The holding circuit includes: a ninth MOS transistor M9, a fourth MOS transistor M4, a second MOS transistor M2, a tenth MOS transistor M10, and an eleventh MOS transistor M11. The drain of the ninth MOS transistor M9 is connected to the first end of the bootstrap capacitor C1, the source of the fourth MOS transistor M4 is connected to the second end of the bootstrap capacitor C1, the source of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3, the drain of the tenth MOS transistor M10 is connected to the gate of the first MOS transistor M1, and the source of the tenth MOS transistor M10 is connected to the drain of the eleventh MOS transistor M11. The ninth MOS transistor M9 and the second MOS transistor M2 are connected to each other and are also connected to the drain of the twelfth MOS transistor M12; the source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 are both grounded, the drain of the fourth MOS transistor M4, the drain of the second MOS transistor M2, the gate of the tenth MOS transistor M10, and the source of the twelfth MOS transistor M12 are all connected to the power supply Vdd; the gates of the ninth MOS transistor M9 and the second MOS transistor M2 are both input with the first clock signal CLK, and the gates of the fourth MOS transistor M4, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 are all input with the second clock signal CLKN.

[0010] Furthermore, in the novel gate voltage bootstrap switch sampling circuit, the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the seventh MOS transistor M7, the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are all NMOS transistors, and the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the eighth MOS transistor M8, and the twelfth MOS transistor M12 are all PMOS transistors.

[0011] Based on the above technical solution, the beneficial effects of the present invention are:

[0012] The present invention provides a novel gate voltage bootstrap switch sampling circuit. Compared with traditional circuits, the number of components required for the opening path of the novel gate voltage bootstrap circuit is greatly reduced. The bootstrap circuit only needs to work through a transmission gate and a MOS tube, while the traditional circuit requires three different MOS tubes to cooperate with each other. Obviously, the working path of the novel gate voltage bootstrap circuit is simpler, thereby realizing high-speed sampling of the switch tube. Ultimately, the present invention reduces the on-resistance of the switch tube, reduces the circuit complexity, realizes the accuracy requirements of the switch tube under high-speed sampling, and has the characteristics of high-speed sampling stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of the structure of the gate voltage bootstrap switch sampling circuit based on traditional technology.

[0014] Figure 2 This is a structural schematic diagram of the novel gate voltage bootstrap switch sampling circuit provided by the present invention.

[0015] Figure 3 This is a schematic diagram of the working principle of the novel gate voltage bootstrap switch sampling circuit provided by the present invention in the holding stage.

[0016] Figure 4 This is a schematic diagram of the working principle of the novel gate voltage bootstrap switch sampling circuit provided by the present invention in the sampling stage. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0018] This embodiment provides a novel gate voltage bootstrap switch sampling circuit, the structure of which is as follows: Figure 2 As shown, it includes: a bootstrap circuit, a holding circuit and a sampling tube; wherein:

[0019] The sampling tube is a first MOS tube M1, the drain of the first MOS tube M1 is connected to the input signal Vin, and the source of the first MOS tube M1 is connected to the output signal Vout;

[0020] The bootstrap circuit includes: a digital switch circuit, a bootstrap capacitor C1, a third MOS transistor M3 and a twelfth MOS transistor M12. The digital switch circuit is composed of a first transmission gate switch and a second transmission gate switch; the first transmission gate switch is composed of a fifth MOS transistor M5 and a sixth MOS transistor M6, the source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6 and to the gate of the third MOS transistor M3, the drain of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and to the input signal Vin; the second transmission gate switch is composed of a seventh MOS transistor M7 and an eighth MOS transistor M8, the seventh MOS transistor M8 is connected to the drain of the sixth MOS transistor M6 and to the gate of the third MOS transistor M3; the drain of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and to the input signal Vin; The source of M7 is connected to the drain of the eighth MOS transistor M8 and to the first end of the bootstrap capacitor C1. The drain of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and to the input signal Vin. The gates of the fifth MOS transistor M5 and the seventh MOS transistor M7 are both input with the first clock signal CLK. The gates of the sixth MOS transistor M6 and the eighth MOS transistor M8 are both input with the second clock signal CLKN. The second clock signal CLKN is opposite to the first clock signal CLK. The second end of the bootstrap capacitor C1 is connected to the source of the third MOS transistor M3. The drain of the third MOS transistor M3 is connected to the gate of the first MOS transistor M1.

[0021] The holding circuit includes: a ninth MOS transistor M9, a fourth MOS transistor M4, a second MOS transistor M2, a tenth MOS transistor M10, and an eleventh MOS transistor M11. The drain of the ninth MOS transistor M9 is connected to the first end of the bootstrap capacitor C1, the source of the fourth MOS transistor M4 is connected to the second end of the bootstrap capacitor C1, the source of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3, the drain of the tenth MOS transistor M10 is connected to the gate of the first MOS transistor M1, and the source of the tenth MOS transistor M10 is connected to the drain of the eleventh MOS transistor M11. The ninth MOS transistor M9 and the second MOS transistor M2 are connected to each other and are also connected to the drain of the twelfth MOS transistor M12; the source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 are both grounded, the drain of the fourth MOS transistor M4, the drain of the second MOS transistor M2, the gate of the tenth MOS transistor M10, and the source of the twelfth MOS transistor M12 are all connected to the power supply Vdd; the gates of the ninth MOS transistor M9 and the second MOS transistor M2 are both input with the first clock signal CLK, and the gates of the fourth MOS transistor M4, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 are all input with the second clock signal CLKN.

[0022] In the novel gate voltage bootstrap switch sampling circuit, the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the seventh MOS transistor M7, the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are all NMOS transistors, and the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the eighth MOS transistor M8, and the twelfth MOS transistor M12 are all PMOS transistors.

[0023] In terms of working principle:

[0024] In the novel gate voltage bootstrap switch sampling circuit provided by the present invention, a bootstrap capacitor C1 is used to obtain a signal source according to a digital switching circuit and output a bootstrap voltage to the gate of a first MOS transistor M1 according to the signal source; a holding circuit is respectively connected to the bootstrap circuit and the sampling transistor and is used to control the charging of the bootstrap capacitor C1 and the resetting of the gate potential of the first MOS transistor M1 according to a first clock signal CLK and a second clock signal CLKN; the digital switching circuit is used to control the discharging of the bootstrap capacitor C1 according to the first clock signal CLK and a second clock signal CLKN which is opposite to the first clock signal CLK, and to control the holding circuit's control of the sampling transistor gate voltage.

[0025] like Figure 3 FIG2 is a schematic diagram showing the working principle of the novel gate voltage bootstrap switch sampling circuit in the hold phase. The first and second transmission gates are turned off by a clock signal, and the fourth and ninth MOS transistors M4 and M11 are turned on to complete the charging of the bootstrap capacitor C1, so that the voltage across the bootstrap capacitor C1 is increased to the power supply voltage. At the same time, the second MOS transistor M2 is turned on to complete the shutoff of the third MOS transistor M3. The tenth and eleventh MOS transistors M10 and M11 are turned on to complete the gate voltage zeroing of the first MOS transistor M1.

[0026] like Figure 4 The figure shows the working principle of the novel gate voltage bootstrap switch sampling circuit in the sampling phase. The first transmission gate is controlled by the clock signal, and the second transmission gate is opened. Since the third MOS transistor M3 is a PMOS transistor, the potential transmitted to the gate voltage of the third MOS transistor M3 through the first transmission gate is lower than the potential of the second transmission gate plus the capacitor charge, causing the third MOS transistor M3 to be turned on. The voltage drop on the bootstrap capacitor C1 is added to the input voltage and output to the gate of the first MOS transistor M1, completing the gate voltage boost of the switch transistor.

[0027] In such Figure 1 In the conventional gate voltage bootstrap switch sampling circuit shown, its sampling working path first needs to turn on the MOS transistor M1, and then complete the switching operation of the MOS transistor M6 through the MOS transistors M3 and M7. It is obvious that the startup path of the conventional gate voltage bootstrap switch sampling circuit has more working components and a more complex working path than the present invention, and it takes more time to start up.

[0028] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A novel gate voltage bootstrap switch sampling circuit, comprising: Bootstrap circuit, holding circuit and sampling tube; characterized by: The sampling tube is a first MOS tube M1, the drain of the first MOS tube M1 is connected to the input signal Vin, and the source of the first MOS tube M1 is connected to the output signal Vout; The bootstrap circuit includes: a digital switch circuit, a bootstrap capacitor C1, a third MOS transistor M3 and a twelfth MOS transistor M12. The digital switch circuit is composed of a first transmission gate switch and a second transmission gate switch; the first transmission gate switch is composed of a fifth MOS transistor M5 and a sixth MOS transistor M6, the source of the fifth MOS transistor M5 is connected to the drain of the sixth MOS transistor M6 and to the gate of the third MOS transistor M3, the drain of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and to the input signal Vin; the second transmission gate switch is composed of a seventh MOS transistor M7 and an eighth MOS transistor M8, the seventh MOS transistor M8 is connected to the drain of the sixth MOS transistor M6 and to the gate of the third MOS transistor M3; the drain of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and to the input signal Vin; The source of M7 is connected to the drain of the eighth MOS transistor M8 and to the first end of the bootstrap capacitor C1. The drain of the seventh MOS transistor M7 is connected to the source of the eighth MOS transistor M8 and to the input signal Vin. The gates of the fifth MOS transistor M5 and the seventh MOS transistor M7 are both input with the first clock signal CLK. The gates of the sixth MOS transistor M6 and the eighth MOS transistor M8 are both input with the second clock signal CLKN. The second clock signal CLKN is opposite to the first clock signal CLK. The second end of the bootstrap capacitor C1 is connected to the source of the third MOS transistor M3. The drain of the third MOS transistor M3 is connected to the gate of the first MOS transistor M1. The holding circuit includes: a ninth MOS transistor M9, a fourth MOS transistor M4, a second MOS transistor M2, a tenth MOS transistor M10, and an eleventh MOS transistor M11. The drain of the ninth MOS transistor M9 is connected to the first end of the bootstrap capacitor C1, the source of the fourth MOS transistor M4 is connected to the second end of the bootstrap capacitor C1, the source of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3, the drain of the tenth MOS transistor M10 is connected to the gate of the first MOS transistor M1, and the source of the tenth MOS transistor M10 is connected to the drain of the eleventh MOS transistor M11. The ninth MOS transistor M9 and the second MOS transistor M2 are connected to each other and are also connected to the drain of the twelfth MOS transistor M12; the source of the ninth MOS transistor M9 and the source of the eleventh MOS transistor M11 are both grounded, the drain of the fourth MOS transistor M4, the drain of the second MOS transistor M2, the gate of the tenth MOS transistor M10, and the source of the twelfth MOS transistor M12 are all connected to the power supply Vdd; the gates of the ninth MOS transistor M9 and the second MOS transistor M2 are both input with the first clock signal CLK, and the gates of the fourth MOS transistor M4, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 are all input with the second clock signal CLKN.

2. The novel gate voltage bootstrap switch sampling circuit according to claim 1, characterized in that: In the novel gate voltage bootstrap switch sampling circuit, the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the seventh MOS transistor M7, the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are all NMOS transistors, and the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the eighth MOS transistor M8, and the twelfth MOS transistor M12 are all PMOS transistors.

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