1553B protocol communication method applied to integrated avionics system

Abstract

The present invention provides a 1553B protocol communication method applied to an integrated avionics system, comprising: when receiving data, the 1553B protocol chip and FPGA control the reception of data through an interrupt mode, the received data and the control word are stored in the FPGA using a FIFO, the FIFO data status bit indicates whether the data is valid, and the data is reported to the CPU through an interrupt mode, so as to ensure that there is no packet loss or re-retrieval during the data reception process; when sending data, the CPU and FPGA use a method of querying the status of the sent data to update the sent data, and the FPGA and the 1553B protocol chip use two methods of active update and passive reception interrupt to update the sent data, make full use of the bus time slot, and use the method of setting and clearing the vector word to indicate the presence or absence of the sent data, so as to ensure that there is no packet loss or repetition during the data transmission process. That is, the present invention can avoid the problem of data packet loss and re-retrieval during the sending and receiving process.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated avionics systems, and in particular to a 1553B protocol communication method applied to an integrated avionics system. Background Art

[0002] With the increase in the number of avionics equipment, the effective integration of various avionics equipment to achieve efficient and reasonable utilization of resources and functions is an inevitable requirement for avionics equipment bus communication. 1553B (MIL-STD-1553B) bus protocol is widely used in various avionics equipment due to its high reliability and real-time performance.

[0003] In the integrated avionics system, it is composed of the display and control system, central control equipment, ATC air traffic control transponder and other equipment. The display and control system, as the upper avionics system, sends various ATC air traffic control control commands to the central control equipment through the 1553B bus. The central control equipment forwards them to the ATC air traffic control transponder through the 1553B bus. The air traffic control transponder analyzes the received data and completes the control instructions. The ATC air traffic control equipment reports target information and warning information to the central control equipment through 1553B. The central control equipment forwards them to the upper avionics through the 1553B bus to complete the target display.

[0004] In traditional integrated avionics systems, 1553B bus communication usually adopts 1553B protocol chip and CPU architecture. Since 1553B protocol chip and external communication adopt LocalBus bus and interrupt mode, and CPU LocalBus bus resources are relatively precious, this architecture will affect the layout of other peripherals. However, 1553B protocol chip and FPGA and CPU architecture are adopted. Communication between 1553B protocol chip and CPU is completed through FPGA, and 1553B bus receiving and sending communication control logic is placed in FPGA, and data processing is placed in CPU. It can make good use of FPGA's rich hardware interface resources. However, since there is an FPGA between 1553B protocol chip and CPU, the sending data and receiving data in 1553B protocol chip will not be automatically cleared after being taken away, and can only be overwritten by new data. The data sending and receiving cycles on both sides may deviate, resulting in data packet loss or repeated acquisition of the same packet of data. Summary of the invention

[0005] The present invention aims to provide a 1553B protocol communication method applied to an integrated avionics system to solve the problem of data packet loss or re-retrieval during the transmission and reception process.

[0006] The present invention provides a 1553B protocol communication method applied to an integrated avionics system, comprising:

[0007] When receiving data, the 1553B protocol chip and FPGA control data reception through interrupts. The received data and control words are stored in FIFO in the FPGA. The FIFO data status bit indicates whether the data is valid and reports it to the CPU through interrupts to ensure that no packet is lost or re-read during data reception.

[0008] When sending data, the CPU and FPGA use the method of querying the data sending status to update the sending data. The FPGA and 1553B protocol chip use two methods, active update and passive receive interrupt, to update the sending data, fully utilize the bus time slot, and use the vector word setting and clearing method to indicate the presence or absence of sending data, to ensure that there is no packet loss or duplication during data transmission.

[0009] Furthermore, the 1553B protocol communication method applied to the integrated avionics system comprises the following steps:

[0010] S1, FPGA initializes 1553B protocol chip;

[0011] S2, when the CPU receives data, the CPU waits for the FPGA to receive data interrupt. After receiving the interrupt, the CPU reads the FIFO data status bit and reads a complete packet of received data. Then, the CPU issues a read completion command, processes the received data, and waits for the next FPGA to receive data interrupt.

[0012] When the CPU sends data, the CPU queries the data sending status of the sending sub-address in the FPGA, and determines whether to send the sending data and control word and the sending completion flag to the FPGA according to the data sending status;

[0013] S3, when FPGA receives the data sent by CPU, upon receiving the sending completion flag from CPU, it updates the received data into the register and pulls up the sending data READY signal of the corresponding sub-address;

[0014] S4, FPGA performs transmission time slot and reception time slot control;

[0015] S5, when FPGA reports to CPU to receive data, when reading FIFO for the first time, it pre-reads a packet of data from FIFO, then pulls the receive data interrupt to CPU, and waits for the read completion command issued by CPU. If CPU issues the read completion command, FPGA reads a packet of new data from FIFO, and pulls the receive data interrupt to CPU again; if CPU times out and does not issue the read completion command, FPGA pulls the receive data interrupt to CPU again.

[0016] Furthermore, in step S1, the FPGA initializes the 1553B protocol chip, including configuring register parameters, initializing data blocks, and clearing vector words.

[0017] Further, in step S2, when the CPU sends data, it determines whether to send the sending data, the control word, and the sending completion flag to the FPGA according to the data sending status, which specifically includes:

[0018] When the data transmission status is high, it means that the current sub-address is being sent, and the CPU needs to query the data transmission status again in the next query cycle;

[0019] When the data transmission status is low, it means that the current sub-address is idle, and the CPU sends the transmission data and control word to the FPGA, and then sends the transmission completion flag.

[0020] Furthermore, in step S4, the FPGA performs the control of the sending time slot and the receiving time slot, which specifically includes the following sub-steps:

[0021] S4.01, determine whether the FPGA initialization 1553B protocol chip is completed, if yes, go to step S4.02, otherwise loop step S4.01;

[0022] S4.02, FPGA determines whether there is a 1553B protocol chip interrupt, if yes, go to step S4.03; otherwise, go to step S4.04;

[0023] S4.03, FPGA queries the stack pointer of the 1553B protocol chip, and obtains the message descriptor address pointed to by the stack pointer; then queries the message descriptor address, obtains the control word and data block pointer, and then goes to step S4.05;

[0024] S4.04, FPGA determines whether there is a data sending READY signal, if yes, go to step S4.08; otherwise, go to step S4.02;

[0025] S4.05, determine whether the control word is a sending control word or a receiving control word, if it is a receiving control word, go to step S4.06; if it is a sending control word, go to step S4.07;

[0026] S4.06, FPGA obtains the received data through the data block pointer, and packs the control word and the received data into FIFO to prevent data loss, and then goes to step S4.02;

[0027] S4.07, FPGA obtains the sending sub-address by sending the control word, and then goes to step S4.08;

[0028] S4.08, FPGA determines whether there is a READY signal for sending data of the sub-address, if yes, go to step S4.09; otherwise, go to step S4.10;

[0029] S4.09, FPGA writes the transmission data into the 1553B protocol chip and sets the corresponding vector word bit, and then goes to step S4.11;

[0030] S4.10, FPGA clears the corresponding vector word bit, and then goes to step S4.11;

[0031] S4.11, FPGA writes the vector word into the 1553B protocol chip, and then goes to step S4.02.

[0032] In some preferred embodiments, the CPU refers to a core component including an arithmetic unit, a controller and a register.

[0033] In some preferred solutions, the CPU can be replaced by ARM, PPC or DSP.

[0034] In some preferred embodiments, the FPGA includes a programmable logic device.

[0035] In some preferred solutions, the FPGA can be replaced by SPLD or CPLD.

[0036] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0037] The 1553B protocol communication method applied to the integrated avionics system proposed in the present invention can effectively avoid the problems of data packet loss and re-retrieval during data transmission and reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 Flowchart for controlling the transmit and receive time slots for the FPGA. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Example

[0043] In the integrated avionics system, the display and control system sends various ATC air traffic control commands to the central control device through the 1553B bus, and the central control device forwards them to the ATC air traffic control transponder through the 1553B bus. The air traffic control transponder parses the received data and completes the response to the control command. The ATC air traffic control equipment reports target information and warning information to the central control device through the 1553B bus, and the central control device forwards it to the avionics through the 1553B bus to complete the target display. When the ATC air traffic control equipment receives the control command, if the data packet is lost, it may not be able to respond to the control command of the display and control system, so that the ATC equipment is not controlled by the display and control, and equipment failure occurs. When the ATC air traffic control equipment reports target information and warning information, if the data packet is lost, or the same packet of data is reported repeatedly, the air target may be lost, or a false alarm target may appear, thereby affecting the system performance. Therefore, in order to solve the problem of data packet loss and repeated data acquisition, this embodiment proposes a 1553B protocol communication method applied to the integrated avionics system, including:

[0044] When receiving data, the 1553B protocol chip and FPGA control data reception through interrupts. The received data and control words are stored in FIFO in the FPGA. The FIFO data status bit indicates whether the data is valid and reports it to the CPU through interrupts to ensure that no packet is lost or re-read during data reception.

[0045] When sending data, the CPU and FPGA use the method of querying the data sending status to update the sending data. The FPGA and 1553B protocol chip use two methods, active update and passive receive interrupt, to update the sending data, fully utilize the bus time slot, and use the vector word setting and clearing method to indicate the presence or absence of sending data, to ensure that there is no packet loss or duplication during data transmission.

[0046] It should be noted that the above-mentioned CPU includes core components such as ARM, PPC, DSP, etc., which include an arithmetic unit, a controller, and a register, and the FPGA includes programmable logic devices such as SPLD and CPLD.

[0047] The 1553B protocol communication method applied to the integrated avionics system comprises the following steps:

[0048] S1. FPGA initializes the 1553B protocol chip, including configuring register parameters, initializing data blocks, and clearing vector words;

[0049] S2, when the CPU receives data, the CPU waits for the FPGA to receive data interrupt. After receiving the interrupt, the CPU reads the FIFO data status bit and reads a complete packet of received data. Then, the CPU issues a read completion command, processes the received data, and waits for the next FPGA to receive data interrupt.

[0050] When the CPU sends data, the CPU queries the data sending status of the sending sub-address in the FPGA, and determines whether to send the sending data, control word, and sending completion flag to the FPGA according to the data sending status. Specifically:

[0051] When the data transmission status is high, it means that the current sub-address is being sent, and the CPU needs to query the data transmission status again in the next query cycle;

[0052] When the data transmission status is low, it means that the current sub-address is idle, and the CPU sends the transmission data and control word to the FPGA, and then sends the transmission completion flag.

[0053] S3. When the FPGA receives the data sent by the CPU, upon receiving the sending completion flag from the CPU, it updates the received data into the register and pulls up the sending data READY signal of the corresponding sub-address.

[0054] S4, FPGA controls the sending time slot and receiving time slot. The control flow chart is as follows Figure 1 As shown, it specifically includes the following sub-steps:

[0055] S4.01, determine whether the FPGA initialization 1553B protocol chip is completed, if yes, go to step S4.02, otherwise loop step S4.01;

[0056] S4.02, FPGA determines whether there is a 1553B protocol chip interrupt, if yes, go to step S4.03; otherwise, go to step S4.04;

[0057] S4.03, FPGA queries the stack pointer of the 1553B protocol chip, and obtains the message descriptor address pointed to by the stack pointer; then queries the message descriptor address, obtains the control word and data block pointer, and then goes to step S4.05;

[0058] S4.04, FPGA determines whether there is a data sending READY signal, if yes, go to step S4.08; otherwise, go to step S4.02;

[0059] S4.05, determine whether the control word is a sending control word or a receiving control word, if it is a receiving control word, go to step S4.06; if it is a sending control word, go to step S4.07;

[0060] S4.06, FPGA obtains the received data through the data block pointer, and packs the control word and the received data into FIFO to prevent data loss, and then goes to step S4.02;

[0061] S4.07, FPGA obtains the sending sub-address by sending the control word, and then goes to step S4.08;

[0062] S4.08, FPGA determines whether there is a READY signal for sending data of the sub-address, if yes, go to step S4.09; otherwise, go to step S4.10;

[0063] S4.09, FPGA writes the transmission data into the 1553B protocol chip and sets the corresponding vector word bit, and then goes to step S4.11;

[0064] S4.10, FPGA clears the corresponding vector word bit, and then goes to step S4.11;

[0065] S4.11, FPGA writes the vector word into the 1553B protocol chip, and then goes to step S4.02.

[0066] S5, when FPGA reports to CPU to receive data, when reading FIFO for the first time, it pre-reads a packet of data from FIFO, then pulls the receive data interrupt to CPU, and waits for the read completion command issued by CPU. If CPU issues the read completion command, FPGA reads a packet of new data from FIFO, and pulls the receive data interrupt to CPU again; if CPU times out and does not issue the read completion command, FPGA pulls the receive data interrupt to CPU again.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A 1553B protocol communication method applied to an integrated avionics system. It is characterized in that include: When receiving data, the 1553B protocol chip and FPGA control data reception through interrupts. The received data and control words are stored in FIFO in the FPGA. The FIFO data status bit indicates whether the data is valid and reports it to the CPU through interrupts to ensure that no packet is lost or re-read during data reception. When sending data, the CPU and FPGA use the method of querying the sending data status to update the sending data. The FPGA and 1553B protocol chip use two methods, active update and passive reception interrupt, to update the sending data, making full use of the bus time slot, and using the vector word setting and clearing method to indicate whether there is sending data, ensuring that there is no packet loss or duplication during data transmission; The 1553B protocol communication method applied to the integrated avionics system comprises the following steps: S1, FPGA initializes 1553B protocol chip; S2, when the CPU receives data, the CPU waits for the FPGA to receive data interrupt. After receiving the interrupt, the CPU reads the FIFO data status bit and reads a complete packet of received data. Then, the CPU issues a read completion command, processes the received data, and waits for the next FPGA to receive data interrupt. When the CPU sends data, the CPU queries the data sending status of the sending sub-address in the FPGA, and determines whether to send the sending data and control word and the sending completion flag to the FPGA according to the data sending status; S3, when FPGA receives the data sent by CPU, upon receiving the sending completion flag from CPU, it updates the received data into the register and pulls up the sending data READY signal of the corresponding sub-address; S4, FPGA performs transmission time slot and reception time slot control; S5, when FPGA reports received data to CPU, when reading FIFO for the first time, it pre-reads a packet of data from FIFO, then pulls the receive data interrupt to CPU, and waits for the read completion command sent by CPU; If the CPU issues a read completion command, the FPGA reads a new packet of data from the FIFO and pulls a receive data interrupt to the CPU again; if the CPU times out and does not issue a read completion command, the FPGA pulls a receive data interrupt to the CPU again; In step S4, the FPGA performs the control of the sending time slot and the receiving time slot, which specifically includes the following sub-steps: S4.01, determine whether the FPGA initialization 1553B protocol chip is completed, if yes, go to step S4.02, otherwise loop step S4.01; S4.02, FPGA determines whether there is a 1553B protocol chip interrupt, if yes, go to step S4.03; Otherwise, go to step S4.04; S4.03, FPGA queries the stack pointer of the 1553B protocol chip and obtains the message descriptor address pointed to by the stack pointer; Then query the message descriptor address, obtain the control word and data block pointer, and then go to step S4.05; S4.04, FPGA determines whether there is a data sending READY signal, if yes, go to step S4.08; Otherwise, go to step S4.02; S4.05, determine whether the control word is a sending control word or a receiving control word, if it is a receiving control word, go to step S4.06; If it is to send a control word, go to step S4.07; S4.06, FPGA obtains the received data through the data block pointer, and packs the control word and the received data into FIFO to prevent data loss, and then goes to step S4.02; S4.07, FPGA obtains the sending sub-address by sending the control word, and then goes to step S4.08; S4.08, FPGA determines whether there is a READY signal for sending data of the sub-address, if yes, go to step S4.09; otherwise, go to step S4.10; S4.09, FPGA writes the transmission data into the 1553B protocol chip and sets the corresponding vector word bit, and then goes to step S4.11; S4.10, FPGA clears the corresponding vector word bit, and then goes to step S4.11; S4.11, FPGA writes the vector word into the 1553B protocol chip, and then goes to step S4.

02.

2. The 1553B protocol communication method applied to an integrated avionics system according to claim 1, It is characterized in that In step S1, the FPGA initializes the 1553B protocol chip, including configuring register parameters, initializing data blocks, and clearing vector words.

3. The 1553B protocol communication method applied to an integrated avionics system according to claim 1, It is characterized in that In step S2, when the CPU sends data, it determines whether to send the sending data, the control word, and the sending completion flag to the FPGA according to the data sending status, which specifically includes: When the data transmission status is high, it means that the current sub-address is being sent, and the CPU needs to query the data transmission status again in the next query cycle; When the data transmission status is low, it means that the current sub-address is idle, and the CPU sends the transmission data and control word to the FPGA, and then sends the transmission completion flag.

4. The 1553B protocol communication method applied to an integrated avionics system according to any one of claims 1 to 3, It is characterized in that The CPU refers to a core component including an arithmetic unit, a controller and a register.

5. The 1553B protocol communication method applied to an integrated avionics system according to claim 4, It is characterized in that The CPU is replaced by ARM, PPC or DSP.

6. The 1553B protocol communication method applied to an integrated avionics system according to any one of claims 1 to 3, It is characterized in that The FPGA includes a programmable logic device.

7. The 1553B protocol communication method applied to an integrated avionics system according to claim 6, It is characterized in that The FPGA is replaced by SPLD or CPLD.

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