Dual-loop adaptive equalizer circuit based on power comparison

Abstract

The application provides a double-loop adaptive equalizer circuit based on power comparison, which comprises an equalizer, an input end of the equalizer being connected with a differential data stream; an adjusting circuit, an input end of the adjusting circuit being electrically connected with an output end of the equalizer; a high-frequency adaptive loop, which is used for detecting high-frequency power and low-frequency power of an output signal of the equalizer; a low-frequency adaptive loop, which is used for detecting high-frequency power and low-frequency power of an output signal of the adjusting circuit; the high-frequency adaptive loop and the low-frequency adaptive loop respectively generate high-frequency control signals and low-frequency control signals by comparing the high-frequency power and the low-frequency power of the output signals of the equalizer and the adjusting circuit, so as to adjust the high-frequency power and / or the low-frequency power of one or two signals, and make the high-frequency power and the low-frequency power of the two signals tend to be the same respectively. The equalizer has strong adaptive equalization capability and is not easily affected by external factors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of adaptive development of equalizers in integrated circuits, and particularly relates to a double-loop adaptive equalizer circuit based on power comparison. BACKGROUND

[0002] Due to the non-ideal conductivity of copper, dielectric, connectors and other discontinuous characteristics, the transmission channel presents a low-pass filtering characteristic in the frequency domain, and the high-frequency components of the signal are attenuated after passing through the transmission channel, resulting in serious intersymbol interference (ISI), which causes the information transmitted by the signal to be severely damaged and the bit error rate (BER) to be greatly improved. The continuous-time linear equalizer (CTLE) presents a high-pass filtering characteristic in the frequency domain, which exactly offsets the high-frequency attenuation characteristic of the transmission channel, compensates for the high-frequency components of the signal attenuated due to the transmission channel, and restores the integrity of the signal. However, the high-frequency attenuation characteristic of the transmission channel is not fixed, and it will be affected by the conductor material of the transmission channel, the length of the channel, the environmental factors, etc. In order to meet the best compensation for the fluctuation of the high-frequency attenuation characteristic of the transmission channel, it is particularly important to introduce adaptive control in the CTLE.

[0003] There are two kinds of traditional adaptive equalization methods, specifically:

[0004] The first one is the adaptive equalization method based on spectral equalization, the core idea of which is to analyze the power of the data stream in the frequency domain.

[0005]

[0006] A balanced frequency f m is used to separate the spectral density function S(x) of an ideal NRZ random data stream into two spectrums with the same power, and by comparing the power difference between the low-frequency and high-frequency spectrums and converting it into an analog control signal, the equalization ability of the linear equalizer is adjusted, and finally the power of the two spectrums is equalized, so as to achieve optimal compensation.

[0007]

[0008] However, in fact, the power analysis in the frequency domain is the spectral density function S EQ (x) of the linear equalizer output data stream, which is related to the main pole p EQ of the linear equalizer in the frequency domain and will be affected by it, so it is difficult to determine f m . What's worse, f mThe cut-off frequency of the high-pass filter (cutting high frequency energy) and the low-pass filter (cutting low frequency energy) as the adaptive loop directly determines the control accuracy of the adaptive loop, f m Any deviation of f will cause the equalization effect of the adaptive equalization loop to greatly decrease.

[0009] The second is an adaptive equalization method based on slope detection, the core idea of which is to analyze the slope of the data jump edge in the time domain, use an amplitude limiter to generate an output signal with a slope (the slope is known to be the slope of the ideal signal), and use it as the reference of the output signal of the linear equalizer. By comparing the difference between the slopes of the output signals of the amplitude limiter and the linear equalizer and converting it into an analog control signal, the equalization ability of the equalizer is adjusted, and finally the slope of the output signal of the linear equalizer is consistent with the slope of the output signal of the amplitude limiter, so as to achieve optimal compensation. However, this method realizes adaptive equalization by detecting the slope of the signal in the time domain, which will face the problem of offset sensitivity. Worse still, at high transmission rates, the node parasitic capacitance of the slope detector will severely limit the accuracy of slope detection. SUMMARY

[0010] In order to solve the technical problem of poor adaptive equalization ability of the equalizer in the prior art, the application provides a double-loop adaptive equalizer circuit based on power comparison.

[0011] The application provides a double-loop adaptive equalizer circuit based on power comparison, which comprises:

[0012] An equalizer, wherein an input end of the equalizer inputs a differential data stream;

[0013] An adjusting circuit, wherein an input end of the adjusting circuit is electrically connected with an output end of the equalizer;

[0014] A high-frequency adaptive loop, which is used for detecting high-frequency power and low-frequency power of an output signal of the equalizer;

[0015] A low-frequency adaptive loop, which is used for detecting high-frequency power and low-frequency power of an output signal of the adjusting circuit;

[0016] The high-frequency adaptive loop and the low-frequency adaptive loop respectively generate a high-frequency control signal and a low-frequency control signal by comparing the high-frequency power and the low-frequency power of the output signals of the equalizer and the adjusting circuit, so as to adjust the high-frequency power and / or the low-frequency power of the output signals of the equalizer and / or the adjusting circuit, and make the high-frequency power and the low-frequency power of the output signals of the equalizer and the adjusting circuit tend to be the same.

[0017] Preferably, the adjusting circuit comprises:

[0018] a limiter, an input of the limiter being electrically connected with an output of the equalizer;

[0019] a loop regulator, an input of the loop regulator being electrically connected with an output of the limiter;

[0020] the high frequency adaptive loop generates a high frequency control signal by comparing high frequency power of the output signal of the equalizer and the output signal of the regulating circuit, and simultaneously feeds back to the equalizer and the loop regulator;

[0021] the low frequency adaptive loop generates a low frequency control signal by comparing low frequency power of the output signal of the equalizer and the output signal of the regulating circuit, and feeds back to the loop regulator.

[0022] Preferably, the high frequency adaptive loop comprises a first power detector, a high frequency comparator and a high frequency digital controller, and the low frequency adaptive loop comprises a second power detector, a low frequency comparator and a low frequency digital controller;

[0023] an input of the first power detector is electrically connected with an output of the equalizer, an input of the second power detector is electrically connected with an output of the loop regulator, high frequency power outputs and low frequency power outputs of the first power detector and the second power detector are respectively electrically connected with inputs of the high frequency comparator and the low frequency comparator, an output of the high frequency comparator is electrically connected with an input of the high frequency digital controller, an output of the high frequency digital controller is simultaneously electrically connected with a control end of the equalizer and a high frequency control end of the loop regulator, an output of the low frequency comparator is electrically connected with an input of the low frequency digital controller, and an output of the low frequency digital controller is electrically connected with a low frequency control end of the loop regulator.

[0024] Preferably, the first power detector and the second power detector each comprise a low frequency power detector and a high frequency power detector, wherein the low frequency power detector comprises a low frequency band pass filter and a low frequency rectifier, and the high frequency power detector comprises a high frequency band pass filter and a high frequency rectifier.

[0025] Preferably, the low frequency band pass filter comprises NPN transistors Q1-Q4, current sources I1-I3, capacitors C1-C2 and resistors R1-R2.

[0026] One end of the resistors R1 and R2, the collectors of the NPN transistors Q3 and Q4 are connected to the power supply voltage VDD simultaneously; the negative terminals of the current sources I1, I2 and I3 are connected to the ground simultaneously; the bases of the NPN transistors Q1 and Q2 are connected to the non-inverted signal input terminal VP and the inverted signal input terminal VN respectively; the other end of the resistor R1 is connected to the collector of the NPN transistor Q1, one end of the capacitor C1 and the base of the NPN transistor Q3 simultaneously; the other end of the resistor R2 is connected to the collector of the NPN transistor Q2, the other end of the capacitor C1 and the base of the NPN transistor Q4 simultaneously; the emitter of the NPN transistor Q1 is connected to one end of the capacitor C2 and the positive terminal of the current source I1 simultaneously; the emitter of the NPN transistor Q2 is connected to the other end of the capacitor C2 and the positive terminal of the current source I2 simultaneously; the emitters of the NPN transistors Q3 and Q4 are connected to the positive terminal of the current source I3.

[0027] Preferably, the high-frequency band-pass filter comprises NPN transistors Q5-Q8, current sources I4-I6, a capacitor C4 and resistors R3-R6;

[0028] One end of the resistors R3 and R4, the collectors of the NPN transistors Q7 and Q8 are connected to the power supply voltage VDD simultaneously; the negative terminals of the current sources I4, I5 and I6 are connected to the ground simultaneously; the bases of the NPN transistors Q5 and Q6 are connected to the non-inverted signal input terminal VP and the inverted signal input terminal VN respectively; the other end of the resistor R3 is connected to the bases of the NPN transistors Q5 and Q7 simultaneously; the other end of the resistor R4 is connected to the collector of the NPN transistor Q6 and the base of the NPN transistor Q8 simultaneously; the emitter of the NPN transistor Q5 is connected to one end of the resistor R5 and the positive terminal of the current source I4 simultaneously; the emitter of the NPN transistor Q6 is connected to one end of the resistor R6 and the positive terminal of the current source I5 simultaneously; the other end of the resistor R5 is connected to one end of the capacitor C4; the other end of the resistor R6 is connected to the other end of the capacitor C4; the emitters of the NPN transistors Q7 and Q8 are connected to the positive terminal of the current source I6.

[0029] Preferably, the equalizer comprises NPN transistors Q9-Q10, current sources I7-I8, capacitors C6-C8, inductors L1-L2 and resistors R7-R9, wherein the resistor R9 is a variable resistor controlled by a high-frequency control signal;

[0030] One end of the inductors L1 and L2 is connected to the power supply voltage VDD; the negative end of the current sources I7 and I8 and one end of the capacitors C7 and C8 are connected to the ground; the bases of the NPN transistors Q9 and Q10 are connected to the positive-phase signal input terminal VP and the negative-phase signal input terminal VN respectively; the other end of the inductor L1 is connected to one end of the resistor R7; the other end of the inductor L2 is connected to one end of the resistor R8; the other end of the resistor R7 is connected to the collector of the NPN transistor Q9 and the other end of the capacitor C7; the other end of the resistor R8 is connected to the collector of the NPN transistor Q10 and the other end of the capacitor C8; the emitter of the NPN transistor Q9 is connected to one end of the capacitor C6, one end of the resistor R9 and the positive end of the current source I7; the emitter of the NPN transistor Q10 is connected to the other end of the capacitor C6, the other end of the resistor R9 and the positive end of the current source I8.

[0031] Preferably, the loop regulator comprises a tail current circuit and a bias current circuit, wherein the output end of the tail current circuit outputs a tail current I tail , and the bias current circuit is used to adjust the tail current I tail , so that the output signal swing of the loop regulator follows the output signal swing of the equalizer.

[0032] Preferably, the tail current circuit comprises NPN transistors Q11-Q12, inductors L3-L4 and resistors R10-R11; the bias current circuit comprises a variable current source I11 controlled by a low-frequency control signal;

[0033] One end of the inductors L3 and L4 is connected to the power supply voltage VDD; the bases of the NPN transistors Q11 and Q12 are connected to the positive-phase signal input terminal VP and the negative-phase signal input terminal VN respectively; the other end of the inductor L3 is connected to one end of the resistor R10; the other end of the inductor L4 is connected to one end of the resistor R11; the other end of the resistor R10 is connected to the collector of the NPN transistor Q11; the other end of the resistor R11 is connected to the collector of the NPN transistor Q12; the emitters of the NPN transistors Q11 and Q12 are connected to the positive end of the variable current source I11 and output the tail current I tail .

[0034] Preferably, the loop regulator further comprises a negative capacitance circuit, which is used to expand the bandwidth of the output signal.

[0035] Preferably, the negative capacitance circuit comprises NPN transistors Q13 and Q14, current sources I9 and I10 and a capacitor C9;

[0036] The negative terminal of the current source I9, I10 is connected to ground; the collector of the NPN transistor Q13 and the base of the NPN transistor Q14 are commonly connected to the other terminal of the resistor R10; the collector of the NPN transistor Q14 and the base of the NPN transistor Q13 are commonly connected to the other terminal of the resistor R11; the emitter of the NPN transistor Q13 is connected to one terminal of the capacitor C9 and the positive terminal of the current source I9; the emitter of the NPN transistor Q14 is connected to the other terminal of the capacitor C9 and the positive terminal of the current source I10.

[0037] Preferably, the loop regulator further comprises a capacitive load CL, which is a variable load controlled by a high-frequency control signal, and one terminal of the capacitive load CL is connected to the other terminal of the resistor R10.

[0038] The application provides a double-loop adaptive equalizer circuit based on power comparison, which uses a digital control signal as a high-frequency / low-frequency control signal, reduces the power consumption of the control circuit, improves the stability of the control precision, and is not affected by external factors; compared with a traditional adaptive equalization method based on spectrum equalization, the application adjusts the equalization capability of the equalizer by detecting the power difference of a signal in the same frequency band through two same power detectors, instead of adjusting the equalization frequency f m As high-frequency and low-frequency power detectors of the cutoff frequency, the application reduces the influence of the performance of the power detection circuit on the control precision; compared with a traditional adaptive equalization method based on slope detection, the application adjusts the equalization capability of the equalizer by detecting the power information in the frequency domain, instead of the slope information in the time domain in the traditional method, avoids the limitation of the precision of the detection circuit by the parasitic capacitance of the node, and has passed the tape-out verification. Therefore, the adaptive equalizer of the application is not easily affected by external factors and has good equalization capability. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of the application. Other embodiments and many of the intended advantages of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0040] Figure 1 is a circuit framework diagram of a traditional adaptive equalizer based on spectrum equalization;

[0041] Figure 2 is a circuit framework diagram of a traditional adaptive equalizer based on slope detection;

[0042] Figure 3 is a circuit block diagram of a power comparison based dual-loop adaptive equalizer according to an embodiment of the present application

[0043] Figure 4 is a circuit block diagram of a power comparison based dual-loop adaptive equalizer according to an embodiment of the present application

[0044] Figure 5 is a circuit diagram of a power detector according to an embodiment of the present application

[0045] Figure 6 is a circuit diagram of an equalizer according to an embodiment of the present application

[0046] Figure 7 is a frequency characteristic response curve of an equalizer according to an embodiment of the present application

[0047] Figure 8 is a circuit diagram of a loop regulator according to an embodiment of the present application

[0048] Figure 9 is an output frequency domain response curve of a loop regulator without capacitive load compensation according to an embodiment of the present application

[0049] Figure 10 is an output frequency domain response curve of a loop regulator with capacitive load compensation according to an embodiment of the present application

[0050] Figure 11 is an adaptive equalization control flow chart of a power comparison based dual-loop adaptive equalizer according to an embodiment of the present application

[0051] Meaning of each number in the figure: 1, equalizer; 2, regulating circuit; 21, limiter; 22, loop regulator; 221, tail current circuit; 222, negative capacitance circuit; 223, capacitive load circuit; 224, bias current circuit; 3, output buffer; 4, high frequency adaptive loop; 41, first power detector; 411, low frequency power detector; 4111, low frequency band pass filter; 4112, low frequency rectifier; 412, high frequency power detector; 4121, high frequency band pass filter; 4122, high frequency rectifier; 42, high frequency comparator; 43, high frequency digital controller; 5, low frequency adaptive loop; 51, second power detector; 52, low frequency comparator; 53, low frequency digital controller. DETAILED DESCRIPTION

[0052] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0054] Traditional adaptive equilibrium methods include the following two types, specifically:

[0055] The first type is an adaptive equalization method based on spectrum equalization. Figure 1 The circuit diagram of a traditional adaptive equalizer based on spectrum equalization is shown, such as... Figure 1 As shown, the system includes an equalizer, a low-pass filter, a high-pass filter, an output buffer, a first rectifier, a second rectifier, and a voltage / current converter. The data stream enters the input terminal of the equalizer; the output terminal of the equalizer is simultaneously connected to the input terminals of the low-pass filter, the high-pass filter, and the output terminal of the output buffer; the output terminal of the low-pass filter is connected to the input terminal of the first rectifier; the output terminal of the high-pass filter is connected to the input terminal of the second rectifier; the first and second rectifiers are respectively connected to the two input terminals of the voltage / current converter; the output terminal of the voltage / current converter is connected to the control terminal of the equalizer.

[0056] The core idea of ​​the adaptive equalization method based on spectrum equalization is to analyze the power of the data stream in the frequency domain.

[0057]

[0058] Using a balanced frequency f mThe spectral density function S(x) of an ideal NRZ random data stream is separated into two spectra with the same power. By comparing the power difference between the low-frequency and high-frequency spectra and converting it into analog control signals, the equalization capability of the linear equalizer is adjusted, and finally the power of the two spectra is made equal, thereby achieving optimal compensation.

[0059]

[0060] However, frequency domain power analysis actually focuses on the spectral density function S of the linear equalizer output data stream. EQ (x), which in the frequency domain is related to the dominant pole p of the linear equalizer. EQ Related, and will be affected by it, therefore f m It's difficult to determine. Worse still, f m The cutoff frequencies of the high-pass filter (which intercepts high-frequency energy) and low-pass filter (which intercepts low-frequency energy) used in the adaptive loop directly determine the control accuracy of the adaptive loop. m Any deviation will cause the balancing effect of this adaptive balancing loop to decrease significantly.

[0061] The second type is an adaptive equalization method based on slope detection. Figure 2 The circuit diagram of a traditional slope-detection-based adaptive equalizer is shown, such as... Figure 2 As shown, the system includes an equalizer, a limiter, an output driver, a first slope detector, a second slope detector, and an integrator. Data flows into the input of the equalizer; the output of the equalizer is simultaneously connected to the input of the limiter and the output of the first slope detector; the output of the limiter is simultaneously connected to the input of the output driver and the input of the second slope detector; the first and second slope detectors are simultaneously connected to the two inputs of the integrator; the output of the integrator is connected to the control terminal of the equalizer.

[0062] The core idea of ​​slope-detection-based adaptive equalization is to analyze the slope of data transition edges in the time domain. A limiter generates an output signal with a slope (known to be the slope of the ideal signal), which is then used as a reference for the output signal of a linear equalizer. By comparing the difference in slope between the limiter and the linear equalizer output signals and converting it into an analog control signal, the equalizer's equalization capability is adjusted. Ultimately, the slope of the linear equalizer's output signal is made consistent with the slope of the limiter's output signal, achieving optimal compensation. However, this method achieves adaptive equalization by detecting the signal slope in the time domain, which leads to offset sensitivity issues. Worse still, at high transmission rates, the nodal parasitic capacitance of the slope detector severely limits the accuracy of slope detection.

[0063] Therefore, the application aims to provide an adaptive equalizer circuit which is not easily affected by external factors and has good adaptive equalization capability.

[0064] The application provides a double-loop adaptive equalizer circuit based on power comparison. Figure 3 A circuit framework diagram of the double-loop adaptive equalizer based on power comparison according to an embodiment of the application is shown, Figure 4 A circuit framework diagram of the double-loop adaptive equalizer based on power comparison according to one specific embodiment of the application is shown, as Figure 3 、 Figure 4 as shown, including an equalizer 1, an adjusting circuit 2, an output buffer 3, a high-frequency adaptive loop 4 and a low-frequency adaptive loop 5. The adjusting circuit 2 includes a limiter 21 and a loop adjuster 22; the high-frequency adaptive loop 4 includes a first power detector 41, a high-frequency comparator 42 and a high-frequency digital controller 43; the low-frequency adaptive loop 5 includes a second power detector 51, a low-frequency comparator 52 and a low-frequency digital controller 53; the first power detector 41 and the second power detector 51 each include a band-pass filter (high-pass or low-pass) and a rectifier (high-pass or low-pass). The equalizer 1, the limiter 21 and the output buffer 3 together constitute a main path; the high-frequency adaptive loop 4 and the low-frequency adaptive loop 5 together constitute a feedback path.

[0065] Specifically, the input end of the equalizer 1 inputs a data stream, which in this embodiment can also be a differential data stream. Taking the differential data stream as an example, the differential data stream enters the differential input end of the equalizer 1; the differential output end of the equalizer 1 is connected to the differential input end of the limiter 21 and the differential input end of the first power detector 41 at the same time; the differential output end of the limiter 21 is connected to the differential input end of the output buffer 3 and the differential input end of the loop adjuster 22 at the same time; the differential output end of the loop adjuster 22 is connected to the differential input end of the second power detector 51; the high-frequency power output end P EQ.H of the first power detector 41 is connected to the inverting input end of the high-frequency comparator 42; the low-frequency power output end P EQ.L of the first power detector 41 is connected to the inverting input end of the low-frequency comparator 52; the high-frequency power output end P LR.H of the second power detector 51 is connected to the non-inverting input end of the high-frequency comparator 42; the low-frequency power output end P LR.LThe in-phase input of the low-frequency comparator 52 is connected to the output of the equalizer 1, and the output of the high-frequency comparator 42 is connected to the input of the high-frequency digital controller 43. The output of the low-frequency comparator 52 is connected to the input of the low-frequency digital controller 53. The output of the high-frequency digital controller 43 is connected to the control terminal of the equalizer 1 and the high-frequency control terminal of the loop regulator 22. The output of the low-frequency digital controller 53 is connected to the low-frequency control terminal of the loop regulator 22. The node A signal of the differential output of the equalizer 1 is the output signal of the equalizer 1, and the node B signal of the differential output of the loop regulator 22 is the output signal of the loop regulator 22.

[0066] In the embodiment, due to the amplification of the limiter 21, the difference in low-frequency power between the outputs of the equalizer 1 and the limiter 21 affects the control accuracy of the high-frequency adaptive loop 4. Therefore, a loop regulator 22 is added after the limiter 21. The low-frequency adaptive loop 5 detects the power of the output signals of the equalizer 1 and the loop regulator 22 in the same low-frequency band through the first power detector 41 and the second power detector 51, compares the power difference between the two signals through the low-frequency comparator 52, sends a low-frequency enable signal EN-LF to the low-frequency digital controller 53, and controls the increase or decrease of the five-bit register according to the "0" or "1" of the low-frequency enable signal. Finally, the low-frequency control signal LF signal[4:0] is sent to adjust the low-frequency power of the output signal of the loop regulator 22, so that it follows the low-frequency power of the output signal of the equalizer 1, and ensures that the low-frequency power of the two comparison signals is the same at each time the high-frequency adaptive loop 4 works.

[0067] Since the equalizer 1 and the limiter 21 both generate signals with a sinc 2 (f) spectrum of a random binary data stream.

[0068]

[0069] where P EQ.H is the high-frequency power of the output signal of the equalizer 1, and P Slicer.H is the high-frequency power of the output signal of the limiter 21. The core idea of the high-frequency adaptive loop 4 is to sharpen the signal output by the equalizer 1 using a limiter 21, use the output signal of the limiter 21 as a reference, compare the power difference between the output signal of the limiter 21 and the output signal of the equalizer 1 in the same high-frequency band [f a ,f b ], and convert it into a digital control signal to adjust the equalization capability of the equalizer 1.

[0070] In the embodiment, a loop regulator 22 is added after the limiter 21. The loop regulator 22 can also generate a signal with a sinc 2 (f) spectrum of a random binary data stream.

[0071]

[0072] Where P EQ.H It is the high-frequency power of the output signal of equalizer 1, P LR.H This refers to the high-frequency power of the output signal of the loop regulator 22. The high-frequency adaptive loop 4 uses the first power detector 41 and the second power detector 51 to detect whether the output signals of the equalizer 1 and the loop regulator 22 are in the same high-frequency band [f]. a ,f b The power of the equalizer 1 and the loop regulator 22 are compared by the high-frequency comparator 42. The high-frequency enable signal EN-HF is sent to the high-frequency digital controller 43. The high-frequency digital controller 43 controls the increase or decrease of the four-bit register according to the "0" or "1" of the high-frequency enable signal. Finally, the high-frequency control signal HF signal[3:0] is sent to adjust the high-frequency power of the output signal of equalizer 1 and the output signal of loop regulator 22, so that the high-frequency power of the output signal of equalizer 1 and the output signal of loop regulator 22 are closer to each other and the difference gradually decreases until N=1.

[0073] It should be noted that, in this embodiment, the adjustment method to make the low-frequency power of the output signal of equalizer 1 and the low-frequency power of the output signal of loop regulator 22 tend to be the same is: adjusting the low-frequency power of the output signal of loop regulator 22 to actively approach the low-frequency power of the output signal of equalizer 1. The adjustment method to make the high-frequency power of the output signal of equalizer 1 and the high-frequency power of the output signal of loop regulator 22 tend to be the same is: simultaneously adjusting the high-frequency power of the output signal of loop regulator 22 and the high-frequency power of the output signal of equalizer 1, so that the two are close to each other. However, those skilled in the art should understand that there are three ways to make the high or low frequency power of the output signal of equalizer 1 approach the same as the high or low frequency power of the output signal of loop regulator 22: 1. The high or low frequency power of the output signal of equalizer 1 actively approaches the high or low frequency power of the output signal of loop regulator 22; 2. The high or low frequency power of the output signal of loop regulator 22 actively approaches the high or low frequency power of the output signal of equalizer 1; 3. The high or low frequency power of the output signal of equalizer 1 and the high or low frequency power of the output signal of loop regulator 22 simultaneously and actively approach each other. Therefore, there are 3 × 3 = 9 ways to make the high frequency power and low frequency power of the output signal of equalizer 1 approach the same as the high frequency power and low frequency power of the output signal of loop regulator 22.

[0074] Figure 5 A circuit diagram of a power detector according to a specific embodiment of this application is shown, as follows: Figure 5 As shown, the first power detector 41 and the second power detector 51 have the same structure, each including a low-frequency power detector 411 and a high-frequency power detector 412.

[0075] Specifically, the low-frequency power detector 411 includes a low-frequency band-pass filter 4111 and a low-frequency rectifier 4112, the low-frequency band-pass filter 4111 including NPN transistors Q1-Q4, current sources I1-I3, capacitors C1-C2 and resistors R1-R2; and the low-frequency rectifier 4112 including a capacitor C3.

[0076] One end of the resistors R1 and R2 and the collectors of the NPN transistors Q3 and Q4 are connected to a power supply voltage VDD; the negative terminals of the current sources I1, I2 and I3 and one end of the capacitor C3 are connected to ground; the bases of the NPN transistors Q1 and Q2 are connected to a non-inverted signal input terminal VP and an inverted signal input terminal VN, respectively; the other end of the resistor R1 is connected to the collector of the NPN transistor Q1, one end of the capacitor C1 and the base of the NPN transistor Q3; the other end of the resistor R2 is connected to the collector of the NPN transistor Q2, the other end of the capacitor C1 and the base of the NPN transistor Q4; the emitter of the NPN transistor Q1 is connected to one end of the capacitor C2 and the positive terminal of the current source I1; the emitter of the NPN transistor Q2 is connected to the other end of the capacitor C2 and the positive terminal of the current source I2; and the emitters of the NPN transistors Q3 and Q4 are connected to one end of the capacitor C3 and the positive terminal of the current source I3, and serve as an output terminal.

[0077] When a signal is input, the low-frequency band-pass filter 4111 intercepts the energy of the low-frequency band of the signal, and the filter capacitor C3 of the low-frequency rectifier 4112 converts the energy into a low-frequency average voltage V F (corresponding to C3), and the energy is converted into a low-frequency average voltage V aver.L . Since V aver.L 2 / sC3=P eff.L The output of the low-frequency band-pass filter 4111 can be considered as the low-frequency effective power P eff.L .

[0078] The high-frequency power detector 412 includes a high-frequency band-pass filter 4121 and a high-frequency rectifier 4122, the high-frequency band-pass filter 4121 including NPN transistors Q5-Q8, current sources I4-I6, a capacitor C4 and resistors R3-R6; and the high-frequency rectifier 4122 including a capacitor C5.

[0079] One end of resistors R3 and R4, and the collectors of NPN transistors Q7 and Q8 are simultaneously connected to the power supply voltage VDD; the negative terminals of current sources I4, I5, and I6, and one end of capacitor C5 are simultaneously connected to ground; the bases of NPN transistors Q5 and Q6 are connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN, respectively; the other end of resistor R3 is simultaneously connected to the bases of NPN transistors Q5 and Q7; the other end of resistor R4 is simultaneously connected to the collector of NPN transistor Q6 and the base of NPN transistor Q8; the emitter of NPN transistor Q5 is simultaneously connected to one end of resistor R5 and the positive terminal of current source I4; the emitter of NPN transistor Q6 is simultaneously connected to one end of resistor R6 and the positive terminal of current source I5; the other end of resistor R5 is connected to one end of capacitor C4; the other end of resistor R6 is connected to the other end of capacitor C4; the emitters of NPN transistors Q7 and Q8 are jointly connected to one end of capacitor C5 and the positive terminal of current source I6, serving as the output terminal.

[0080] When a signal is input, the high-frequency band energy of the signal is intercepted by the high-frequency bandpass filter 4121 and then filtered by the filter capacitor C of the high-frequency rectifier 4122. F (Corresponding to C5), converting energy into a high-frequency average voltage V. aver.H Because of V aver.H 2 ·sC F =P eff.H The output of the high-frequency bandpass filter 4121 can be considered as the high-frequency effective power P of the energy within a certain time period. eff.H .

[0081] Figure 6 A circuit diagram of an equalizer according to a specific embodiment of this application is shown, such as... Figure 6 As shown, equalizer 1 includes NPN transistors Q9-Q10, current sources I7-I8, capacitors C6-C8, inductors L1-L2 and resistors R7-R9, where resistor R9 is a variable resistor controlled by the high-frequency control signal HF signal[3:0].

[0082] One end of inductors L1 and L2 is connected to the power supply voltage VDD; the negative terminals of current sources I7 and I8 and one end of capacitors C7 and C8 are connected to ground; the bases of NPN transistors Q9 and Q10 are connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN, respectively; the other end of inductor L1 is connected to one end of resistor R7; the other end of inductor L2 is connected to one end of resistor R8; the other end of resistor R7 is connected to the collector of NPN transistor Q9 and the other end of capacitor C7; the other end of resistor R8 is connected to the collector of NPN transistor Q10 and the other end of capacitor C8; the emitter of NPN transistor Q9 is connected to one end of capacitor C6, one end of resistor R9, and the positive terminal of current source I7; the emitter of NPN transistor Q10 is connected to the other end of capacitor C6, the other end of resistor R9, and the positive terminal of current source I8. The other ends of capacitors C7 and C8 serve as the output terminals.

[0083] In this embodiment, equalizer 1 adopts an emitter degenerate structure, and its transfer function is:

[0084]

[0085] The switching on and off of the MOSFET in the variable resistor R9 is controlled by the high-frequency control signal HF signal[3:0], thereby controlling the emitter resistor R. E The adjustment (corresponding to R9) is achieved by adjusting the emitter resistance R. E The resistance value is adjusted to change the transmission characteristics of equalizer 1, so as to match the channel attenuation and achieve optimal compensation.

[0086] Figure 7 The following diagram illustrates the frequency response curve of an equalizer according to a specific embodiment of this application: Figure 7 As shown, with the increase of the high-frequency control signal (HF signal), the emitter resistor value gradually decreases, and the boost factor decreases; conversely, with the decrease of the high-frequency control signal, the emitter resistor value gradually increases, and the boost factor increases. The equalizer 1 of this application has sufficiently high linearity, and its output signal swing |V out.EQ |for:

[0087]

[0088] The change in emitter resistance alters the low-frequency gain of the equalizer, causing the swing of the equalizer 1 output signal to change accordingly.

[0089] Figure 8 A circuit diagram of a loop regulator according to a specific embodiment of this application is shown, such as Figure 8As shown, the loop regulator 22 comprises a tail current circuit 221, a negative capacitance circuit 222, a capacitive load circuit 223 and a bias current circuit 224. Among them, the tail current circuit 221 outputs a tail current I tail at the output end as the main circuit of the loop regulator 22; the bias current circuit 224 is used to adjust the tail current I tail , so that the output signal swing of the loop regulator 22 follows the output signal swing of the equalizer 1; the negative capacitance circuit 222 is used to expand the bandwidth of the signal; and the capacitive load circuit 223 is used to optimize the high frequency component of the signal.

[0090] Specifically, the tail current circuit 221 comprises NPN transistors Q11-Q12, inductors L3-L4 and resistors R10-R11; the negative capacitance circuit 222 comprises NPN transistors Q13, Q14, current sources I9, I10 and a capacitor C9; the capacitive load circuit 223 comprises a capacitive load CL; and the bias current circuit 224 comprises a variable current source I11 controlled by a low frequency control signal LF Signal[4:0].

[0091] One end of the inductors L3, L4 is connected to the power supply voltage VDD; the negative ends of the current sources I9, I10 and I11 are connected to the ground; the base of the NPN transistor Q11 is connected to the same phase signal input end VP; the base of the NPN transistor Q12 is connected to the opposite phase signal input end VN; the other end of the inductor L3 is connected to one end of the resistor R10; the other end of the inductor L4 is connected to one end of the resistor R11; the other end of the resistor R10 is connected to the collector of the NPN transistor Q11, the collector of the NPN transistor Q13, the base of the NPN transistor Q14 and one end of the capacitive load CL; the other end of the resistor R11 is connected to the collector of the NPN transistor Q12, the collector of the NPN transistor Q14, the base of the NPN transistor Q13 and the other end of the capacitive load CL; the emitter of the NPN transistor Q13 is connected to one end of the capacitor C9 and the positive end of the current source I9; the emitter of the NPN transistor Q14 is connected to the other end of the capacitor C9 and the positive end of the current source I10; and the emitters of the NPN transistors Q11 and Q12 are connected to the positive end of the variable current source I11. Among them, the two ends of the capacitive load CL serve as the output end.

[0092] In this embodiment, since the limiter 21 of the previous stage of the loop regulator 22 has a large gain, it will amplify the signal to the limiting state. Therefore, the input of the loop regulator 22 is also a limiting signal, and the output signal swing of the loop regulator 22 is determined by the load (corresponding to the resistor R10 or R11) and the tail current (I tail +I tail.NC ), and the swing |V out.LR | of the output signal is:

[0093]

[0094] The tail current I tail of the loop regulator 22 is adjusted by controlling the on-off of the MOS transistor in the bias current circuit 224 through the low frequency control signal LF signal[4:0], and the output swing of the loop regulator 22 is changed by adjusting the tail current I tail of the loop regulator 22, so that it follows the output swing of the equalizer 1, and ensures that the output swing of the equalizer 1 and the output swing of the loop regulator 22 are the same at each time the high frequency adaptive loop 4 works.

[0095] Due to the inductance and negative capacitance effect in the loop regulation path, a high frequency gain peak (△Gain) appears in the frequency response of the loop regulation path. When the equalizer 1 increases the boost factor by increasing the resistance value of the emitter resistor to compensate for the high frequency channel attenuation, the high frequency gain peak will increase, and the high frequency component of the output signal of the loop regulator 22 is over-compensated as the reference of the high frequency adaptive loop 4. Specifically, Figure 9 the output frequency domain response curve of the loop regulator without capacitive load compensation according to one embodiment of the present application is shown, as Figure 9 indicated.

[0096] To solve this problem, the embodiment adds a capacitive load CL controlled by a high frequency control signal HF signal[3:0] at the output end of the loop regulator 22 to ensure that the best high frequency response can be obtained under all equalization conditions, but this design will sacrifice a certain bandwidth. Specifically, Figure 10 the output frequency domain response curve of the loop regulator with capacitive load compensation according to one embodiment of the present application is shown, as Figure 10 indicated.

[0097] Based on the above-mentioned power comparison-based double-loop adaptive equalizer circuit, the embodiment also provides an equalization method.

[0098] Figure 11 the adaptive equalization control flowchart of the power comparison-based double-loop adaptive equalizer according to one embodiment of the present application is shown, as Figure 11 indicated, which includes two adaptive loops: a low frequency adaptive loop and a high frequency adaptive loop.

[0099] The low frequency adaptive loop controls the low frequency power P B.L of the output signal of the loop regulator through a 5-bit register to send a low frequency control signal LF signal[4:0], and initializes the low frequency control signal LF signal[4:0] =

[11111] . Then the low frequency power P A.Lthe low frequency power P of the output signal of the loop regulator B.L is adjusted according to the difference between the low frequency power P of the output signal of the loop regulator B.L and the low frequency power P of the output signal of the equalizer B.L . Specifically, when the low frequency power P of the output signal of the loop regulator A.L is less than the low frequency power P of the output signal of the equalizer B.L , the low frequency enable signal EN-LF=0, the low frequency control signal is increased by one, so that the low frequency power P of the output signal of the loop regulator B.L is increased; when the low frequency power P of the output signal of the loop regulator A.L is greater than the low frequency power P of the output signal of the equalizer B.L , the low frequency enable signal EN-LF=1, the low frequency control signal is decreased by one, so that the low frequency power P of the output signal of the loop regulator B.L is decreased. Finally, the low frequency power P of the output signal of the loop regulator A.L follows the low frequency power P of the output signal of the equalizer

[0100] The high frequency adaptive loop simultaneously controls the high frequency power P of the output signal of the equalizer A.H and the high frequency power P of the output signal of the loop regulator B.H by sending a high frequency control signal HF signal[3:0] through a 4-bit register and initializing the high frequency control signal HF signal[3:0]=

[1111] . Then, the high frequency power P of the output signal of the equalizer A.H and the high frequency power P of the output signal of the loop regulator B.H are simultaneously adjusted according to the difference between the high frequency power P of the output signal of the equalizer A.H and the high frequency power P of the output signal of the loop regulator B.H . Specifically, when the high frequency power P of the output signal of the equalizer A.H is less than the high frequency power P of the output signal of the loop regulator B.H , the high frequency enable signal EN-HF=1, the high frequency control signal is decreased by one, so that the high frequency power P of the output signal of the equalizer A.H is increased, while the high frequency power P of the output signal of the loop regulator B.H is decreased; when the high frequency power P of the output signal of the equalizer A. is greater than the high frequency power P of the output signal of the loop regulator B.H , the high frequency enable signal EN-HF=0, the high frequency control signal is increased by one, so that the high frequency power P of the output signal of the equalizer A.H is decreased, while the high frequency power P of the output signal of the loop regulator B.H is increased. Finally, the high frequency power P of the output signal of the equalizer A.HThe low-frequency power P of the output signal of the loop regulator B.H .

[0101] Meanwhile, in order to avoid the two adaptive loops from conflicting with each other and failing to converge to a proper position, the low-frequency adaptive loop and the high-frequency adaptive loop use different clocks to stagger the two adaptive loops. In this embodiment, the high-frequency adaptive loop works once, and the low-frequency adaptive loop works sixteen times.

[0102] The application provides a double-loop adaptive equalizer circuit based on power comparison, adopts a digital control signal as a high-frequency / low-frequency control signal, reduces the power consumption of a control circuit, improves the stability of control precision, and is not affected by external factors; compared with a traditional adaptive equalization method based on spectrum equalization, the application adjusts the equalization capability of an equalizer by detecting the power difference of a signal in the same frequency band through two same power detectors, replaces the traditional method of adjusting the equalization capability of an equalizer by adjusting the balance frequency f m The high-frequency and low-frequency power detectors with the cutoff frequency reduce the influence of the performance of a power detection circuit on control precision; compared with a traditional adaptive equalization method based on slope detection, the application adjusts the equalization capability of an equalizer by detecting power information in the frequency domain, replaces the slope information in the time domain in the traditional method, avoids the precision of a detection circuit being limited by a node parasitic capacitor, and has passed the flow verification. Therefore, the adaptive equalizer is not easily affected by external factors, and has good equalization capability.

[0103] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the application without departing from the spirit and scope of the application. In this way, if these modifications and changes are within the scope of the claims of the application and their equivalents, the application also aims to cover these modifications and changes. The word "comprises" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are described in mutually different dependent claims does not mean that the combination of these measures cannot be used to advantage. Any reference signs in the claims should not be considered as limiting the scope.

Claims

1. A dual-loop adaptive equalizer circuit based on power comparison, characterized in that, include: An equalizer, wherein a differential data stream is input to the input terminal of the equalizer; An adjustment circuit, wherein the input terminal of the adjustment circuit is electrically connected to the output terminal of the equalizer; A high-frequency adaptive loop is used to detect the high-frequency power and low-frequency power of the output signal of the equalizer; A low-frequency adaptive loop is used to detect the high-frequency power and low-frequency power of the output signal of the regulation circuit; The high-frequency adaptive loop and the low-frequency adaptive loop respectively compare the high-frequency power and low-frequency power of the output signals of the equalizer and the adjustment circuit, and generate high-frequency control signals and low-frequency control signals accordingly, thereby adjusting the high-frequency power and / or low-frequency power of the output signals of the equalizer and / or the adjustment circuit, so that the high-frequency power and low-frequency power of the output signals of the equalizer and the adjustment circuit tend to be the same. The regulating circuit includes: A limiter, wherein the input terminal of the limiter is electrically connected to the output terminal of the equalizer; A loop regulator, wherein the input terminal of the loop regulator is electrically connected to the output terminal of the limiter; The high-frequency adaptive loop generates a high-frequency control signal by comparing the high-frequency power of the output signal of the equalizer and the output signal of the adjustment circuit, and simultaneously feeds it back to the equalizer and the loop regulator; the low-frequency adaptive loop generates a low-frequency control signal by comparing the low-frequency power of the output signal of the equalizer and the output signal of the adjustment circuit, and feeds it back to the loop regulator.

2. The dual-loop adaptive equalizer circuit based on power comparison according to claim 1, characterized in that, The high-frequency adaptive loop includes a first power detector, a high-frequency comparator, and a high-frequency digital controller; the low-frequency adaptive loop includes a second power detector, a low-frequency comparator, and a low-frequency digital controller. The input terminal of the first power detector is electrically connected to the output terminal of the equalizer, and the input terminal of the second power detector is electrically connected to the output terminal of the loop regulator. The high-frequency power output terminal and the low-frequency power output terminal of the first power detector and the second power detector are respectively electrically connected to the input terminal of the high-frequency comparator and the input terminal of the low-frequency comparator. The output terminal of the high-frequency comparator is electrically connected to the input terminal of the high-frequency digital controller. The output terminal of the high-frequency digital controller is simultaneously electrically connected to the control terminal of the equalizer and the high-frequency control terminal of the loop regulator. The output terminal of the low-frequency comparator is electrically connected to the input terminal of the low-frequency digital controller, and the output terminal of the low-frequency digital controller is electrically connected to the low-frequency control terminal of the loop regulator.

3. The dual-loop adaptive equalizer circuit based on power comparison according to claim 2, characterized in that, Both the first power detector and the second power detector include a low-frequency power detector and a high-frequency power detector. The low-frequency power detector includes a low-frequency bandpass filter and a low-frequency rectifier, and the high-frequency power detector includes a high-frequency bandpass filter and a high-frequency rectifier.

4. The dual-loop adaptive equalizer circuit based on power comparison according to claim 3, characterized in that, The low-frequency bandpass filter includes NPN transistors Q1-Q4, current sources I1-I3, capacitors C1-C2, and resistors R1-R2; One end of resistors R1 and R2, and the collectors of NPN transistors Q3 and Q4 are simultaneously connected to the power supply voltage VDD; the negative terminals of current sources I1, I2, and I3 are simultaneously connected to ground; the bases of NPN transistors Q1 and Q2 are respectively connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN; the other end of resistor R1 is simultaneously connected to the collector of NPN transistor Q1, one end of capacitor C1, and the base of NPN transistor Q3; the other end of resistor R2 is simultaneously connected to the collector of NPN transistor Q2, the other end of capacitor C1, and the base of NPN transistor Q4; the emitter of NPN transistor Q1 is simultaneously connected to one end of capacitor C2 and the positive terminal of current source I1; the emitter of NPN transistor Q2 is simultaneously connected to the other end of capacitor C2 and the positive terminal of current source I2; the emitters of NPN transistors Q3 and Q4 are both connected to the positive terminal of current source I3.

5. The dual-loop adaptive equalizer circuit based on power comparison according to claim 3, characterized in that, The high-frequency bandpass filter includes NPN transistors Q5-Q8, current sources I4-I6, capacitor C4, and resistors R3-R6; One end of resistors R3 and R4, and the collectors of NPN transistors Q7 and Q8 are simultaneously connected to the power supply voltage VDD; the negative terminals of current sources I4, I5, and I6 are simultaneously connected to ground; the bases of NPN transistors Q5 and Q6 are respectively connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN; the other end of resistor R3 is simultaneously connected to the collector of NPN transistor Q5 and the base of NPN transistor Q7; the other end of resistor R4 is simultaneously connected to the collector of NPN transistor Q6 and the base of NPN transistor Q8; the emitter of NPN transistor Q5 is simultaneously connected to one end of resistor R5 and the positive terminal of current source I4; the emitter of NPN transistor Q6 is simultaneously connected to one end of resistor R6 and the positive terminal of current source I5. The other end of resistor R5 is connected to one end of capacitor C4; the other end of resistor R6 is connected to the other end of capacitor C4; the emitters of NPN transistors Q7 and Q8 are connected to the positive terminal of current source I6.

6. The dual-loop adaptive equalizer circuit based on power comparison according to claim 1, characterized in that, The equalizer includes NPN transistors Q9-Q10, current sources I7-I8, capacitors C6-C8, inductors L1-L2 and resistors R7-R9, wherein resistor R9 is a variable resistor controlled by a high-frequency control signal. One end of each inductor L1 and L2 is connected to the power supply voltage VDD; the negative terminals of current sources I7 and I8 and one end of each capacitor C7 and C8 are connected to ground; the bases of NPN transistors Q9 and Q10 are connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN, respectively; the other end of inductor L1 is connected to one end of resistor R7; the other end of inductor L2 is connected to one end of resistor R8; the other end of resistor R7 is simultaneously connected to the collector of NPN transistor Q9 and the other end of capacitor C7; the other end of resistor R8 is simultaneously connected to the collector of NPN transistor Q10 and the other end of capacitor C8; the emitter of NPN transistor Q9 is simultaneously connected to one end of capacitor C6, one end of resistor R9, and the positive terminal of current source I7; the emitter of NPN transistor Q10 is simultaneously connected to the other end of capacitor C6, the other end of resistor R9, and the positive terminal of current source I8.

7. The dual-loop adaptive equalizer circuit based on power comparison according to claim 1, characterized in that, The loop regulator includes a tail current circuit and a bias current circuit, wherein the output terminal of the tail current circuit outputs a tail current Itail, and the bias current circuit is used to adjust the tail current Itail so that the output signal swing of the loop regulator follows the output signal swing of the equalizer.

8. The dual-loop adaptive equalizer circuit based on power comparison according to claim 7, characterized in that, The tail current circuit includes NPN transistors Q11-Q12, inductors L3-L4, and resistors R10-R11; the bias current circuit includes a variable current source I11 controlled by a low-frequency control signal. One end of each inductor L3 and L4 is connected to the power supply voltage VDD; the bases of NPN transistors Q11 and Q12 are connected to the non-inverting signal input terminal VP and the inverting signal input terminal VN, respectively; the other end of inductor L3 is connected to one end of resistor R10; the other end of inductor L4 is connected to one end of resistor R11; the other end of resistor R10 is connected to the collector of NPN transistor Q11; the other end of resistor R11 is connected to the collector of NPN transistor Q12; the emitters of NPN transistors Q11 and Q12 jointly output the tail current Itail and are connected to the positive terminal of the variable current source I11.

9. The dual-loop adaptive equalizer circuit based on power comparison according to claim 8, characterized in that, The loop regulator also includes a negative capacitor circuit, which is used to extend the bandwidth of the output signal.

10. The dual-loop adaptive equalizer circuit based on power comparison according to claim 9, characterized in that, The negative capacitor circuit includes NPN transistors Q13 and Q14, current sources I9 and I10, and capacitor C9. The negative terminals of current sources I9 and I10 are simultaneously connected to ground; the collector of NPN transistor Q13 and the base of NPN transistor Q14 are both connected to the other end of resistor R10; the collector of NPN transistor Q14 and the base of NPN transistor Q13 are both connected to the other end of resistor R11; the emitter of NPN transistor Q13 is simultaneously connected to one end of capacitor C9 and the positive terminal of current source I9; the emitter of NPN transistor Q14 is simultaneously connected to the other end of capacitor C9 and the positive terminal of current source I10.

11. The dual-loop adaptive equalizer circuit based on power comparison according to claim 8, characterized in that, The loop regulator also includes a capacitive load CL, which is a variable load controlled by a high-frequency control signal, and one end of the capacitive load CL is connected to the other end of the resistor R10.

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