Data packet forwarding system and method, storage medium

Abstract

The disclosure provides a data packet forwarding system and method and a storage medium, relates to the technical field of network communication, and can be applied to the scene of forwarding data packets. The data packet forwarding system comprises an FPGA and a network adapter, the network adapter is used for connecting the FPGA with a server in communication, the FPGA comprises: a packet analysis circuit unit, which is used for analyzing a received to-be-forwarded data packet and extracting a packet type from an analysis result, and generating a packet type signal based on the packet type; a path determination circuit unit, which is used for searching for target port information matched with the to-be-forwarded data packet from a bridge mode register when the packet type is determined to be an ARP type according to the packet type signal, and generating a target port signal according to the target port information; and a packet forwarding circuit unit, which is used for forwarding the to-be-forwarded data packet according to the target port signal. The technical scheme of the embodiment of the disclosure can avoid the time delay and jitter in the data packet forwarding process.

Description

Technical Field

[0001] This disclosure relates to the field of network communication technology, and more specifically, to a data packet forwarding system, a data packet forwarding method, and a computer-readable storage medium. Background Technology

[0002] With the continuous growth of network traffic, especially multimedia traffic, users have increasingly higher requirements for network service quality. Data exchange services play a crucial role in network service quality, and the computing power of switching equipment directly affects the quality of data exchange services.

[0003] In data exchange implementation schemes, high-speed packet forwarding can be achieved at the software level using frameworks such as DPDK (Data Plane Development Kit) or VPP (Vector Packet Processing). Although these methods are flexible, they all require data to be transferred to the CPU (Central Processing Unit) for processing before being sent down. The transmission process is prone to latency and jitter, which affects the performance of data packet forwarding.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a data packet forwarding system, a data packet forwarding method, and a computer-readable storage medium, thereby at least to some extent overcoming the problem in the related art that latency and jitter easily occur during data packet forwarding, affecting data packet forwarding performance.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to a first aspect of the present disclosure, a data packet forwarding system is provided, the data packet forwarding system including a field-programmable gate array (FPGA) and a network adapter, the network adapter being used to communicatively connect the FPGA to a server; the FPGA including a packet parsing circuit unit, a path determination circuit unit, a packet forwarding circuit unit, and a bridge mode register;

[0008] The message parsing circuit unit is used to parse the received data packets to be forwarded, extract the message type of the data packets to be forwarded from the parsing result, and generate a message type signal based on the message type and send it to the path determination circuit unit.

[0009] When the packet type is determined to be Address Resolution Protocol (ARP) based on the packet type signal, the path determination circuit unit searches for target port information matching the data packet to be forwarded in the bridge mode register, and generates a target port signal based on the target port information and sends it to the packet forwarding circuit unit.

[0010] The message forwarding circuit unit is used to forward the data message to be forwarded according to the target port signal.

[0011] In some example embodiments of this disclosure, based on the foregoing scheme, the message parsing circuit unit is further configured to extract the message header information of the data packet to be forwarded from the parsing result, and generate a first message header signal based on the message header information and send it to the path determination circuit unit;

[0012] The path determination circuit unit is further configured to, when determining that the message type is a non-ARP type based on the message type signal, obtain a target flow table matching the message header information based on the received first message header signal, determine message header modification information based on the target flow table, modify the message header information of the data packet to be forwarded based on the message header modification information, and generate a second message header signal based on the modified message header information and send it to the message forwarding circuit unit.

[0013] The message forwarding circuit unit is also used to obtain the target port information in the second message header signal, and forward the modified data message to be forwarded according to the target port information in the second message header signal.

[0014] In some exemplary embodiments of this disclosure, based on the foregoing scheme, the message forwarding circuit unit includes a first forwarding sub-circuit unit and a second forwarding sub-circuit unit;

[0015] The first forwarding sub-circuit unit is used to send the data packet to be forwarded to the server through the network adapter when it is determined from the target port signal that the target port points to the server.

[0016] The second forwarding sub-circuit unit is used to forward the data packet to be forwarded to the optical fiber interface when the target port is determined to point to the optical fiber interface based on the target port signal.

[0017] In some example embodiments of this disclosure, based on the foregoing scheme, the second forwarding sub-circuit unit is specifically used to forward the data packet to be forwarded to the optical fiber interface after performing QoS processing.

[0018] In some example embodiments of this disclosure, based on the foregoing scheme, the path determination circuit unit, when obtaining the target flow table matching the header information based on the received first header signal, is specifically used to: perform a Tri-State Content Addressing Memory (TCAM) query based on the header information in the first header signal, and match the target flow table from the server memory according to the query result and the header information.

[0019] In some example embodiments of this disclosure, based on the foregoing scheme, the message header information includes five-tuple information, which includes the source Internet Protocol IP address, source port, destination IP address, destination port, and transport layer protocol.

[0020] In some example embodiments of this disclosure, based on the foregoing scheme, the FPGA further includes a message preprocessing circuit unit;

[0021] The message preprocessing circuit unit is used to receive the data message to be forwarded, perform maximum transmission unit (MTU) detection on the data message to be forwarded, and input the data message to be forwarded that passes the detection into the message parsing circuit unit.

[0022] In some example embodiments of this disclosure, based on the foregoing scheme, the FPGA further includes a message buffer circuit unit;

[0023] The message caching circuit unit is used to cache the data packets to be forwarded transmitted by the message preprocessing circuit unit.

[0024] According to a second aspect of the present disclosure, a data packet forwarding method is provided, applied to the data packet forwarding system described in any one of the preceding claims, the method comprising:

[0025] The received data packets to be forwarded are parsed, and the packet type of the data packets to be forwarded is extracted from the parsing results;

[0026] In response to the message type being Address Resolution Protocol (ARP) type, the target port information matching the data packet to be forwarded is determined from the bridge mode register;

[0027] The data packet to be forwarded is forwarded according to the target port information.

[0028] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein when executed by a processor, the computer program implements the data packet forwarding method according to any one of the preceding claims.

[0029] The data packet forwarding system, method, and storage medium provided in this disclosure use the packet parsing circuit unit of an FPGA (Field Programmable Gate Array) to parse the received data packets to be forwarded. The parsing result extracts the packet type of the data packet to be forwarded, and a packet type signal is generated based on this packet type and sent to the path determination circuit unit of the FPGA. When the path determination circuit unit determines that the packet type is ARP (Address Resolution Protocol) based on the packet type signal, it searches for target port information matching the data packet to be forwarded in the bridge mode register, and generates a target port signal based on the target port information and sends it to the packet forwarding circuit unit of the FPGA. The packet forwarding circuit unit forwards the data packet to be forwarded based on the target port signal. On the one hand, from a hardware perspective, FPGA is used to implement data packet processing and forwarding. The forwarding and processing of data packets hardly rely on the CPU. Moreover, since the hardware design on the FPGA is a multi-concurrency pipeline, it can avoid latency and jitter problems caused by server CPU multi-core performance allocation, operating system interrupts, context switching, etc. On the other hand, for ARP type data packets to be forwarded, the target port information matching the data packet can be directly found from the bridge mode register, without having to obtain it by looking up the flow table, thus improving the forwarding efficiency of data packets.

[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0032] Figure 1 The schematic diagram illustrates the structure of a data packet forwarding system according to some embodiments of the present disclosure;

[0033] Figure 2This illustration schematically shows a structural diagram of another data packet forwarding system according to some embodiments of the present disclosure;

[0034] Figure 3 This schematic diagram illustrates the working principle of a data packet forwarding system according to some embodiments of the present disclosure;

[0035] Figure 4 This illustration schematically shows a workflow diagram of a data packet forwarding system according to some embodiments of the present disclosure;

[0036] Figure 5 The illustration shows a flowchart of a data packet forwarding method according to some embodiments of the present disclosure;

[0037] Figure 6 A schematic diagram of a computer-readable storage medium according to some embodiments of the present disclosure is shown.

[0038] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0040] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0041] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0042] In this embodiment, the high performance, programmability, and easy upgradeability of FPGAs are utilized to push the control and forwarding layers of SDN (Software-Defined Network) down to hardware. The software management layer, which performs calculations on the CPU, is only responsible for tasks such as flow table distribution and statistics. The FPGA hardware layer implements tasks such as parsing, modifying, and packaging data packets, as well as matching ACLs (Access Control Lists) and QoS (Quality of Service).

[0043] In the example embodiments disclosed herein, a data packet forwarding system is first provided. Figure 1 This illustration schematically shows a data packet forwarding system structure according to some example embodiments of the present disclosure, with reference to... Figure 1 As shown, the data packet forwarding system 10 may include an FPGA 11 and a network adapter 12. The network adapter 12 is used to connect the FPGA 11 to a server for communication. The FPGA 11 may include a packet parsing circuit unit 111, a path determination circuit unit 112, a packet forwarding circuit unit 113, and a bridge mode register 114. Wherein:

[0044] The message parsing circuit unit 111 can be used to parse the received data packets to be forwarded, extract the message type of the data packets to be forwarded from the parsing result, and generate a message type signal based on the message type and send it to the path determination circuit unit 112; the path determination circuit unit 112 can be used to find the target port information matching the data packets to be forwarded from the bridge mode register 114 when the message type is determined to be ARP type according to the message type signal, and generate a target port signal based on the target port information and send it to the message forwarding circuit unit 113; the message forwarding circuit unit 113 can be used to forward the data packets to be forwarded according to the target port signal.

[0045] The data packet forwarding system provided in this example embodiment, on the one hand, uses an FPGA to implement data packet processing and forwarding from a hardware perspective, without relying on a CPU. Moreover, since the hardware design on the FPGA is a multi-concurrency pipeline, it can avoid latency and jitter problems caused by CPU multi-core performance allocation, operating system interrupts, and context switching in servers. On the other hand, for ARP type data packets to be forwarded, the target port information matching the data packet can be directly found from the bridge mode register, without needing to obtain it by looking up the flow table, thus improving the forwarding efficiency of data packets.

[0046] In one example embodiment, reference Figure 1As shown, the message parsing circuit unit 111 can also be used to extract the message header information of the data packet to be forwarded from the parsing result, and generate a first message header signal based on the message header information and send it to the path determination circuit unit 112; the path determination circuit unit 112 can also be used to obtain a target flow table that matches the message header information of the data packet to be forwarded based on the received first message header signal when the message type is determined to be a non-ARP type based on the message type signal, determine the message header modification information based on the target flow table, modify the message header information of the data packet to be forwarded based on the message header modification information, and generate a second message header signal based on the modified message header information and send it to the message forwarding circuit unit 113; the message forwarding circuit unit 113 can also be used to obtain the target port information in the second message header signal and forward the modified data packet to be forwarded based on the target port information in the second message header signal.

[0047] For example, when the path determination circuit unit 112 obtains the target flow table that matches the message header information based on the received first message header signal, it can specifically be used to: perform a TCAM (Ternary Content Addressable Memory) query based on the message header information in the first message header signal, and match the target flow table from the server memory according to the query result and the message header information.

[0048] In one example embodiment, the message header information may include 5-tuple information, which includes the source IP (Internet Protocol) address, source port, destination IP address, destination port, and transport layer protocol.

[0049] In one example embodiment, the message forwarding circuit unit 113 may include a first forwarding sub-circuit unit and a second forwarding sub-circuit unit. Specifically: the first forwarding sub-circuit unit can be used to send the data packet to be forwarded to the server via the network adapter 12 when the target port is determined to point to the server based on the target port signal; the second forwarding sub-circuit unit can be used to forward the data packet to be forwarded to the fiber optic interface pointed to by the target port when the target port is determined to point to the fiber optic interface based on the target port signal.

[0050] For example, the second forwarding sub-circuit unit may perform QoS processing on the data packet to be forwarded before forwarding it to the fiber optic interface pointed to by the target port. For example, the QoS processing on the data packet to be forwarded may include at least one of queue management, queue scheduling, and congestion control.

[0051] based on Figure 1 The corresponding data packet forwarding system in the embodiment, Figure 2This schematically illustrates a structural diagram of another data packet forwarding system according to some example embodiments of the present disclosure, with reference to... Figure 2 As shown, the data packet forwarding system 20 may include an FPGA 21 and a network adapter 22. The network adapter 22 can be used to connect the FPGA 21 to a server for communication. The FPGA 21 may include a packet parsing circuit unit 211, a path determination circuit unit 212, a packet forwarding circuit unit 213, a bridge mode register 214, and a packet preprocessing circuit unit 215. The working principles and functions of the network adapter 22, packet parsing circuit unit 211, path determination circuit unit 212, packet forwarding circuit unit 213, and bridge mode register 214 are as follows: Figure 1 The network adapter 12, packet parsing circuit unit 111, path determination circuit unit 112, packet forwarding circuit unit 113, and bridge mode register 114 in the corresponding embodiment are one-to-one, as detailed above. Figure 1 The description of the corresponding embodiments will not be repeated here.

[0052] The message preprocessing circuit unit 215 can be used to receive data packets to be forwarded, perform MTU (Maximum Transmission Unit) detection on the received data packets to be forwarded, and input the data packets to be forwarded that pass the detection to the message parsing circuit unit 211.

[0053] In one example embodiment, FPGA 21 may further include a message buffer unit, which can be used to buffer the data packets to be forwarded transmitted by message preprocessing circuit unit 215.

[0054] In one exemplary embodiment of this disclosure, the above Figure 1 , Figure 2 The data packet forwarding system in the corresponding embodiment may also include a server, for example, which may be a general-purpose x86 server.

[0055] In one example embodiment of this disclosure, the FPGA and network adapter described above can be integrated into a server.

[0056] Based on the above Figure 1 , Figure 2 The data packet forwarding system in the corresponding embodiment will be further illustrated below.

[0057] Figure 3 This schematic diagram illustrates the operation of a data packet forwarding system according to some example embodiments of the present disclosure, with reference to... Figure 3As shown, the data packet forwarding system may include an FPGA 31 and a network adapter 32. The FPGA 31 can communicate with the server's CPU via the network adapter 32. The network adapter 32 can receive data packets that need to be processed by the FPGA 31 and then sent to the server's CPU for further processing. The data packets that the server needs to send can be sent to the FPGA 31 for processing. The function of exchanging data packets between the network adapter 32's buffer and the server's memory does not need to be implemented on the FPGA 31. The FPGA 31 can implement a complete data packet processing mechanism, including the parsing, processing, packaging, and sending of data packets to be forwarded. The CPU is used to control the forwarding mode of the FPGA 31 and the network adapter 32, as well as the distribution and statistics of flow tables. The forwarding traffic of data packets mainly depends on the FPGA 31 rather than the CPU. For example, the CPU can also monitor the operating status of the data packet forwarding system. The FPGA 31 may include a message parsing circuit unit 311, a path determination circuit unit 312, a message forwarding circuit unit 313, a bridge mode register 314, and a message preprocessing circuit unit 315. The message preprocessing circuit unit 315 may include a MUX (multiplexer, data selector) and a maximum transmission unit (MTU). The path determination circuit unit 312 may include a lookup table sub-circuit unit and a message header modification sub-circuit unit. The message forwarding circuit unit 313 may include a first forwarding sub-circuit unit and a second forwarding sub-circuit unit.

[0058] based on Figure 3 The working principle diagram shown is as follows. Figure 4 This illustration schematically depicts the workflow of a data packet forwarding system according to some example embodiments of the present disclosure, with reference to... Figure 4 As shown, the workflow may include the following steps S410 to S480.

[0059] In step S410, data packets are preprocessed.

[0060] Data packets to be forwarded sent by the CPU or received by the fiber optic port are input into the FPGA 31 for processing and forwarding. Data packets to be forwarded sent by the CPU can be input into the FPGA 31 as a data stream via the network adapter 32, while data packets to be forwarded received by the fiber optic port can be directly input into the FPGA 31 as a data stream. The FPGA 31 merges multiple data streams through its MUX, restoring the data stream format to packet format, and then inputs it to the MTU for MTU detection. The MTU is used to determine the maximum size of the data service unit that the data packet receiver can accept. Data packets that meet the maximum size requirement are retained, while those that do not are discarded. After the MTU detects the data packets to be forwarded, the successfully detected data packets are input into the packet parsing circuit unit 311. Simultaneously, the successfully detected data packets can be cached in the storage unit 316 in the FPGA 31. This storage unit 316 can be, for example, DDR (Double Data Rate) memory.

[0061] In step S420, the data packet is parsed.

[0062] After receiving the data packet to be forwarded, the message parsing circuit unit 311 can parse the data packet to be forwarded, extract the message type of the data packet to be forwarded from the parsing result, and generate a message type signal based on the message type and send it to the path determination circuit unit 312.

[0063] The message parsing circuit unit 311 can also extract the field information of each protocol layer of the message header that the service is concerned with from the parsing result, that is, the message header information, which may be, for example, a five-tuple information.

[0064] In step S430, it is determined whether the message type is ARP.

[0065] When the path determination circuit unit 312 determines that the message type of the data message to be forwarded is ARP based on the message type signal, it executes step S440; otherwise, it executes step S450.

[0066] In step S440, the target port information matching the data packet to be forwarded is searched in the bridge mode register.

[0067] When the path determination circuit unit 312 determines that the packet type of the data packet to be forwarded is ARP based on the packet type signal, it finds the target port information matching the data packet by checking the bridge mode register 314, without needing to look up the flow table. The path determination circuit unit 312 generates a target port signal based on the target port information and sends it to the packet forwarding circuit unit 313. Then, step S480 is executed.

[0068] In step S450, fuzzy matching search of the flow table is performed.

[0069] Flow tables serve as the basis for data packet forwarding and represent an abstraction of the data packet forwarding function of network devices. Flow table entries contain instructions and actions. When a data packet matches a particular entry, the instruction in that entry is applied to the data packet. Actions in flow table entries can exist independently or be included within instructions. For example, when issuing flow tables, a series of actions can be specified for a certain instruction in a particular entry.

[0070] When the path determination circuit unit 312 determines that the message type of the data message to be forwarded is non-ARP based on the message type signal through its lookup table sub-circuit unit, it organizes the message header information (such as 5-tuple information) into a format consistent with the table entries stored in TCAM based on the received first message header signal, obtains the lookup keyword key, inputs it into TCAM, performs TCAM query, and outputs the address index of the matching table entry.

[0071] In one example embodiment, if no matching entry is found through the TCAM query, the default flow table of fuzzy matching can be used as the fuzzy matching result. This default flow table provides the address index of the default matching entry.

[0072] In step S460, the flow table performs an exact match lookup.

[0073] The path determination circuit unit 312 can use its lookup table sub-circuit unit to search for the required precisely matching flow table content from the server's memory based on the packet header information and the index found through fuzzy matching of the flow table. For example, priorities can be set for the flow tables. There may be multiple flow tables found based on the packet header information and the index. The flow table with the highest priority can be selected as the target flow table according to the set priority.

[0074] In one example embodiment, if the required exact match flow table content is not found in the server's memory based on the index found by fuzzy matching of the packet header information and the flow table, the default flow table that matches exactly can be used as the exact match flow table content.

[0075] For example, based on the action in the target flow table entry, if the action indicates that the data packet needs to be discarded, then the corresponding data packet to be forwarded is discarded; otherwise, the data packet to be forwarded is processed according to the action indicated by the action, such as modifying the header information of the data packet to be forwarded.

[0076] In step S470, the header information of the data packet to be forwarded is modified.

[0077] The header modification sub-circuit unit in the path determination circuit unit 312 queries the MAC (Media Access Control) address and IP address table according to the flow table matching result index to obtain the header modification information. Based on the header modification information, it modifies the header information of the data packet to be forwarded, obtains the modified data packet to be forwarded, and generates a second header signal based on the modified header information and sends it to the packet forwarding circuit unit 313.

[0078] For example, matching status information, traffic count information, etc. can be periodically packaged into ETH (Ethernet) packets, and the ETH packets can be reported to the server through network adapter 32 to realize flow table statistics.

[0079] In step S480, data packets are forwarded based on the target port information.

[0080] When the first forwarding sub-circuit unit in the message forwarding circuit unit 313 determines that the target port points to the server based on the target port signal, it sends the received data packet to be forwarded to the server's CPU through the network adapter 32. When the second forwarding sub-circuit unit in the message forwarding circuit unit 313 determines that the target port points to the fiber optic interface based on the target port signal, it can first perform QoS processing on the data packet to be forwarded, and then send the processed data packet to the fiber optic interface. For example, the data stream can be sent to the multi-channel fiber optic interface according to the configured shaping bandwidth through data stream multiplexing. This fiber optic interface can be, for example, a QSFP (Quad Small Form-factor Pluggable) interface.

[0081] For example, QoS processing of data packets to be forwarded may include at least one of the following: data packet caching, data packet management, data packet queue management, data packet scheduling, and congestion control.

[0082] The solution in this disclosure can be programmed into an FPGA using Verilog HDL (Hardware Description Language). The FPGA handles the reception, detection, and transmission of data packets (such as IP packets) to be forwarded, as well as traffic marking, flow table lookup in data packet routing, data packet modification, and integration with the management layer's routing table entry distribution mechanism and service traffic management. Leveraging the high performance, programmability, and easy upgradeability of the FPGA, the SDN control and forwarding layers are implemented in hardware. This allows for hardware-level modification of data packets, ACL matching, and QoS management. The CPU can then focus solely on flow table distribution and statistics, effectively avoiding latency and jitter issues caused by CPU multi-core performance allocation, operating system interrupts, and context switching, thus improving the system's service processing performance and efficiency.

[0083] Based on the data packet forwarding system of the above embodiments, this disclosure also provides a data packet forwarding method. Figure 5 The schematic diagram illustrates a data packet forwarding method according to some embodiments of the present disclosure, which can be applied to the data packet forwarding system described in any of the above embodiments. (Refer to...) Figure 5 As shown, the data packet forwarding method may include the following steps S510 to S530.

[0084] In step S510, the received data packet to be forwarded is parsed, and the packet type of the data packet to be forwarded is extracted from the parsing result;

[0085] In step S520, in response to the extracted message type being ARP, the target port information matching the data packet to be forwarded is determined from the bridge mode register.

[0086] In step S530, the data packet to be forwarded is forwarded according to the target port information.

[0087] According to the data packet forwarding method in this example embodiment, on the one hand, from the hardware level, FPGA is used to implement the processing and forwarding of data packets. The forwarding and processing of data packets hardly rely on the CPU. Moreover, since the hardware design on the FPGA is a multi-concurrency pipeline, the latency and jitter problems caused by CPU multi-core performance allocation, operating system interruption, context switching, etc. in the server can be avoided. On the other hand, for ARP type data packets to be forwarded, the target port information matching the data packet to be forwarded can be directly found from the bridge mode register, without the need to obtain it by looking up the flow table, which improves the forwarding efficiency of data packets.

[0088] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0089] It should be noted that although several modules or units in the data packet forwarding system have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0090] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0091] refer to Figure 6 As shown, a program product 600 for implementing the data packet forwarding method described in embodiments of the present disclosure is illustrated. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0092] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0093] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0094] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, radio frequency (RF), or any suitable combination thereof.

[0095] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0096] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0097] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0098] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0099] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data packet forwarding system, characterized by, The network adapter is used for connecting the FPGA with a server in communication; the FPGA comprises a message analysis circuit unit, a path determination circuit unit, a message forwarding circuit unit and a bridge mode register; The message analysis circuit unit is used for analyzing a received data message to be forwarded, extracting a message type of the data message to be forwarded from an analysis result, and generating a message type signal based on the message type and sending the message type signal to the path determination circuit unit; The path determination circuit unit is used for, when the message type is determined as an address resolution protocol (ARP) type according to the message type signal, searching for target port information matched with the data message to be forwarded from the bridge mode register, and generating a target port signal according to the target port information and sending the target port signal to the message forwarding circuit unit; The message forwarding circuit unit is used for forwarding the data message to be forwarded according to the target port signal.

2. The data message forwarding system of claim 1, wherein, The message analysis circuit unit is further used for extracting message header information of the data message to be forwarded from the analysis result, and generating a first message header signal according to the message header information and sending the first message header signal to the path determination circuit unit; The path determination circuit unit is further used for, when the message type is determined as a non-ARP type according to the message type signal, obtaining a target flow table matched with the message header information based on the received first message header signal, determining message header modification information according to the target flow table, modifying the message header information of the data message to be forwarded based on the message header modification information, generating a second message header signal according to the modified message header information and sending the second message header signal to the message forwarding circuit unit; The message forwarding circuit unit is further used for obtaining target port information in the second message header signal, and forwarding the modified data message to be forwarded according to the target port information in the second message header signal.

3. The data message forwarding system according to claim 1 or 2, characterized in that, The message forwarding circuit unit comprises a first forwarding sub-circuit unit and a second forwarding sub-circuit unit; The first forwarding sub-circuit unit is used for, when it is determined that a target port points to a server according to the target port signal, sending the data message to be forwarded to the server through the network adapter; The second forwarding sub-circuit unit is used for, when it is determined that the target port points to a fiber interface according to the target port signal, forwarding the data message to be forwarded to the fiber interface.

4. The data message forwarding system of claim 3, wherein, The second forwarding sub-circuit unit is specifically used for forwarding the data message to be forwarded to the fiber interface after quality of service (QoS) processing.

5. The data message forwarding system of claim 2, wherein, When the path determination circuit unit obtains the target flow table matched with the message header information based on the received first message header signal, it is specifically used for performing a ternary content-addressable memory (TCAM) query based on message header information in the first message header signal, and matching the target flow table from a server memory according to a query result and the message header information.

6. The data message forwarding system of claim 2, wherein, The message header information comprises five-tuple information, and the five-tuple information comprises a source Internet protocol (IP) address, a source port, a destination IP address, a destination port and a transport layer protocol.

7. The data message forwarding system of claim 1, wherein, The FPGA further comprises a packet preprocessing circuit unit; The packet preprocessing circuit unit is configured to receive the to-be-forwarded data packet, perform maximum transmission unit (MTU) detection on the to-be-forwarded data packet, and input the to-be-forwarded data packet that passes the detection to the packet analysis circuit unit.

8. The data message forwarding system of claim 7, wherein, The FPGA further comprises a packet buffering circuit unit; The packet buffering circuit unit is configured to buffer the to-be-forwarded data packet transmitted by the packet preprocessing circuit unit.

9. A data packet forwarding method, characterized by, The method is applied to the data packet forwarding system in any one of claims 1 to 8, and the method comprises: analyzing the received to-be-forwarded data packet, and extracting a packet type of the to-be-forwarded data packet from an analysis result; in response to the packet type being an address resolution protocol (ARP) type, determining target port information matched with the to-be-forwarded data packet from a bridge mode register; forwarding the to-be-forwarded data packet according to the target port information. 10.A computer readable storage medium, having stored thereon a computer program, wherein the computer program is executed by a processor to implement the data packet forwarding method in claim 9.

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