Method of manufacturing a circuit board assembly

Abstract

A circuit board assembly is provided. The circuit board assembly includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer, and a plurality of shielding posts. The core layer has a receiving slot, wherein the receiving slot has an inner sidewall. The electronic component is disposed in the receiving slot. The first shielding ring wall is disposed in the receiving slot and covers the inner sidewall, wherein the first shielding ring wall surrounds the electronic component and does not contact the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The shielding posts are disposed in the first insulating layer. In this way, the electronic component can be shielded from electromagnetic waves.

Description

Technical Field

[0001] This application relates to a circuit board assembly and a method for manufacturing the same, and more particularly to a circuit board assembly and a method for manufacturing the same that can effectively shield electromagnetic interference between electronic components. Background Technology

[0002] Current chip packages, such as System-in-a-Package (SiP), include multiple electronic components. These components generate electromagnetic waves during operation, which can interfere with their function. This can lead to malfunctions or even breakdowns in electronic devices housed within the chip package, such as smartphones or tablets. Therefore, reducing or avoiding such electromagnetic interference with the electronic components within the chip package is a topic worthy of exploration. Summary of the Invention

[0003] The purpose of this application is to provide a circuit board assembly, including a core layer, at least one electronic component, at least one first shielding ring wall, at least one second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer, and a plurality of shielding posts. The core layer has at least one receiving groove, wherein the receiving groove has an inner sidewall. The electronic component is disposed within the receiving groove. The first shielding ring wall is disposed within the receiving groove and covers the inner sidewall, wherein the first shielding ring wall surrounds the electronic component but does not contact the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The shielding posts are disposed in the first insulating layer.

[0004] In some embodiments, the shielding post is electrically connected to the first shielding ring wall.

[0005] In some embodiments, the circuit board assembly further includes a shielding layer disposed under a first insulating layer, wherein the first insulating layer is disposed between the shielding layer and the core layer, and the plurality of shielding pillars extend to the core layer and the shielding layer.

[0006] In some embodiments, the second shielding ring wall includes two metal layers and a conductive material, the metal layers being arranged in concentric rings, wherein one of the metal layers surrounds the other metal layer and the conductive material.

[0007] In some embodiments, one surface of the electronic component, one end of the conductive material, and the surface of the core layer are coplanar.

[0008] In some embodiments, the height of the second shielding ring wall is greater than the thickness of at least one of the electronic components.

[0009] In some embodiments, the circuit board assembly further includes a second insulating layer, wherein the first circuit layer is disposed between the second insulating layer and the core layer.

[0010] In some implementations, the core layer is made of a photosensitive dielectric material.

[0011] In some embodiments, the circuit board assembly further includes a graphene layer disposed in the receiving groove and surrounding the electronic component, wherein the graphene layer is continuously distributed around the electronic component.

[0012] In some embodiments, the electronic components are electrically isolated from the first shielding ring wall, the second shielding ring wall, and the shielding pillar.

[0013] This application also discloses a method for manufacturing a circuit board assembly, comprising providing a substrate. A first dielectric layer and a first release film are formed on the substrate, wherein the first release film is disposed between the first dielectric layer and the substrate. The first dielectric layer is patterned to form a first dielectric pattern layer, wherein the first dielectric pattern layer has at least one first groove and at least one first trench. A first metal layer is formed on the first dielectric pattern layer, wherein the first metal layer covers the upper surface of the first dielectric pattern layer, the sidewalls of the first groove, and the sidewalls of the first trench. At least one electronic component is disposed in at least one of the first grooves, wherein the electronic component is disposed on the substrate. After disposing the electronic component in at least one of the first grooves, a second dielectric pattern layer is disposed on the first dielectric pattern layer and the electronic component to form a core layer including the first dielectric pattern layer and the second dielectric pattern layer. At least one circuit layer is formed on the core layer. At least one insulating layer is formed on the circuit layer. A plurality of shielding pillars are formed in the insulating layer.

[0014] In some embodiments, the step of forming the second dielectric pattern layer includes forming a second dielectric layer and a second release film on a substrate on the opposite side of the first dielectric layer while forming the first dielectric layer and the first release film, wherein the second release film is disposed between the second dielectric layer and the substrate. The second dielectric layer is patterned to form the second dielectric pattern layer, wherein the second dielectric pattern layer has at least one second groove and at least one second trench. A second metal layer is formed on the second dielectric pattern layer, wherein the second metal layer covers the upper surface of the second dielectric pattern layer, the sidewalls of the second groove, and the sidewalls of the second trench.

[0015] In some embodiments, the method of manufacturing a circuit board assembly further includes filling a plurality of conductive materials in the first trench and the second trench during the process of setting the electronic components in at least one of the first trenches, wherein the conductive materials protrude from the surfaces of the first dielectric pattern layer and the second dielectric pattern layer.

[0016] In some embodiments, the method of manufacturing a circuit board assembly further includes thinning the first metal layer, the second metal layer, the first dielectric pattern layer, and the second dielectric pattern layer to expose the upper surfaces of the first dielectric pattern layer and the second dielectric pattern layer after forming the first metal layer and the second metal layer respectively on the first dielectric pattern layer and the second dielectric pattern layer, and before placing the electronic components in at least one of the first recesses.

[0017] In some implementations, the method of patterning the first dielectric layer and the second dielectric layer includes an exposure process and a development process.

[0018] In some embodiments, a second dielectric pattern layer is disposed on the first dielectric pattern layer and on the electronic component, and the second dielectric pattern layer and the first dielectric pattern layer are bonded to each other.

[0019] In some embodiments, during the step of disposing the second dielectric pattern layer on the first dielectric pattern layer and on the electronic component, the substrate, the first dielectric pattern layer, the second dielectric pattern layer, the electronic component, and the plurality of conductive materials are in an operating environment with a temperature between 25°C and 180°C.

[0020] In some embodiments, the method of manufacturing a circuit board assembly further includes removing the substrate after forming the conductive pillars in the insulating layer; forming at least one additional circuit layer on the core layer; and forming at least one additional insulating layer on the additional circuit layer.

[0021] In some embodiments, portions of the conductive pillars are disposed within the insulating layer along the first and second metal layers adjacent to the electronic component. Attached Figure Description

[0022] The following description, taken in conjunction with the accompanying drawings, will provide the best understanding of all aspects of this application. It should be understood that, according to industry practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features may be arbitrarily increased or decreased.

[0023] Figure 1A This is a cross-sectional schematic diagram illustrating a circuit board assembly according to some embodiments of this application.

[0024] Figure 1B To illustrate the basis Figure 1A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and shielding pillars.

[0025] Figures 2A to 2J This is a cross-sectional schematic diagram illustrating the process stages of a method for manufacturing a circuit board assembly according to some embodiments of this application.

[0026] Figure 3A This is a cross-sectional schematic diagram illustrating a circuit board assembly according to some other embodiments of this application.

[0027] Figure 3B To illustrate the basis Figure 3A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, shielding pillars, and graphene layer.

[0028] Figures 4A to 4D This is a cross-sectional schematic diagram illustrating the method for manufacturing a circuit board assembly according to other embodiments of this application at various process stages.

[0029] Figure 5A A cross-sectional schematic diagram is provided to illustrate a circuit board assembly according to some other embodiments of this application.

[0030] Figure 5B To illustrate the basis Figure 5A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and shielding pillars.

[0031] Figures 6A to 6C This is a cross-sectional schematic diagram illustrating the method for manufacturing a circuit board assembly according to some other embodiments of this application at various process stages.

[0032] Figure 7 This is a cross-sectional schematic diagram illustrating a circuit board assembly according to some other embodiments of the present application. Detailed Implementation

[0033] The following invention provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements, values, operations, materials, configurations, and the like are described below to simplify this application. Of course, these are merely examples and are not intended to be limiting. Other elements, values, operations, materials, configurations, and the like should also be considered. For example, in the following description, forming a first feature over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or words may be repeated in various examples. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, for ease of description, spatially relative terms such as "below," "below," "lower than," "above," and "above" may be used in this application to describe an element or feature relative to one or more other elements or features as shown in the figures. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0035] Typically, the circuit board assembly of this application can be used in any electronic product or device, and can integrate various components such as radio frequency, digital, and optoelectronic components into a highly integrated circuit board in a system-level package, while avoiding electromagnetic leakage or interference between the various components.

[0036] First, please refer to Figure 1A , Figure 1A This is a cross-sectional schematic diagram illustrating a circuit board assembly according to some embodiments of this application. In some embodiments of this application, the circuit board assembly 100 includes a core layer 110, at least one electronic component 112, at least one first shielding ring wall 113, at least one second shielding ring wall 114, a first wiring layer 120, a second wiring layer 130, a first insulating layer 140, and a plurality of shielding posts 141. The core layer 110 has at least one receiving groove 111, wherein the receiving groove 111 has an inner sidewall. Note that the inner sidewall is not specifically labeled to avoid clutter in the drawings. The electronic component 112 is disposed in the receiving groove 111. The first shielding ring wall 113 is disposed in the receiving groove 111 and covers the inner sidewall, wherein the first shielding ring wall 113 surrounds the electronic component 112 and does not contact the electronic component 112. The second shielding ring wall 114 is disposed in the core layer 110 and surrounds the first shielding ring wall 113. In one embodiment, the core layer 110 is made of a photosensitive dielectric material. In some embodiments, the material of the core layer 110 includes, but is not limited to, photosensitive dielectric materials such as photosensitive polyimide (PSPI), photoimageable coverlay (PIC), or combinations thereof. Specifically, the first shielding ring wall 113 not contacting the electronic component 112 means that there is an annular gap between the first shielding ring wall 113 and the electronic component 112 to electrically separate them. Furthermore, using a photosensitive dielectric material can support components of different sizes and form corresponding chambers or accommodating spaces. Given a specific space size, more components can be stacked vertically, resulting in high integration.

[0037] The core layer 110 may contain more than one electronic component 112, and when there are multiple electronic components 112, each electronic component 112 is surrounded by a corresponding first shielding ring wall 113. It should be noted that... Figure 1A One electronic component 112 and one first shielding ring wall 113 are shown, but this is merely exemplary and should not be considered as a limitation of the present application. Specifically, the first shielding ring wall 113 initially shields or blocks the electromagnetic waves leaked by the electronic component 112 to eliminate most of the electromagnetic interference. In one embodiment, the electronic component 112 may include, but is not limited to, active components, passive components, high-frequency components, digital components, optoelectronic components, or combinations thereof. In one embodiment, the material of the first shielding ring wall 113 includes, but is not limited to, conductive metals such as copper, gold, silver, nickel, and conductive alloys, or combinations thereof.

[0038] Please refer to this first. Figure 1B , Figure 1B To illustrate the basis Figure 1A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and shielding pillars. In some embodiments, the second shielding ring wall 114 is disposed in the core layer 110 and surrounds the first shielding ring wall 113. Figure 1B The relationship between the first shielding ring wall 113 and the second shielding ring wall 114 can be clearly seen. Specifically, the second shielding ring wall 114 does not directly contact the first shielding ring wall 113, but is arranged in a concentric ring with the first shielding ring wall 113.

[0039] Please continue reading. Figure 1AIn some embodiments, the second shielding ring wall 114 includes two metal layers 1141 and a conductive material 1142, the two metal layers 1141 being arranged in concentric rings, with one metal layer 1141 surrounding another metal layer 1141 and the conductive material 1142. Specifically, the two ends of the second shielding ring wall 114 extend to the upper and lower surfaces of the core layer 110. The second shielding ring wall 114 can shield or block electromagnetic waves leaked due to discontinuities between multiple electronic components 112, even when there are size differences. Specifically, the discontinuity refers to the unplated copper portion embedded in a vertical device. Furthermore, on a circuit board, the number and type of embedded components vary at each location, resulting in different discontinuities, but these discontinuities are less than the overall board thickness. Thus, in conjunction with the first shielding ring wall 113, it can shield most, if not almost, electromagnetic waves leaking from the electronic components 112 in all directions. Moreover, the metal layers 1141 in the second shielding ring wall 114 can increase the rigidity of the circuit board assembly 100. In one embodiment, the material of the two metal layers 1141 of the second shielding ring wall 114 includes, but is not limited to, conductive metals such as copper, gold, silver, nickel, and conductive alloys, or combinations thereof. In one embodiment, the material of the conductive material 1142 of the second shielding ring wall 114 includes, but is not limited to, metal alloys of copper, gold, silver, nickel, or combinations thereof.

[0040] Please continue reading. Figure 1A A core layer 110 is disposed between a first circuit layer 120 and a second circuit layer 130. Specifically, the electronic component 112 in the core layer 110 needs to be electrically connected to the outside world; therefore, the first circuit layer 120 and the second circuit layer 130 are disposed on the upper and lower surfaces of the core layer 110 to achieve this electrical connection. Furthermore, the second circuit layer 130 is disposed between a first insulating layer 140 and the core layer 110. Shielding posts 141 are disposed in the first insulating layer 140. Additionally, a plurality of conductive posts 142 are disposed in the first insulating layer 140, and these conductive posts 142 are electrically connected to the electronic component 112. In one embodiment, the shielding posts 141 are electrically connected to a first shielding ring wall 113 and extend to the upper and lower surfaces of the first insulating layer 140. Furthermore, the shielding posts 141 surround the aforementioned plurality of conductive posts 142.

[0041] See also Figure 1B The shielding posts 141 are arranged along the wall of the first shielding ring 113. Thus, when current flows through the conductive posts 142 below the electronic component 112, which serve as the pin conduction portion, and an electromagnetic field is generated, the shielding posts 141 can shield the electromagnetic field generated by the current. It should be noted here that... Figure 1BEight shielding posts 141 are shown, but this is merely exemplary and should not be considered a limitation of the present application. More or fewer shielding posts 141 should be included within the scope of this application. Furthermore, the shielding posts 141 are arranged in a columnar shape, unlike the first shielding ring wall 113 and the second shielding ring wall 114, thus allowing the conductive posts 142 to further communicate with external circuits. In some embodiments, the materials of the shielding posts 141 and the conductive posts 142 include, but are not limited to, conductive metals such as copper, gold, silver, nickel, and conductive alloys, or combinations thereof.

[0042] In some embodiments, electronic component 112 is electrically isolated from the first shielding ring wall 113, the second shielding ring wall 114, and the shielding post 141. In this way, the first shielding ring wall 113, the second shielding ring wall 114, and the shielding post 141 will not affect the electrical flow or function of electronic component 112 with external circuits.

[0043] In some embodiments, the circuit board assembly 100 further includes a shielding layer 150 disposed beneath a first insulating layer 140, which is located between the shielding layer 150 and the core layer 110. The shielding posts 141 extend to both the core layer 110 and the shielding layer 150. Specifically, the shielding layer 150 is disposed on the surface of the first insulating layer 140 relative to the core layer 110, and is perpendicular to the centerline of the conductive posts 142, thereby enhancing the shielding performance of electromagnetic fields. In one embodiment, the shielding layer 150 may be omitted and replaced with a thick copper layer, thereby increasing the heat dissipation efficiency of the circuit board assembly 100. In one embodiment, metal wiring may be used instead of the shielding layer 150 to allow the electronic components 112 to be further electrically connected to more electronic devices.

[0044] In another embodiment, the first insulating layer 140 may also have a multilayer structure, with the layers connected by an added circuit layer 143 and conductive posts 142.

[0045] Please refer to Figure 1A One surface of the electronic component 112, one end of the second shielding ring wall 114, and the surface of the core layer 110 are coplanar. Specifically, the second shielding ring wall 114 extends to the upper and lower surfaces of the core layer 110, so as to completely shield the electromagnetic waves leaked by the electronic component 112 due to the interruption.

[0046] In one embodiment, the circuit board assembly 100 further includes a second insulating layer 160, a wiring layer 170, and a plurality of conductive posts 161, and a first wiring layer 120 is disposed between the second insulating layer 160 and the core layer 110. The wiring layer 170 is disposed on the second insulating layer 160, and the conductive posts 161 extend to the core layer 110 and the wiring layer 170.

[0047] It should be noted that, as Figure 1A The manufacturing method and process of the circuit board assembly 100 shown will be described in detail in subsequent paragraphs.

[0048] Please see Figure 3A , Figure 3A This is a cross-sectional schematic diagram illustrating a circuit board assembly according to other embodiments of this application. For example... Figure 3A As shown, this implementation is similar to... Figure 1A The biggest difference between the circuit board assembly 100 and the previous one is that the core layer 310 of the circuit board assembly 300 in this embodiment further includes a graphene layer 315. It should be noted that... Figure 3A The overall structure of the 300 circuit board assembly is similar to Figure 1A The circuit board assembly 100 and the circuit board assembly 300 include a core layer 310, at least one electronic component 312, at least one first shielding ring wall 313, at least one second shielding ring wall 314, a first circuit layer 320, a second circuit layer 330, a first insulating layer 340, and a plurality of shielding posts 341. The core layer 310 has at least one receiving groove 311, wherein the receiving groove 311 has an inner sidewall. The electronic component 312 is disposed in the receiving groove 311. The first shielding ring wall 313 is disposed in the receiving groove 311 and covers the inner sidewall, wherein the first shielding ring wall 313 surrounds the electronic component 312 and does not contact the electronic component 312. The second shielding ring wall 314 is disposed in the core layer 310 and surrounds the first shielding ring wall 313. The second shielding ring wall 314 includes two metal layers 3141 and a conductive material 3142. The two metal layers 3141 are arranged in concentric rings, with one metal layer 3141 surrounding another metal layer 3141 and the conductive material 3142. A core layer 310 is disposed between a first circuit layer 320 and a second circuit layer 330. The second circuit layer 330 is disposed between a first insulating layer 340 and a core layer 310. Shielding posts 341 are disposed in the first insulating layer 340. In addition, a plurality of conductive posts 342 are also disposed in the first insulating layer 340, and the plurality of conductive posts 342 are electrically connected to electronic components 312. The shielding posts 341 are arranged along the first shielding ring wall 313. The circuit board assembly 300 also includes a shielding layer 350, wherein the shielding layer 350 is disposed below the first insulating layer 340, and the first insulating layer 340 is disposed between the shielding layer 350 and the core layer 310, and the shielding posts 341 extend to the core layer 310 and the shielding layer 350. The circuit board assembly 300 also includes a second insulating layer 360, a wiring layer 370, and a plurality of conductive posts 361, and a first wiring layer 320 is disposed between the second insulating layer 360 and the core layer 310. The wiring layer 370 is disposed on the second insulating layer 360, and the conductive posts 361 extend to the core layer 310 and the wiring layer 370.

[0049] The materials of all components in the aforementioned circuit board assembly 300 are consistent with... Figure 1A The circuit board assembly is 100% identical, so it will not be described in detail here.

[0050] In some embodiments, a graphene layer 315 is disposed in the receiving groove 311 and surrounds the electronic component 312, with the graphene layer 315 continuously distributed around the electronic component 312. Specifically, the graphene layer 315 is disposed between the electronic component 312 and the first shielding ring wall 313, between the electronic component 312 and the first circuit layer 320, and between the second circuit layer 330 and the first insulating layer 340, and the graphene layer 315 has a continuous structure. When the graphene layer 315 is disposed in the receiving groove 311, the graphene layer 315 can improve the heat dissipation efficiency of the circuit board assembly 300.

[0051] Please refer to the following first. Figure 3B , Figure 3B To illustrate the basis Figure 3A A top-view schematic diagram of the core layer, electronic components, first shielding ring wall, second shielding ring wall, shielding pillars, and graphene layer. Figure 3B It is clear that the graphene layer 315 is disposed between the first shielding ring wall 313 and the electronic component 312, and covers the electronic component 312, thereby improving the heat dissipation efficiency of the electronic component 312.

[0052] It should be noted that, as Figure 3A The manufacturing method and process of the circuit board assembly 300 shown will be described in detail in subsequent paragraphs.

[0053] Please see Figure 5A , Figure 5A This is a cross-sectional schematic diagram illustrating a circuit board assembly according to further embodiments of this application. Specifically, Figure 5A A circuit board assembly 500 with multiple electronic components 512 is shown.

[0054] Figure 5A The circuit board assembly shown comprises a core layer 510, electronic components 512, a first shielding ring wall 513, a second shielding ring wall 514, a metal layer 5141, a conductive material 5142, a first circuit layer 520, a second circuit layer 530, a first insulating layer 540, shielding pillars 541, conductive pillars 542, an additional circuit layer 543, a shielding layer 550 (or a thick copper layer, metal wiring), a second insulating layer 560, conductive pillars 561, and a wiring layer 570. The structural features and materials of each component are consistent with... Figure 1A and Figure 3A The circuit board assemblies 100 and 300 shown are the same, so they will not be described again here.

[0055] Specifically Figure 5AThree electronic components 512 are marked. The different electronic components 512 in the vertical direction are separated by a photosensitive dielectric material. Therefore, there will be a gap between the electronic components 512, and electromagnetic waves will leak out. Accordingly, the second shielding ring wall 514 can shield and block these leaked electromagnetic waves and keep the electronic components 512 from interfering with each other.

[0056] Please see Figure 5B , Figure 5B To illustrate the basis Figure 5A A top view of the core layer, electronic components, first shielding ring wall, second shielding ring wall, and shielding pillars. Figure 5B It can also be seen that the first shielding ring wall 513 does not contact the electronic component 512, thus maintaining electrical isolation between the first shielding ring wall 513 and the electronic component 512.

[0057] It should be noted that, as Figure 5A The manufacturing method and process of the circuit board assembly 500 shown will be described in detail in subsequent paragraphs.

[0058] Please see Figure 7 , Figure 7 This is a cross-sectional schematic diagram illustrating a circuit board assembly according to some other embodiments of the present application. Figure 7 The circuit board assembly shown comprises a core layer 710, electronic components 712, a first shielding ring wall 713, a second shielding ring wall 714, a metal layer 7141, a conductive material 7142, a first circuit layer 720, a second circuit layer 730, a first insulating layer 740, shielding pillars 741, conductive pillars 742, an additional circuit layer 743, a shielding layer 750 (or a thick copper layer, metal wiring), a second insulating layer 760, conductive pillars 761, and a wiring layer 770. The structural features and materials of each component are consistent with... Figure 1A and Figure 3A The circuit board assemblies 100 and 300 shown are the same, so they will not be described again here.

[0059] Specifically Figure 7 Two electronic components 712 are shown, one of which has its upper surface not in contact with the upper surface of the core layer 710. In one embodiment, the height of the second shielding ring wall 714 is greater than the thickness of the electronic component 712 that is not in contact with the upper surface of the core layer 710. Accordingly, the second shielding ring wall 714 can prevent electromagnetic wave leakage from the electronic component 712 with discontinuities and prevent the electronic components 712 from interfering with each other.

[0060] The following will be aimed at Figure 1A The manufacturing process of the circuit board assembly 100 shown in the embodiment is described in detail.

[0061] Please see Figure 2A Up to Figure 2J, Figures 2A to 2J This is a cross-sectional schematic diagram illustrating the method for manufacturing a circuit board assembly according to some embodiments of this application at various process stages. First, by Figure 2A As shown, a substrate 210 is provided, and a first dielectric layer 220 and a first release film 230, as well as a second dielectric layer 240 and a second release film 250 are formed on both sides (i.e., the upper and lower surfaces) of the substrate 210, respectively. The first release film 230 is disposed between the first dielectric layer 220 and the substrate 210, while the second release film 250 is disposed between the second dielectric layer 240 and the substrate 210. Specifically, the first release film 230 and the second release film 250 are provided to facilitate the separation of the first dielectric layer 220 and the second dielectric layer 240 in subsequent processes. In one embodiment, the materials of the first dielectric layer 220 and the second dielectric layer 240 include, but are not limited to, photosensitive dielectric materials such as photosensitive polyimide (PSPI), photoimageable coverlay (PIC), or combinations thereof.

[0062] Please see Figure 2B The first dielectric layer 220 and the second dielectric layer 240 are patterned to form a first dielectric pattern layer 220' and a second dielectric pattern layer 240'. The first dielectric pattern layer 220' has a first groove 221 and a first trench 222, and the second dielectric pattern layer 240' has a second groove 241 and a second trench 242. Specifically, the first dielectric pattern layer 220' and the second dielectric pattern layer 240' are components that serve as structural packages. In one embodiment, the patterning of the first dielectric layer 220 and the second dielectric layer 240 includes, but is not limited to, exposure and development processes.

[0063] like Figure 2C As shown, a first metal layer 260 is formed on the first dielectric pattern layer 220', wherein the first metal layer 260 covers the upper surface of the first dielectric pattern layer 220', the sidewalls of the first groove 221, and the sidewalls of the first trench 222. Furthermore, a second metal layer 270 is formed on the second dielectric pattern layer 240', wherein the second metal layer 270 covers the upper surface of the second dielectric pattern layer 240', the sidewalls of the second groove 241, and the sidewalls of the second trench 242. In one embodiment, the method of forming the first metal layer 260 and the second metal layer 270 includes, but is not limited to, deposition processes, electroplating processes, coating processes, or combinations thereof. In one embodiment, the materials used to form the first metal layer 260 and the second metal layer 270 include, but are not limited to, conductive metals such as copper, gold, silver, nickel, and conductive alloys, or combinations thereof.

[0064] Please see Figure 2DThe first metal layer 260, the second metal layer 270, the first dielectric pattern layer 220', and the second dielectric pattern layer 240' are thinned to form the first dielectric pattern layer 220'' and the second dielectric pattern layer 240'', along with the first metal pattern layer 260' and the second metal pattern layer 270', exposing the upper surfaces. In one embodiment, the methods for thinning the first metal layer 260, the second metal layer 270, the first dielectric pattern layer 220', and the second dielectric pattern layer 240' include, but are not limited to, etching, exposure, and development processes.

[0065] like Figure 2E As shown, an electronic component 112 is disposed in the first groove 221, and the electronic component 112 is located above the substrate 210. It should be noted that the electronic component 112 does not contact the first metal pattern layer 260' on the sidewall of the first groove 221, thus avoiding electrical connection between the electronic component 112 and the first metal pattern layer 260'. At the same time, a plurality of conductive materials 1142 are filled in the first groove 222 and the second groove 242. It should be noted that the plurality of conductive materials 1142 protrude from the surfaces of the first dielectric pattern layer 220'' and the second dielectric pattern layer 240''. Accordingly, in the subsequent stacking process, the first dielectric pattern layer 220'' and the second dielectric pattern layer 240'' can be completely bonded.

[0066] Please see Figure 2F The second dielectric pattern layer 240'' is peeled off from the substrate 210 using the second release film 250, and then further stacked onto the first dielectric pattern layer 220'' and the electronic component 112. In this way, the first metal pattern layer 260' and the second metal pattern layer 270' are bonded together, and multiple conductive materials 1142 are also bonded together, forming the first shielding ring wall 113 and the second shielding ring wall 114. Accordingly, a... Figure 1A The core layer 110 is shown. When the second dielectric pattern layer 240'' is stacked on the first dielectric pattern layer 220'' and the electronic component 112, the first dielectric pattern layer 220'' and the second dielectric pattern layer 240'' are bonded to each other. Next, a second circuit layer 130 is formed on the core layer 110. Specifically, the second circuit layer 130 is formed by etching after electroplating or depositing metal.

[0067] In one embodiment, during the bonding of the first dielectric pattern layer 220'' and the second dielectric pattern layer 240'' to each other, the ambient temperature is between 25°C and 180°C to keep it below the glass transition temperature and melting point of the dielectric ceramic layer. This prevents the core layer 110 from expanding and deforming due to heating or overheating, which could lead to damage.

[0068] Please see Figure 2GA first insulating layer 140 is fabricated, and a shielding layer 150 (or a thick copper layer or metal wiring) is formed on one of its surfaces. Furthermore, an add-on circuit layer 143 is formed within the first insulating layer 140. In one embodiment, the shielding layer 150 (or thick copper layer, metal wiring) is formed by, but not limited to, deposition, electroplating, coating, or combinations thereof.

[0069] like Figure 2H As shown, a plurality of shielding pillars 141 and a plurality of conductive pillars 142 are formed in the first insulating layer 140. The shielding pillars 141 extend to the upper and lower surfaces of the first insulating layer 140, and the conductive pillars 142 are surrounded by the shielding pillars 141. In one embodiment, the shielding pillars 141 and the conductive pillars 142 are formed by, but not limited to, drilling and deposition processes.

[0070] See Figure 2I ,Will Figure 2H The first insulating layer 140, fabricated in the first insulating layer 140, is stacked onto the core layer 110. Note that this step involves bonding the surface of the first insulating layer 140 without the shielding layer 150 to the core layer 110. Thus, the plurality of shielding pillars 141 are electrically connected to the first shielding ring wall 113, and the plurality of conductive pillars 142 are electrically connected to the electronic components 112.

[0071] Please see again Figure 2J The core layer 110 is separated from the substrate 210 by a first release film 230, and a first circuit layer 120 is formed on the surface of the core layer 110 where the first insulating layer 140 is not bonded. Specifically, the first circuit layer 120 is formed by etching after electroplating or depositing metal. Next, a second insulating layer 160 is formed on the first circuit layer 120, and a plurality of conductive pillars 161 are formed in the second insulating layer 160. Then, a wiring layer 170 is formed on the second insulating layer 160. Specifically, the first circuit layer 120 is disposed between the second insulating layer 160 and the core layer 110, and the second insulating layer 160 is disposed between the wiring layer 170 and the first circuit layer 120.

[0072] Thus, the following was formed: Figure 1A The circuit board assembly 100 shown has the effect of shielding electromagnetic waves leaked from the electronic components 112 in all directions.

[0073] Next, the following will address... Figure 3A The manufacturing process of the circuit board assembly 300 shown in the embodiment is described in detail.

[0074] First, it should be noted that in order to place a graphene layer 315 on the core layer 310 in the circuit board assembly 300, therefore, in the aforementioned Figure 2EDuring the step of filling the conductive material 1142, electronic components 112 are not set. Instead, the second dielectric pattern layer 240'' is first stacked on the first dielectric pattern layer 220'', and the conductive material 1142 is bonded.

[0075] Please see Figure 4A A first shielding ring wall 313 is formed on the inner sidewall of the receiving groove 311, and a second circuit layer 330 is formed on the core layer 310. The first shielding ring wall 313 and the second circuit layer 330 are formed by, but not limited to, deposition process, electroplating process, coating process or a combination thereof.

[0076] Next, as Figure 4B As shown, a graphene layer 315 is formed on the substrate 410, inside the first shielding ring wall 313, and on the second circuit layer 330. The graphene layer 315 is continuous and integrally formed. In one embodiment, the graphene layer 315 is formed in the core layer 310 and on the second circuit layer 330 by embedding.

[0077] See also Figure 4C Electronic components 312 are disposed in graphene layer 315. Specifically, graphene layer 315 covers electronic components 312 and electrically separates electronic components 312 from the first shielding ring wall 313.

[0078] Next, as Figure 4D As shown, after the graphene layer 315 is formed and the electronic components 312 are set, the subsequent steps are all the same as... Figures 2G to 2J Similarly, a first insulating layer 340, shielding pillars 341, conductive pillars 342, an additional circuit layer 343, a shielding layer 350, a first circuit layer 320, a second insulating layer 360, conductive pillars 361, and a wiring layer 370 are thus formed. In this way, a structure is formed as follows: Figure 3A The circuit board assembly 300 shown has the effect of shielding electromagnetic waves leaked from electronic components 312 in all directions, and also has the effect of enhancing heat dissipation efficiency.

[0079] The following will be aimed at Figure 5A The manufacturing process of the circuit board assembly 500 shown in the embodiment is described in detail.

[0080] Please see Figures 6A to 6C , Figures 6A to 6C This is a cross-sectional schematic diagram illustrating a method for manufacturing a circuit board assembly according to some other embodiments of this application, showing the various process stages. The difference between this embodiment and the previously described embodiments is that this embodiment includes a plurality of electronic components 512.

[0081] First, such as Figure 6AAs shown, a first dielectric pattern layer 630 and a first release film 620a are formed on one side of the first substrate 610, and a second dielectric pattern layer 640 and a second release film 620b are formed on the other side. The first release film 620a is disposed between the first dielectric pattern layer 630 and the first substrate 610, and the second release film 620b is disposed between the second dielectric pattern layer 640 and the first substrate 610. A third dielectric pattern layer 650 and a third release film 620c are formed on one side of the second substrate 610', and a fourth dielectric pattern layer 660 and a fourth release film 620d are formed on the other side. The third release film 620c is disposed between the third dielectric pattern layer 650 and the second substrate 610', and the fourth release film 620d is disposed between the fourth dielectric pattern layer 660 and the second substrate 610'. Furthermore, electronic components 512 are disposed in a plurality of grooves in the third dielectric pattern layer 650.

[0082] Next, as Figure 6B As shown, the first dielectric pattern layer 630 and the second dielectric pattern layer 640 are sequentially peeled off using the first release film 620a and the second release film 620b, and then sequentially stacked onto the third dielectric pattern layer 650 and the electronic component 512. The first dielectric pattern layer 630, the second dielectric pattern layer 640, and the third dielectric pattern layer 650 are bonded to each other. Furthermore, another electronic component 512 is disposed on the stacked first dielectric pattern layer 630 and within the second dielectric pattern layer 640. If the upper surfaces of the plurality of electronic components 512 cannot be flush with the upper surface of the second dielectric pattern layer 640, a fourth dielectric pattern layer 660 can be used for further adjustment to make the upper surface of the core layer 510 flush.

[0083] like Figure 6C As shown, all subsequent steps are the same as Figures 2G to 2J Similarly, a first insulating layer 540, shielding pillar 541, conductive pillar 542, additional circuit layer 543, shielding layer 550, first circuit layer 520, second insulating layer 560, conductive pillar 561, and wiring layer 570 are thus formed. In this way, a structure is formed as follows: Figure 5A The circuit board assembly 500 shown has the effect of shielding electromagnetic waves leaked from the electronic components 512 in all directions.

[0084] In summary, the circuit board assembly of this application employs a first shielding ring wall around each electronic component to initially shield electromagnetic waves. Next, a second shielding ring wall is used to shield electromagnetic waves leaked due to size differences in the electronic components. Then, the first and / or second shielding pillars are used to shield the electromagnetic field generated by the conductive pillars. Finally, a shielding layer is provided to enhance the overall shielding effect. Additionally, a graphene layer can be added to increase the heat dissipation of the circuit board assembly. Therefore, this application can effectively prevent electromagnetic interference between electronic components.

[0085] The foregoing invention outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this application. Those skilled in the art will understand that they can readily use this application as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also understand that although this application has been disclosed above with various embodiments, it is not intended to limit this application. Any modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the claims.

[0086] [Symbol Explanation]

[0087] 100: Circuit board assembly

[0088] 110: Core Layer

[0089] 111: Receiving slot

[0090] 112: Electronic components

[0091] 113: First shielding ring wall

[0092] 114: Second shielding ring wall

[0093] 1141: Metal layer

[0094] 1142: Conductive materials

[0095] 120: First Line Layer

[0096] 130: Second line layer

[0097] 140: First insulating layer

[0098] 141: Shielding post

[0099] 142: Conductive post

[0100] 143: Additional Line Layer

[0101] 150: Shielding layer

[0102] 160: Second insulating layer

[0103] 161: Conductive post

[0104] 170: Wiring layer

[0105] 210:Substrate

[0106] 220: First dielectric layer

[0107] 220': First dielectric pattern layer

[0108] 220'': First dielectric pattern layer

[0109] 221: First Groove

[0110] 222: First trench

[0111] 230: First release film

[0112] 240: Second dielectric layer

[0113] 240': Second dielectric pattern layer

[0114] 240'': Second dielectric pattern layer

[0115] 241: Second groove

[0116] 242: Second trench

[0117] 250: Second release film

[0118] 260: First metal layer

[0119] 260': First metal pattern layer

[0120] 270: Second metal layer

[0121] 270': Second metal pattern layer

[0122] 300: Circuit board assembly

[0123] 310: Core Layer

[0124] 311: Receiving slot

[0125] 312: Electronic components

[0126] 313: First shielding ring wall

[0127] 314: Second Shielding Ring Wall

[0128] 3141: Metal layer

[0129] 3142: Conductive materials

[0130] 315: Graphene layer

[0131] 320: First Line Layer

[0132] 330: Second line layer

[0133] 340: First insulating layer

[0134] 341: Shielding post

[0135] 342: Conductive post

[0136] 343: Add-on circuit layer

[0137] 350: Shielding layer

[0138] 360: Second insulating layer

[0139] 361: Conductive post

[0140] 370: Wiring layer

[0141] 410:Substrate

[0142] 420: Release film

[0143] 500: Circuit Board Assembly

[0144] 510: Core Layer

[0145] 511: Receptacle

[0146] 512: Electronic Components

[0147] 513: First shielding ring wall

[0148] 514: Second shielding ring wall

[0149] 5141: Metal layer

[0150] 5142: Conductive materials

[0151] 520: First Line Layer

[0152] 530: Second Line Layer

[0153] 540: First insulating layer

[0154] 541: Shielding post

[0155] 542: Conductive post

[0156] 543: Additional Line Layer

[0157] 550: Shielding layer

[0158] 560: Second insulating layer

[0159] 561: Conductive post

[0160] 570: Wiring Layer

[0161] 610: First substrate

[0162] 610': Second substrate

[0163] 620a: First release film

[0164] 620b: Second release film

[0165] 620c: Third release film

[0166] 620d: Fourth release film

[0167] 630: First dielectric pattern layer

[0168] 640: Second dielectric pattern layer

[0169] 650: Third dielectric pattern layer

[0170] 660: Fourth dielectric pattern layer

[0171] 700: Circuit Board Assembly

[0172] 710: Core Layer

[0173] 711: Receptacle

[0174] 712: Electronic Components

[0175] 713: First Shielding Ring Wall

[0176] 714: Second Shielding Ring Wall

[0177] 7141: Metal layer

[0178] 7142: Conductive materials

[0179] 720: First Line Layer

[0180] 730: Second Line Layer

[0181] 740: First insulating layer

[0182] 741: Shielding post

[0183] 742: Conductive post

[0184] 743: Additional Line Layer

[0185] 750: Shielding layer

[0186] 760: Second insulating layer

[0187] 761: Conductive post

[0188] 770: Wiring layer.

Claims

1. A method of manufacturing a circuit board assembly, characterized by, Comprising: providing a substrate; forming a first dielectric layer and a first release film on the substrate, and forming a second dielectric layer and a second release film on the substrate opposite to the first dielectric layer, wherein the first release film is disposed between the first dielectric layer and the substrate and the second release film is disposed between the second dielectric layer and the substrate; patterning the first dielectric layer to form a first dielectric pattern layer, wherein the first dielectric pattern layer has at least one first recess and at least one first trench; patterning the second dielectric layer to form a second dielectric pattern layer, wherein the second dielectric pattern layer has at least one second recess and at least one second trench; forming a first metal layer on the first dielectric pattern layer, wherein the first metal layer covers an upper surface of the first dielectric pattern layer, a sidewall of the first recess, and a sidewall of the first trench; forming a second metal layer on the second dielectric pattern layer, wherein the second metal layer covers an upper surface of the second dielectric pattern layer, a sidewall of the second recess, and a sidewall of the second trench; disposing at least one electronic component in at least one of the first recesses, wherein the at least one electronic component is disposed on the substrate; after disposing the at least one electronic component in at least one of the first recesses, disposing the second dielectric pattern layer on the first dielectric pattern layer and on the at least one electronic component to form a core layer comprising the first dielectric pattern layer and the second dielectric pattern layer; forming at least one wiring layer on the core layer; forming at least one insulating layer on the at least one wiring layer; and forming a plurality of shielding pillars in the at least one insulating layer.

2. The method of claim 1, further comprising: filling a plurality of conductive materials in the at least one first trench and the at least one second trench during the process of disposing the at least one electronic component in at least one of the first recesses, wherein the plurality of conductive materials protrude from surfaces of the first dielectric pattern layer and the second dielectric pattern layer.

3. The method of claim 1, further comprising: after forming the first metal layer and the second metal layer on the first dielectric pattern layer and the second dielectric pattern layer, respectively, and before disposing the at least one electronic component in at least one of the first recesses, thinning the first metal layer, the second metal layer, the first dielectric pattern layer, and the second dielectric pattern layer to expose upper surfaces of the first dielectric pattern layer and the second dielectric pattern layer.

4. The method of claim 1, wherein the method of patterning the first dielectric layer and the second dielectric layer comprises an exposure process and a development process.

5. The method of claim 1, wherein disposing the second dielectric pattern layer on the first dielectric pattern layer and on the at least one electronic component, the second dielectric pattern layer and the first dielectric pattern layer are adhered to each other.

6. The method of claim 2, wherein the step of disposing the second dielectric pattern layer on the first dielectric pattern layer and on the at least one electronic component is performed while the substrate, the first dielectric pattern layer, the second dielectric pattern layer, the at least one electronic component, and the plurality of conductive materials are in an operating environment having a temperature in a range of 25 °C to 180 °C.

7. The method of claim 1, further comprising: removing the substrate after forming the plurality of conductive pillars in the at least one insulating layer; forming at least one build-up line layer on the core layer; and forming at least one build-up insulating layer on the at least one build-up line layer.

8. The method of claim 7, wherein portions of the plurality of conductive pillars are disposed in the at least one insulating layer along the first metal layer and the second metal layer adjacent to the at least one electronic component. ​

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