Flash memory and method of making the same

Abstract

The application provides a flash memory and a manufacturing method thereof. The flash memory comprises: a substrate, a source line is formed on the substrate, a floating gate structure layer and a first side wall are sequentially formed on the substrate on both sides of the source line from bottom to top, and the first side wall is above the floating gate structure layer on the side close to the source line; a tunneling oxide layer, the tunneling oxide layer covers at least the upper surface and the sidewall surface of the corner of the floating gate structure layer away from the source line; and a word line, the word line is above the substrate on the side of the floating gate structure layer away from the source line. In the application, the corner of the floating gate structure layer is wrapped by the word line, the wrapping property of the corner is increased, the electric field intensity of the corner is improved, and the erasing effect is improved. Meanwhile, the thickness of the floating gate structure layer is reduced, the coupling ratio of the word line and the floating gate is reduced, the pressure difference between the word line and the floating gate is increased, and the erasing effect is improved. The complex process of forming the sharp corner of the floating gate is omitted, and the reliability of the flash memory is ensured.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a flash memory and its manufacturing method. Background Technology

[0002] The development of flash memory (FRAM) has been particularly rapid in recent years. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast storage speed, and ease of erasure and rewriting. Therefore, it has been widely used in microcomputers, automation control, and many other fields. Flash memory is divided into two types: multi-gate flash memory (FRAM) and multi-gate flash memory (MWF). FRAM has a floating gate and a control gate located above the floating gate. FRAM suffers from over-erasure problems. Unlike FRAM, MWF has a source line formed on one side of the floating gate to serve as the erase gate. MWF effectively avoids the over-erasure effect.

[0003] In one type of flash memory, symmetrical floating gates are formed on both sides of the source line, with a sharp corner on the side of the floating gate furthest from the source line. Typically, a relatively thick floating gate is required, and its pointed shape is formed through an isotropic etching process, making it difficult to reduce the thickness of the floating gate. Furthermore, a thicker floating gate, meaning a higher sidewall height, increases the coupling rate between the word line and the floating gate, hindering erasing. Simultaneously, the sharp corner of the floating gate is formed by a dedicated etching process, which is unstable, making it difficult to guarantee the reliability of the manufactured flash memory. Summary of the Invention

[0004] The purpose of this invention is to provide a flash memory and its fabrication method. A tunneling oxide layer at least covers the upper surface and sidewall surface of the floating gate structure layer at the corner furthest from the source line. The word lines are wrapped around the corner of the floating gate structure layer through the tunneling oxide layer, increasing the wrapping at the corner and thus improving the electric field strength, thereby enhancing the erasing effect. Simultaneously, the thickness of the floating gate structure layer can be reduced, decreasing the coupling ratio between the word lines and the floating gate, which helps to increase the voltage difference between the word lines and the floating gate, thereby improving the erasing effect. The complex process of forming the floating gate sharp corners is eliminated, ensuring the reliability of the flash memory.

[0005] This invention provides a flash memory, comprising:

[0006] A substrate on which a source line is formed, and a floating gate structure layer and a first sidewall are formed sequentially from bottom to top on the substrate on both sides of the source line; and the first sidewall is located above the floating gate structure layer on the side closer to the source line.

[0007] A tunneling oxide layer, which at least covers the upper surface and sidewall surface of the floating grid structure layer at the corner away from the source line;

[0008] Word lines, the word lines being located above the substrate on the side of the floating gate structure layer away from the source lines;

[0009] The word lines are wrapped around the floating grid structure layer through the tunneling oxide layer.

[0010] Furthermore, an offset layer is formed on the sidewall of the first sidewall away from the source line, the offset layer exposing the upper surface of the floating grid structure layer away from the source line, and the tunneling oxide layer also covers the sidewall surface of the offset layer.

[0011] Furthermore, the flash memory also includes an isolation layer, which is L-shaped and includes a connected horizontal isolation portion and a vertical isolation portion. The horizontal isolation portion is located between the bottom of the offset layer and the floating gate structure layer, and the vertical isolation portion is located between the sidewall of the first sidewall and the offset layer.

[0012] Furthermore, the flash memory also includes a second sidewall located on the substrate on both sides of the source line. The sidewall of the second sidewall away from the source line is adjacent to the sidewall of the first sidewall near the source line. The second sidewall covers the sidewall of the floating gate structure layer near the source line.

[0013] Furthermore, the floating gate structure layer includes a floating gate oxide layer and a floating gate sequentially located on the substrate, and the corner of the floating gate structure layer on the side away from the source line is a right angle.

[0014] Furthermore, the thickness of the floating grid ranges from 200 angstroms to 400 angstroms.

[0015] The present invention also provides a method for manufacturing a flash memory, comprising:

[0016] A substrate is provided, on which a source line is formed, and on both sides of the source line, a floating gate structure layer and a first sidewall are formed sequentially from bottom to top on the substrate; and the first sidewall is located above the floating gate structure layer on the side closer to the source line;

[0017] A tunneling oxide layer is formed, which at least covers the upper surface and sidewall surface of the floating grid structure layer at the corner away from the source line;

[0018] A word line is formed, which is located above the substrate on the side of the floating gate structure layer away from the source line; the word line is wrapped around the floating gate structure layer through the tunneling oxide layer.

[0019] Furthermore, providing the substrate specifically includes:

[0020] A floating gate oxide layer, a floating gate layer, and a sacrificial layer are sequentially formed on the substrate. The sacrificial layer has an opening that exposes the surface of the floating gate layer.

[0021] A first sidewall is formed on the sidewalls on both sides of the opening;

[0022] Etching removes the floating gate layer and the floating gate oxide layer located between the first sidewalls on both sides of the opening, exposing the substrate surface;

[0023] A second sidewall is formed, which covers the sidewalls of the floating gate oxide layer on both sides, the sidewalls of the floating gate layer, and part of the sidewalls of the first sidewall.

[0024] Furthermore, after forming the second sidewall, the process also includes:

[0025] A source line is formed between the second sidewalls on both sides of the opening and between the first sidewalls, with the bottom of the source line located on the substrate;

[0026] Remove the sacrificial layer;

[0027] The floating gate layer and the floating gate oxide layer on the side of the first sidewalls on both sides of the source line away from the source line are etched, and the remaining floating gate layer and the floating gate oxide layer are etched to form the floating gate structure layer.

[0028] Furthermore, after providing the substrate but before forming the tunneling oxide layer, the method further includes:

[0029] An isolation layer is formed, which covers the sidewall surface of the first sidewall on both sides of the source line away from the source line and part of the surface of the floating grid structure layer;

[0030] An offset material layer is formed, the offset material layer is located on the sidewall of the isolation layer away from the source line, and the bottom part of the offset material layer covers the isolation layer on the surface of the floating grid structure layer;

[0031] The offset material layer is partially etched using wet etching, and the remaining width of the offset material layer is used as the offset layer. The width of the offset layer is controlled and adjusted by wet etching, and the width of the offset layer is related to the thickness of the floating gate in the floating gate structure layer.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention provides a flash memory and its fabrication method. The flash memory includes: a substrate with a source line formed thereon; a floating gate structure layer and a first sidewall formed sequentially from bottom to top on both sides of the source line; the first sidewall being located above the floating gate structure layer on the side closer to the source line; a tunneling oxide layer covering at least the upper surface and sidewall surface of the corner of the floating gate structure layer away from the source line; and word lines located above the substrate on the side of the floating gate structure layer away from the source line. In this invention, the word lines wrap around the corner of the floating gate structure layer through the tunneling oxide layer, increasing the wrapping at the corner and improving the electric field strength at the corner, thereby improving the erasing effect. Simultaneously, the thickness of the floating gate structure layer can be reduced, decreasing the coupling ratio between the word line and the floating gate, which is beneficial for increasing the voltage difference between the word line and the floating gate, thus improving the erasing effect. The complex process of forming the floating gate sharp corners is eliminated, ensuring the reliability of the flash memory. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the flash memory fabrication method according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the flash memory after forming the sacrificial layer and the opening according to an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the flash memory after the source line is formed according to an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the flash memory after removing the sacrificial layer according to an embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram of the flash memory after the offset layer is formed according to an embodiment of the present invention.

[0039] Figure 6 This is a schematic diagram of the flash memory after the floating gate structure layer is formed according to an embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of the flash memory after the tunneling oxide layer is formed according to an embodiment of the present invention.

[0041] Figure 8 This is a schematic diagram of a flash memory structure according to an embodiment of the present invention.

[0042] Figure 9 for Figure 8 An enlarged diagram of the left half of the image.

[0043] The accompanying figure is labeled as follows:

[0044] 100-Substrate; 101-Floating gate oxide layer; 102-Floating gate layer; 103-Sacrificial layer; 104-Opening; 105-First sidewall; 106-Second sidewall; 107-Source line (erase gate); 108-Isolation layer; 109-Offset layer; 110-Tunneling oxide layer; 110a-Tunneling horizontal portion; 110b-Tunneling vertical portion; 111-Word line; 112-Floating gate; 113-Drain doped region. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used so, may be replaced where appropriate.

[0047] This invention provides a method for manufacturing a flash memory, such as... Figure 1 As shown, it includes:

[0048] Step S1: Provide a substrate on which a source line is formed. A floating gate structure layer and a first sidewall are formed sequentially from bottom to top on the substrate on both sides of the source line. The first sidewall is located above the floating gate structure layer on the side closer to the source line.

[0049] Step S2: Form a tunneling oxide layer, wherein the tunneling oxide layer at least covers the upper surface and sidewall surface of the floating grid structure layer at the corner away from the source line;

[0050] Step S3: Forming word lines, wherein the word lines are located above the substrate on the side of the floating gate structure layer away from the source line; the word lines are wrapped around the floating gate structure layer through the tunneling oxide layer.

[0051] The following is combined Figures 2 to 8 A detailed structural schematic diagram of the flash memory formation process in the embodiments of the present invention is provided.

[0052] Please refer to Figure 2 A substrate 100 is provided. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator, or germanium-on-insulator. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. A floating gate oxide layer 101 and a floating gate layer 102 are sequentially formed on the substrate 100. The material of the floating gate oxide layer 101 includes silicon oxide; the material of the floating gate layer 102 includes polycrystalline silicon, which may be phosphorus-doped polycrystalline silicon.

[0053] A sacrificial layer 103 is formed on the floating gate layer 102. The sacrificial layer 103 has an opening 104 that exposes the surface of the floating gate layer 102. The material of the sacrificial layer 103 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the material of the sacrificial layer 103 includes silicon nitride. The method of forming the sacrificial layer 103 includes: forming a sacrificial material layer (not shown) on the floating gate layer 102; forming a patterned mask layer on the sacrificial material layer, the mask layer exposing a portion of the sacrificial material layer; etching the sacrificial material layer using the mask layer as a mask to form the sacrificial layer 103 and the opening 104 located within the sacrificial layer 103; and removing the mask after forming the sacrificial layer 103. The opening 104 provides space for the subsequent formation of the first sidewall 105, the second sidewall 106, and the source line 107.

[0054] Please refer to Figure 3 After the sacrificial layer 103 is formed, the first sidewall 105, the second sidewall 106 and the source line 107 (erasure grid) are formed sequentially in the opening 104.

[0055] Specifically, a first sidewall 105 is formed on both sides of the opening 104. The material of the first sidewall 105 includes a dielectric material, which includes silicon oxide or silicon oxynitride. The material of the first sidewall 105 is different from the material of the sacrificial layer 103. The method of forming the first sidewall 105 includes: forming a first sidewall 105 layer (not shown) on the surface and bottom surface of the sidewall of the opening 104 and on the sacrificial layer 103; etching back the first sidewall 105 layer until the surface of the floating gate layer 102 is exposed, thus forming the first sidewall 105. Using the first sidewall 105 as a mask layer, etching is used to remove the floating gate layer 102 and the floating gate oxide layer 101 located between the first sidewalls 105 on both sides of the opening 104 to expose the surface of the substrate 100; this etching can be performed using a dry etching process or a wet etching process. A second sidewall 106 is formed, covering the sidewalls of the floating gate oxide layer 101, the sidewalls of the floating gate layer 102, and a portion of the sidewall of the first sidewall 105. The substrate 100 is exposed between the second sidewalls 106 within the opening 104. The material of the second sidewall 106 includes a dielectric material, such as silicon oxide or silicon oxynitride. The first sidewall 105 and the second sidewall 106 serve to electrically isolate the subsequently formed source line 107 from the floating gate.

[0056] A source line 107 (erasure gate) is formed between the second sidewalls 106 and the first sidewall 105 on both sides of the opening 104, with the bottom of the source line 107 located on the substrate 100. The method for forming the source line 107 includes: forming a source line layer (not shown) within the opening 104 and on the sacrificial layer 103; planarizing the source line layer until the surface of the sacrificial layer 103 is exposed; and forming the source line 107 between the second sidewalls 106 and the first sidewall 105 on both sides of the opening 104; the material of the source line 107 is polycrystalline silicon. The process for forming the source line layer is a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition.

[0057] Please refer to Figure 4 The process of removing the sacrificial layer 103 includes dry etching or wet etching.

[0058] Please refer to Figure 5An isolation layer 108 is formed, covering the sidewall surfaces of the first sidewalls 105 on both sides of the source line 107 away from the source line 107 and the surface of the floating gate layer 102. The isolation layer 108 is made of at least one of oxide, silicon oxynitride, silicon carbon oxynitride, or silicon carbonitride. The isolation layer 108 is used to reduce the stress between the subsequently formed offset layer 109 and the first sidewalls 105 and the floating gate layer 102. An offset layer 109 is formed, covering the sidewall surfaces of the isolation layer 108 on both sides of the source line 107 away from the source line 107. The bottom of the offset layer 109 contacts the isolation layer 108. The offset layer 109 is made of at least one of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride. The width of the offset layer 109 can be controlled by wet etching with hot phosphoric acid or HF solution. Forming the offset layer 109 specifically includes: forming an offset material layer (not shown), the offset material layer being located on the sidewall of the isolation layer 108 away from the source line 107, and the bottom portion of the offset material layer covering the isolation layer 108 on the surface of the floating gate structure layer; wet etching a portion of the width of the offset material layer, and finally etching the remaining width of the offset material layer as the offset layer 109; controlling and adjusting the width of the offset layer 109 by wet etching, the width of the offset layer 109 being related to the thickness of the floating gate in the floating gate structure layer. The width of the offset layer 109 needs to be determined by multiplying the thickness of the floating gate layer 102 (i.e., the thickness of the floating gate) by a certain coefficient.

[0059] Please refer to Figure 6 The portion of the isolation layer 108 located on the surface of the floating gate layer 102 and not covered by the offset layer 109 is etched, while the portion of the isolation layer 108 located on the surface of the floating gate layer 102 and covered by the offset layer 109 is retained. A floating gate structure layer is formed, which includes a stacked floating gate oxide layer 101 and a floating gate 112. Specifically, the offset layers 109 on both sides of the source line 107 are etched away from the floating gate layer 102 and the floating gate oxide layer 101 on the side away from the source line 107, until the surface of the substrate 100 is exposed; the remaining floating gate layer is etched to form the floating gate 112. The etching process for forming the floating gate structure layer can be an anisotropic dry etching process or an anisotropic wet etching process.

[0060] The offset layer 109 and the isolation layer 108 expose right angles at the corners of the floating gates 112 on both sides of the source line 107. The offset layer 109 and the isolation layer 108 expose a portion of the width of the floating gates 112 on both sides of the source line 107 away from the source line 107, so that a tunneling oxide layer 110 located at the corner of the floating gate (especially on the upper surface) can be formed subsequently, so that the word lines 111 formed subsequently can better wrap the floating gates 112 and improve the erasing effect.

[0061] Please refer to Figure 7A tunneling oxide layer 110 is formed; the tunneling oxide layer 110 at least covers the upper surface and sidewall surface of the corner of the floating gate structure layer away from the source line 107. Exemplarily, the tunneling oxide layer 110 covers the sidewall surfaces of the offset layer 109, the isolation layer 108, the floating gate 112, and the floating gate oxide layer 101 on both sides of the source line 107, as well as the surface of the substrate 100. The material of the tunneling oxide layer 110 includes a dielectric material, which may include silicon oxide or silicon oxynitride.

[0062] Please refer to Figure 8 and Figure 9 After forming the tunneling oxide layer 110, word lines 111 are formed, filling the enclosed space of the tunneling oxide layer 110. Word lines 111 can form a fan-shaped structure, and the material of word lines 111 can be polycrystalline silicon. The process for forming the word line 111 layer is a deposition process, such as ion-pumped chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. Next, ion implantation is performed on the substrate 100 on the side of word lines 111 away from the source line 107 to form a drain-doped region 113. The drain-doped region 113 is used for subsequent electrical connection bit lines. After forming the word lines 111 and the drain-doped region 113, the flash memory is further subjected to annealing.

[0063] For flash memory erase operations, the corner of floating gate 112 is required ( Figure 8 The electric field strength is high (within the circle). Two main factors affect the electric field strength: one is the degree of enclosure of the word line 111 around the corner of the floating gate 112; a good enclosure results in a strong electric field, facilitating erasing. The other is the voltage difference between the word line 111 and the floating gate 112. The higher the sidewall of the floating gate 112 (i.e., the greater its thickness Y), the greater the coupling rate between the word line 111 and the floating gate 112. This results in a smaller voltage difference between the word line 111 and the floating gate 112 (erasing primarily involves applying voltage to the word line 111, which couples a voltage to the floating gate 112), making erasing less efficient.

[0064] Therefore, the tunneling oxide layer 110 of the present invention at least covers the upper surface and sidewall surface of the floating gate structure layer at the corner away from the source line; the word line 111 wraps around the corner of the floating gate structure layer through the tunneling oxide layer 110, increasing the wrapping at the corner and enhancing the corner field strength. Furthermore, right angles offer better process stability. Additionally, the height Y of the floating gate 112 can be reduced, thus reducing the coupling of the word line 111 to the floating gate 112, resulting in a larger voltage difference, which is beneficial for erasing. The thickness of the floating gate 112 is, for example, 200 angstroms to 400 angstroms.

[0065] In the actual manufacturing process, the width X of the tunneling oxide layer 110 covering the upper surface of the floating gate 112 is determined based on the actual measured thickness Y of the floating gate 112. Width X represents the degree to which the word line 111 covers the upper surface of the corner of the floating gate 112. Width X is also the width of the floating gate 112 exposed by the offset layer 109 and the isolation layer 108. The size of width X is achieved by adjusting the width of the offset layer 109, thus establishing a feedback mechanism. After the initial formation of the offset layer 109, its lateral width can be controlled and adjusted using wet etching with HF to form the final offset layer 109. The final width of the offset layer 109 needs to be determined by multiplying the thickness Y of the floating gate 112 by a certain coefficient.

[0066] The increased degree to which the word line 111 wraps around the floating gate 112 enhances the electric field strength during erasure, facilitating the erasure operation. Therefore, the degree to which the word line 111 wraps around the floating gate can be adjusted to regulate the erasure effect. This invention controls the tunneling horizontal portion 110a of the tunneling oxide layer 110 by adjusting the width of the offset layer 109. Figure 8 The width of the circle indicates that the vertical tunneling portion 110b covers the side of the floating gate 112, and the horizontal tunneling portion 110a covers the upper edge of the corner of the floating gate 112. The part of the word line 111 that wraps around the floating gate is the part of the floating gate 112 covered by the horizontal tunneling portion 110a and the vertical tunneling portion 110b. The word line 111 wraps around the corner of the floating gate 112 through the tunneling oxide layer 110, increasing the wrapping at the corner and improving the electric field strength at the corner, thereby improving the erasing effect. At the same time, it is necessary to control the size of the corner. If it is too large, it will increase the coupling effect between the word line 111 and the floating gate 112, reduce the voltage difference between the word line 111 and the floating gate 112, which is not conducive to erasing; if the corner is too small, the wrapping of the word line 111 around the floating gate 112 is poor, and the electric field strength at the corner tip is weak. Preferably, the thickness at the corner, i.e., the thickness Y of the floating gate 112, ranges from 200 angstroms to 400 angstroms; the width at the corner, i.e., the width X of the floating gate 112 exposed by the offset layer 109 and the isolation layer 108, ranges from 1 / 7 to 1 / 3 in ratio to the thickness Y. Furthermore, this near-90-degree corner exhibits better process stability. During erasure, electrons on the side of the floating gate 112 away from the source line 107 pass through the tunneling oxide layer 110 and enter the word line 111 under high voltage to achieve erasure. This invention reduces the thickness of the floating gate 112, decreases the coupling ratio between the word line and the floating gate, and facilitates increasing the voltage difference between the word line and the floating gate, thereby improving the erasure effect. The greater the voltage difference between the word line 111 and the floating gate, the better the erasure effect.

[0067] This invention provides a flash memory, such as... Figure 8 As shown, it includes:

[0068] A substrate 100 is formed on the substrate 100, and a floating gate structure layer and a first sidewall 105 are formed sequentially from bottom to top on the substrate 100 on both sides of the source line 107; and the first sidewall 105 is located above the floating gate structure layer on the side closer to the source line 107.

[0069] The tunneling oxide layer 110 covers at least the upper surface and sidewall surface of the floating grid structure layer at the corner away from the source line 107.

[0070] Word line 111 is located above the substrate 100 on the side of the floating gate structure layer away from the source line 107;

[0071] The word line 111 wraps the floating grid structure layer through the tunnel oxide layer 110.

[0072] Specifically, the floating gate structure layer includes a stacked floating gate oxide layer 101 and a floating gate 112. The corner of the floating gate 112 on the side away from the source line 107 is a right angle. The thickness of the floating gate 112 ranges from 200 angstroms to 400 angstroms. An offset layer 109 is formed on the sidewall of the first sidewall 105 on the side away from the source line 107. The offset layer 109 exposes the upper surface of the floating gate structure layer on the side away from the source line 107, and the tunneling oxide layer 110 also covers the sidewall surface of the offset layer 109. The tunneling horizontal portion 110a of the tunneling oxide layer 110 is controlled by the width of the offset layer 109. Figure 8 The width of the offset layer 109 (within the circle). The material of the offset layer 109 is, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride. The width of the offset layer 109 can be controlled by hot phosphoric acid wet etching.

[0073] The flash memory also includes an isolation layer 108, which is L-shaped and includes a connected horizontal isolation portion and an isolation vertical isolation portion. The horizontal isolation portion is located between the bottom of the offset layer 109 and the floating gate structure layer, and the vertical isolation portion is located between the sidewall of the first sidewall 105 and the offset layer 109. The isolation layer 108 is used to reduce the stress between the subsequently formed offset layer 109 and the first sidewall 105 and the floating gate layer 102.

[0074] The flash memory also includes a second sidewall 106 located on the substrate 100 on both sides of the source line 107. The sidewall of the second sidewall 106 away from the source line 107 is adjacent to the sidewall of the first sidewall 105 near the source line 107. The second sidewall 106 covers the sidewall of the floating gate structure layer near the source line 107.

[0075] In summary, this invention provides a flash memory and its fabrication method. The flash memory includes: a substrate, on which a source line is formed, and on both sides of the source line, a floating gate structure layer and a first sidewall are formed sequentially from bottom to top on the substrate; the first sidewall is located above the floating gate structure layer on the side closer to the source line; a tunneling oxide layer, which at least covers the upper surface and sidewall surface of the corner of the floating gate structure layer away from the source line; and word lines, located above the substrate on the side of the floating gate structure layer away from the source line. In this invention, the word lines wrap around the corner of the floating gate structure layer through the tunneling oxide layer, increasing the wrapping at the corner and improving the electric field strength at the corner, thereby improving the erasing effect. Simultaneously, the thickness of the floating gate structure layer can be reduced, decreasing the coupling ratio between the word line and the floating gate, which is beneficial for increasing the voltage difference between the word line and the floating gate, thus improving the erasing effect. The complex process of forming the floating gate sharp corners is eliminated, ensuring the reliability of the flash memory.

[0076] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0077] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A flash memory, characterized by comprising: The flash memory comprises: a substrate, a source line is formed on the substrate, a floating gate structure layer and a first sidewall are sequentially formed on the substrate on both sides of the source line from bottom to top, and the first sidewall is located above the floating gate structure layer on the side close to the source line; the material of the first sidewall comprises dielectric material; the floating gate structure layer comprises a floating gate oxide layer and a floating gate which are sequentially located on the substrate; an isolation layer and a shift layer are sequentially formed on the sidewall of the first sidewall away from the source line; a tunneling oxide layer, the tunneling oxide layer covers at least the upper surface and the sidewall surface of the corner of the floating gate structure layer away from the source line; the ratio of the width of the corner to the thickness of the corner ranges from 1 / 7 to 1 / 3; the thickness of the corner is the thickness of the floating gate, and the width of the corner is the width of the floating gate exposed by the shift layer and the isolation layer; a word line, the word line is located above the substrate on the side of the floating gate structure layer away from the source line; the word line wraps the floating gate structure layer through the tunneling oxide layer.

2. The flash memory of claim 1, wherein, The shift layer exposes the upper surface of the floating gate structure layer away from the source line, and the tunneling oxide layer also covers the sidewall surface of the shift layer away from the source line.

3. The flash memory of claim 2, wherein, The isolation layer is in L shape and comprises an isolation horizontal part and an isolation vertical part which are connected, the isolation horizontal part is located between the bottom of the shift layer and the floating gate structure layer, and the isolation vertical part is located between the sidewall of the first sidewall and the shift layer.

4. The flash memory of claim 1, wherein, The flash memory further comprises a second sidewall, the second sidewall is located on the substrate on both sides of the source line, the sidewall of the second sidewall away from the source line is adjacent to the sidewall of the first sidewall close to the source line, and the second sidewall covers the sidewall of the floating gate structure layer close to the source line.

5. The flash memory of claim 1, wherein, The corner of the floating gate structure layer away from the source line is a right angle.

6. The flash memory of claim 1, wherein, The thickness of the floating gate ranges from 200 angstroms to 400 angstroms.

7. A method for fabricating a flash memory, the method comprising: The flash memory comprises: a substrate, a source line is formed on the substrate, a floating gate structure layer and a first sidewall are sequentially formed on the substrate on both sides of the source line from bottom to top, and the first sidewall is located above the floating gate structure layer on the side close to the source line; the material of the first sidewall comprises dielectric material; a tunneling oxide layer, the tunneling oxide layer covers at least the upper surface and the sidewall surface of the corner of the floating gate structure layer away from the source line; the ratio of the width of the corner to the thickness of the corner ranges from 1 / 7 to 1 / 3; a word line, the word line is located above the substrate on the side of the floating gate structure layer away from the source line; the word line wraps the floating gate structure layer through the tunneling oxide layer.

8. The method of claim 7, wherein the step of forming the floating gate is performed by a method comprising: The flash memory comprises: a substrate, a source line is formed on the substrate, a floating gate structure layer and a first sidewall are sequentially formed on the substrate on both sides of the source line from bottom to top, and the first sidewall is located above the floating gate structure layer on the side close to the source line; the material of the first sidewall comprises dielectric material; a tunneling oxide layer, the tunneling oxide layer covers at least the upper surface and the sidewall surface of the corner of the floating gate structure layer away from the source line; the ratio of the width of the corner to the thickness of the corner ranges from 1 / 7 to 1 / 3; a word line, the word line is located above the substrate on the side of the floating gate structure layer away from the source line; the word line wraps the floating gate structure layer through the tunneling oxide layer. forming a second side wall covering the sidewalls of the floating gate oxide layer on both sides, the sidewalls of the floating gate layer and part of the sidewalls of the first side wall.

9. The method for manufacturing a flash memory as described in claim 8, characterized in that, After forming the second side wall, further comprising: forming a source line between the second side walls on both sides of the opening and between the first side walls, the bottom of the source line being on the substrate; removing the sacrificial layer; etching the first side wall on both sides of the source line away from the floating gate layer and the floating gate oxide layer on the side of the source line, and etching the remaining floating gate layer and the floating gate oxide layer to form the floating gate structure layer.

10. The method for manufacturing a flash memory as described in claim 7, characterized in that, After providing the substrate and before forming the tunneling oxide layer, further comprising: forming an isolation layer covering the sidewalls of the first side wall on both sides of the source line away from the source line and part of the surface of the floating gate structure layer; forming a biasing material layer on the sidewalls of the isolation layer away from the source line, and the bottom of the biasing material layer covering part of the isolation layer on the surface of the floating gate structure layer; wet etching part of the width of the biasing material layer, and finally remaining the biasing material layer with a certain width as a biasing layer; the width of the biasing layer is controlled by wet etching, and the width of the biasing layer needs to be determined according to the thickness of the floating gate in the floating gate structure layer.

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