A flexible integrated avionics system

Abstract

The present invention discloses a flexible integrated avionics system, comprising a host radio frequency adapter interface, a PXIe backplane, an embedded controller, a signal exciter, an amplitude and phase consistency test card, a power frequency meter, and a universal control interface card. The PXIe backplane is respectively connected to the universal control interface card, the amplitude and phase consistency test card, the power frequency meter, and the embedded controller. The host radio frequency adapter interface is respectively connected to the device to be tested and the amplitude and phase consistency test card, the power frequency meter, the signal exciter, and the external radio frequency adapter. The universal control interface card is connected to the device to be tested via the universal control interface. The host radio frequency adapter interface is used to construct a test topology. The present invention implements a modular design, and its component modules can be quickly assembled and unassembled and flexibly matched to achieve functional inspections and quantitative testing of performance indicators of different products to be tested. It also achieves standardization and miniaturization of the host radio frequency adapter interface.

Description

Technical Field

[0001] The present invention belongs to the technical field of avionics systems, and in particular relates to a flexible integrated avionics system. Background Art

[0002] Avionics systems (dual-use tester equipment) are primarily used to perform functional checks and in-depth testing of key performance indicators of the product under test. These tests include interrogation and response mode checks, transmit operating frequency testing, transmit peak power testing, transmit pulse envelope testing, receive decoding sensitivity testing, receive dynamic range testing, multi-channel S-parameter testing, and interface functional testing. Dual-use tester equipment is used to perform functional checks and quantitative performance testing of JZXWYD aircraft at the equipment site or in the laboratory. It can localize faults down to the LRU (LRM) level and is used for scheduled equipment inspection and maintenance support. Currently, there are numerous in-field testers for airborne equipment in China. Due to differences in aircraft models and control devices, many of these testers are designed as non-standard equipment, resulting in a wide variety of structures. With the advancement of aviation technology, the functions required of subsystem control boxes are increasing, requiring them to possess higher levels of intelligence. This increases the complexity of control logic, the number of channels, and the control methods. The use of benchtop or modular instruments with large switch matrices results in limited versatility and bulky test systems.

[0003] For portable in-field test equipment, each development requires a redesigned enclosure based on the internal circuitry. This not only increases design time and development costs, but also results in a wide variety of appearances and internal layouts, making subsequent maintenance and management quite difficult. The harsh installation conditions, cumbersome disassembly, and complex structure reduce practicality, reliability, mobility, and maintainability. Traditional in-field test equipment no longer meets the requirements for intelligent digital controller performance testing and the harsh test environments of the field. To meet the technical performance testing requirements of the new generation of aircraft ground support equipment, the next-generation avionics system must be highly reliable, easy to maintain, move, connect, and capable of field operation. Advanced performance, flexibility, modularity, and scalability are required to design a highly stable and reliable integrated avionics system. Summary of the Invention

[0004] The purpose of the present invention is to provide a flexible integrated avionics system to solve the above problems.

[0005] The present invention is mainly achieved through the following technical solutions:

[0006] A flexible integrated avionics system includes a host radio frequency adapter interface, a PXIe backplane, an embedded controller, a signal exciter, an amplitude and phase consistency test card, a power frequency meter, and a universal control interface card. The PXIe backplane is respectively connected to the universal control interface card, the amplitude and phase consistency test card, the power frequency meter, and the embedded controller. The host radio frequency adapter interface is respectively connected to the device under test and the amplitude and phase consistency test card, the power frequency meter, the signal exciter, and the external radio frequency adapter. The universal control interface card is connected to the device under test via the universal control interface. The host radio frequency adapter interface is used to construct a test topology. The host RF adapter interface includes a host adapter interface unit and a universal switch control module, and the universal switch control module is respectively connected to the embedded controller and the external RF adapter; the host adapter interface unit includes a high-power signal synthesis and attenuation unit and a small signal distribution and conditioning unit, and the high-power signal synthesis and attenuation unit is connected to the end of the product to be tested, and is connected to the universal switch control module through the small signal distribution and conditioning unit. The small signal distribution and conditioning unit is provided with several test branches, and the test branches are provided with electronic switches, and are correspondingly connected to the amplitude and phase consistency test card, the power frequency meter, and the signal exciter.

[0007] In order to better realize the present invention, further, the high-power signal synthesis and attenuation unit is provided with a power combiner, a fixed attenuator, a first coaxial switch, and a coupler corresponding to the end of the product to be tested. The power combiner is used to receive and synthesize the multi-channel antenna interface signal output by the product to be tested, and the first coaxial switch is respectively connected to the small signal distribution and conditioning unit and the coupler, and is used to output the RF_X1 signal to the small signal distribution and conditioning unit. The output end of the coupler is connected to the small signal distribution and conditioning unit, and is used to output the power signal RF_X2 to the small signal distribution and conditioning unit; the small signal distribution and conditioning unit is respectively provided with an RF_X1 signal test branch and an RF_X2 signal test branch, and the RF_X2 signal test branch is connected to the third electronic switch, the third electronic switch is connected to the fourth electronic switch, and the fourth electronic switch is connected to the power frequency meter; the RF_X1 signal test branch is connected to the fifth electronic switch, and the fifth electronic switch is connected to the vector network port2 port for phase consistency testing.

[0008] In order to better realize the present invention, further, the high-power signal synthesis attenuation unit also includes a first circulator, a second circulator, and a second coaxial switch arranged in sequence from front to back, and a fixed attenuator and a programmable attenuator are connected in parallel between the first circulator and the second circulator; the output end of the coupler is also connected to the first circulator, and the small signal distribution and conditioning unit is correspondingly provided with an RF_X3 signal test branch for outputting the Ω signal of the product to be tested, and a third circulator and a fourth circulator are arranged in sequence on the RF_X3 signal test branch, and a programmable attenuator and a fixed attenuator are arranged in parallel between the third circulator and the third circulator, the fourth circulator is connected to the second electronic switch, and the second electronic switch is connected to the amplifier and the third electronic switch in sequence; the second coaxial switch is respectively connected to the RF_X3 signal test branch and the exciter.

[0009] In order to better implement the present invention, the small signal distribution and conditioning unit further includes an external source test branch, on which a ninth electronic switch is provided, and the ninth electronic switch is connected to the fourth electronic switch and the eighth electronic switch, respectively. A first N-FET switch, a second N-FET switch, a second amplifier, and a third amplifier are sequentially provided between the eighth electronic switch and the ninth electronic switch.

[0010] In order to better implement the present invention, further, the amplitude and phase consistency test card includes a port1 port, a port2 port, a transmitting module, a return module, a sampling circuit, a DDS signal source, a control circuit, a local oscillator and a clock circuit, the sampling circuit is respectively connected to the transmitting module and the return module, the transmitting module includes a first directional coupler and a second directional coupler connected in sequence from front to back, and a first mixer and a second mixer connected in sequence from front to back, the first directional coupler and the second directional coupler are respectively connected to the sampling circuit through the first mixer and the second mixer, and the second directional coupler is connected to the port1 port; the transmitting module includes a third directional coupler, a fourth directional coupler, a third mixer and a fourth mixer, the output end of the third directional coupler is connected to the fourth directional coupler, the third directional coupler and the fourth directional coupler are respectively connected to the sampling circuit through the third mixer and the fourth mixer, the third directional coupler is connected to the port2 port, the DDS signal source is respectively connected to the first directional coupler and the fourth directional coupler, and the local oscillator and the clock circuit are respectively connected to the first mixer and the fourth mixer.

[0011] In order to better realize the present invention, further, the signal exciter includes a baseband signal processing unit and a radio frequency signal processing unit connected to each other, and the radio frequency signal processing unit includes a radio frequency transmitting circuit, a power amplifier circuit, an antenna interface circuit, and a radio frequency receiving circuit connected in sequence from front to back; the radio frequency receiving circuit includes a second attenuator, a power divider, a second operational amplifier, a detector, and a frequency source, a phase-locked loop, an attenuator, a filter, a first operational amplifier, a mixer, and a filter connected in sequence from front to back, the second attenuator is connected to the power divider, and the power divider is respectively connected to the second operational amplifier and the detector, and the second operational amplifier is connected to the mixer through a bandpass filter; the second attenuator is connected to the antenna interface circuit, the detector is connected to the baseband signal processing unit, and the mixer is connected to the baseband signal processing unit through a filter.

[0012] In order to better implement the present invention, the baseband signal processing unit further includes an FPGA and a microcontroller unit MCU connected to the FPGA, a digital signal processing module, a low-speed ADC, a high-speed ADC, and a digital-to-analog converter. The FPGA is connected to the embedded controller through a PXIe bus, the FPGA is connected to the radio frequency transmission circuit through the digital-to-analog converter, the detector is connected to the low-speed ADC, and the mixer is connected to the high-speed ADC through a filter; the FPGA is connected to the GPS / BD receiver through the microcontroller unit MCU, and the GPS / BD receiver is connected to the GPS antenna.

[0013] In order to better realize the present invention, further, the power frequency meter includes a high-speed acquisition circuit, a trigger circuit, and a clock module, a radio frequency input and conditioning module, a detection circuit, a comparison circuit, and a control circuit connected in sequence from front to back, and the control circuit is connected to the embedded controller through a PXIe bus; the high-speed acquisition circuit is respectively connected to the clock module, the radio frequency input and conditioning module, the detection circuit, and the control circuit, and the control circuit is connected to the trigger circuit; the clock module is used to provide a clock signal for the high-speed acquisition circuit, and the high-speed acquisition circuit is used to collect the detection signal and the intermediate frequency signal; the radio frequency input and conditioning module includes a protection diode, a broadband SPDT switch, an attenuator, a radio frequency switch, and a distributor connected in sequence from front to back, and the broadband SPDT switch is connected to the radio frequency switch; the output end of the distributor is respectively connected to the frequency conversion module and the detection circuit, the frequency conversion module is connected to the high-speed acquisition circuit, and the frequency conversion module is used to down-convert the signal to be measured into an intermediate frequency signal.

[0014] In order to better implement the present invention, the frequency conversion module further includes a programmable attenuator, a first SPDT switch, a first power amplifier, a second SPDT switch, a high-pass filter, a mixer, a low-pass filter and a second power amplifier connected in sequence from front to back.

[0015] The beneficial effects of the present invention are as follows:

[0016] (1) The present invention realizes a modular design, and its various modules can be quickly assembled and unassembled and flexibly matched to realize functional inspection and quantitative testing of performance indicators of different products to be tested. A standard 3U PXIe embedded controller is realized through the PXIe backplane. The system is based on a hybrid bus architecture based on the open PXIe bus, which organically combines various components into one, reducing the size and weight of the equipment, increasing the scalability and compatibility of the equipment, facilitating the maintenance and repair of the equipment, and making it more able to meet the application needs of actual combat. At the same time, due to the standardization of the control interface and external structure of the host RF adapter interface, it can adapt to different products to be tested by replacing different host RF adapter interfaces, greatly enriching the functional flexibility of the detector. At the same time, in order to meet military purposes, the detector adopts a modular design, and each module has electromagnetic shielding, low temperature start-up, wide operating temperature range, salt spray resistance and other designs.

[0017] (2) The present invention achieves high integration and universalization of control and measurement modules. By summarizing the commonly used avionics interfaces of the equipment to be tested, a universal control interface card is established using a PXIe interface carrier board + functional interface daughter card. Its interfaces cover various forms such as 1553B, ARINC429, discrete interfaces, and high-speed serial ports. A standard external interface is formed through the massive connectors on the chassis panel to adapt to different application scenarios.

[0018] (3) The present invention has designed a universal power frequency meter and amplitude-phase consistency measurement card, which covers the performance index testing of common avionics equipment to be tested, greatly reducing the volume and weight of the system. The amplitude-phase consistency test card is mainly used for amplitude-phase consistency testing of TR components, and has isolation, standing wave and other test functions. The signal exciter designed by the present invention can realize the encoding and decoding and function detection of common avionics equipment communication signals by burning FPGA programs online, such as the communication functions of A, C, S and other modes of secondary radar, TACAN, DME, VOR, etc.

[0019] (4) The present invention achieves standardization and miniaturization of the host RF adapter interface. Conventional interface adapters are usually bulky. The present invention separates the control circuit from the switch topology, making the host RF adapter interface more miniaturized and modular. The internal topology can be changed according to test requirements. By cooperating with the electronic switch and the coaxial switch, each takes advantage of its strengths, the performance of the switch matrix is ​​improved while the size of the switch matrix is ​​reduced. The host RF adapter interface uses a universal control interface on the outside, which can be quickly replaced by plugging and unplugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is an overall principle block diagram of the avionics system of the present invention;

[0021] Figure 2 This is the principle block diagram of the universal interface control card;

[0022] Figure 3 This is the overall principle block diagram of the power frequency meter;

[0023] Figure 4 It is a structural diagram of the RF input and conditioning module;

[0024] Figure 5 It is a structural diagram of the frequency conversion module;

[0025] Figure 6 It is a structural diagram of the clock module;

[0026] Figure 7 It is a structural diagram of the detection module;

[0027] Figure 8 It is a structural diagram of the high-speed acquisition circuit;

[0028] Figure 9 It is a structural diagram of the comparison circuit;

[0029] Figure 10 It is a structural diagram of the trigger circuit;

[0030] Figure 11 It is a structural diagram of the control circuit;

[0031] Figure 12 This is the measurement flow chart of the power frequency meter;

[0032] Figure 13 This is the overall principle block diagram of the signal exciter;

[0033] Figure 14 This is a principle block diagram of the baseband signal processing unit;

[0034] Figure 15 This is a principle block diagram of the radio frequency signal processing unit;

[0035] Figure 16 This is the overall structural schematic diagram of the host RF adapter interface;

[0036] Figure 17 The overall structural principle diagram of the host adapter interface unit;

[0037] Figure 18 This is the structural principle diagram of the high-power signal synthesis attenuation unit;

[0038] Figure 19 The structural principle diagram of the small signal distribution conditioning unit;

[0039] Figure 20This is the structural principle diagram of the universal switch control module;

[0040] Figure 21 This is the structural principle diagram of the amplitude and phase consistency test card. DETAILED DESCRIPTION

[0041] Example 1:

[0042] A flexible integrated avionics system, such as Figure 1 、 Figure 16 As shown, it includes a host RF adapter interface, a PXIe backplane, an embedded controller, a signal exciter, an amplitude and phase consistency test card, a power frequency meter, and a universal control interface card. The PXIe backplane is connected to the universal control interface card, the amplitude and phase consistency test card, the power frequency meter, and the embedded controller respectively. The host RF adapter interface is connected to the device under test and the amplitude and phase consistency test card, the power frequency meter, the signal exciter, and the external RF adapter respectively; the universal control interface card is connected to the device under test through the universal control interface; the host RF adapter interface is used to build a test topology. The frequency adaptation interface includes a host adaptation interface unit and a universal switch control module, and the universal switch control module is respectively connected to the embedded controller and the external RF adapter; the host adaptation interface unit includes a high-power signal synthesis and attenuation unit and a small signal distribution and conditioning unit, and the high-power signal synthesis and attenuation unit is connected to the product end to be tested, and is connected to the universal switch control module through the small signal distribution and conditioning unit. The small signal distribution and conditioning unit is provided with several test branches, and the test branches are provided with electronic switches, and are correspondingly connected to the amplitude and phase consistency test card, power frequency meter, and signal exciter.

[0043] Preferably, if Figure 17-Figure 19 As shown, the high-power signal synthesis and attenuation unit is provided with a power combiner, a fixed attenuator, a first coaxial switch, and a coupler corresponding to the product to be tested. The power combiner is used to receive and synthesize the multi-channel antenna interface signal output by the product to be tested. The first coaxial switch is respectively connected to the small signal distribution and conditioning unit and the coupler, and is used to output the RF_X1 signal to the small signal distribution and conditioning unit. The output end of the coupler is connected to the small signal distribution and conditioning unit, and is used to output the power signal RF_X2 to the small signal distribution and conditioning unit; the small signal distribution and conditioning unit is respectively provided with an RF_X1 signal test branch and an RF_X2 signal test branch, the RF_X2 signal test branch is connected to the third electronic switch, the third electronic switch is connected to the fourth electronic switch, and the fourth electronic switch is connected to the power frequency meter; the RF_X1 signal test branch is connected to the fifth electronic switch, and the fifth electronic switch is connected to the vector network port2 port for phase consistency testing.

[0044] Preferably, if Figure 17-Figure 19As shown, the high-power signal synthesis attenuation unit also includes a first circulator, a second circulator, and a second coaxial switch arranged in sequence from front to back, and a fixed attenuator and a programmable attenuator are connected in parallel between the first circulator and the second circulator; the output end of the coupler is also connected to the first circulator, and the small signal distribution and conditioning unit is correspondingly provided with an RF_X3 signal test branch for outputting the Ω signal of the product to be tested, and a third circulator and a fourth circulator are sequentially arranged on the RF_X3 signal test branch, and a programmable attenuator and a fixed attenuator are arranged in parallel between the third circulator and the third circulator, the fourth circulator is connected to the second electronic switch, and the second electronic switch is sequentially connected to the amplifier and the third electronic switch; the second coaxial switch is respectively connected to the RF_X3 signal test branch and the exciter.

[0045] The present invention realizes a modular design, and its component modules can be quickly assembled and unassembled, and flexibly matched to realize functional inspection and quantitative testing of performance indicators of different products to be tested. The present invention realizes the standardization and miniaturization of the RF host RF adapter interface. Conventional interface adapters are usually bulky. The present invention separates the control circuit from the switch topology, making the host RF adapter interface more miniaturized and modular. The internal topology can be changed according to the test requirements. By cooperating with the electronic switch and the coaxial switch, each can take advantage of its strengths, thereby improving the performance of the switch matrix and reducing the size of the switch matrix. The external part of the host RF adapter interface adopts a universal control interface, which can be quickly replaced by plugging and unplugging.

[0046] Example 2:

[0047] A flexible integrated avionics system, such as Figure 1 As shown, the system's hardware structure can be roughly divided into a host computer and an external RF adapter. The host computer includes the chassis (including the display, PXIe backplane, and universal control interface, among other external connectors on the chassis). The PXIe test control extension includes an embedded controller, a power frequency meter, an amplitude and phase consistency test card, a universal control interface card, a signal exciter, a host RF adapter interface, and a DC power supply. The embedded controller is the core of the system and the carrier of the system software. It provides serial port signals to control the instrument signal conditioning and switching modules, and provides external interfaces such as a display control, a function keyboard, and USB. The power frequency meter primarily detects the peak power, frequency, and pulse parameters of the test signal. The amplitude and phase consistency test card primarily tests the S parameters of the device under test. The universal control interface card primarily provides serial port and discrete line signals for interaction with the device under test, and can display simple waveforms of the device's intermediate signals and control the device under test. The DC power supply primarily converts the 28V DC power supply into the various power supplies required by the PXIe backplane, powering the test instruments and external modules under test. Each module is interconnected with the PXIe backplane through a custom backplane connector.

[0048] The chassis preferably serves as the main structure for the instrument's components, providing mounting locations and interfaces for each component. It also provides interfaces with external devices under test, power supplies, and other equipment, as well as a human-machine interface. The chassis' external control interface utilizes a mass connector or aviation connector to form a universal interface, adapting to different devices under test through external connector conversion.

[0049] The PXIe test control extension is preferably designed with a universal PXIe hybrid slot architecture, featuring at least eight slots: one system slot, five hybrid slots, and two custom interface slots, each housing modules such as an embedded controller, a power frequency meter, an amplitude and phase consistency test card, a universal control interface card, a signal exciter, and a quick-plug DC power supply. The overall architecture of the PXIe test control extension utilizes the PXIe open industrial bus. To meet the requirements of specific test projects, PXIe-based expansion slots are reserved, facilitating the addition of third-party modular instrumentation, enabling the system to better adapt to a wider range of testing needs.

[0050] Preferably, if Figures 16-20 As shown, the host RF adapter interface mainly completes the construction of the test topology between the RF path of the product to be tested and the internal power frequency meter, amplitude and phase consistency test card and other equipment. Its internal structure is mainly composed of RF components such as RF coaxial switches, attenuators, functional devices, circulators, etc. In order to simplify the form of the test topology, the RF adapter interface can be designed to be specifically for a certain type of product to be tested or all devices to be tested of a certain model. Its versatility is guaranteed as much as possible when the volume allows. When testing different products, all test tasks can be completed without replacing the RF adapter interface or only by replacing the RF adapter interface once. The host RF adapter interface also has the function of transferring interfaces such as universal control interface cards, amplitude and phase consistency test cards, and power frequency meters to external RF adapters. The host RF adapter interface is controlled by an embedded controller through the control port (RS422 and power supply) brought out by the PXIe backplane.

[0051] Preferably, the embedded controller is based on the COMe standard, integrating the chip interface functions and PXIe bus requirements to design a PXIe carrier board, thereby achieving a standard 3U PXIe embedded controller. Preferably, the COMe core unit utilizes Loongson's Loongson 2H processor, which utilizes a MIPS64 R2 core. The CPU integrates interfaces such as VGA, LCD, PCI-E 2.0, SATA*2, USB 2.0*6, SPI, LPC, UART, I2C*2, and NAND, and supports Linux, VxWorks, ReWorks, and Android operating systems.

[0052] Preferably, if Figure 2As shown, the universal control interface card utilizes a PXIe bus carrier board and functional daughter cards. This approach allows for flexible implementation of various universal bus, discrete line, and data acquisition functions by replacing different functional daughter cards, offering strong scalability. By summarizing and integrating common aviation equipment control interfaces, the universal interface control card integrates aviation buses such as 1553B and ARINC429, as well as common discrete signals (such as blocking signals, OC, and TTL), CAN, and RS422, on a single board. This allows for adaptability to a wider range of devices under test (DUT) using minimal resources.

[0053] Example 3:

[0054] This embodiment is optimized based on embodiment 1 or 2. Figure 3-Figure 12 As shown, the power frequency meter mainly includes circuit units such as a radio frequency input and conditioning module, a clock module, a detection circuit, a comparison circuit, a high-speed acquisition circuit, a control circuit, a trigger circuit, and a power supply module. The clock module is used to provide a local oscillator and power calibration signal to the radio frequency input and conditioning module, and a clock signal to the high-speed acquisition circuit. The radio frequency input and conditioning module is used to down-convert the carrier to be measured into an intermediate frequency signal and provide it to the high-speed acquisition circuit, and to split the radio frequency carrier signal and provide it to the detection circuit after power division. The detection circuit is used to perform power detection on the input radio frequency signal and then divide it into two paths, one path being provided to the high-speed acquisition circuit for power and pulse parameter acquisition and analysis, and the other path being provided to the comparison circuit for trigger level comparison. The high-speed acquisition circuit is controlled by the control circuit and is used to collect the detection signal and the intermediate frequency signal, and transmit the data through the control circuit to the embedded controller for statistical analysis and frequency estimation. The comparison circuit is used to transmit the trigger level comparison result to the control circuit, which controls the sampling timing. The trigger unit is used to transmit an external trigger signal to the control circuit, and the control circuit controls the sampling timing according to the trigger signal. In addition, the power supply module is used to supply power to each circuit unit.

[0055] Preferably, if Figure 4 As shown, the RF input and conditioning module includes a protection diode, a broadband SPDT switch, an attenuator, an RF switch, and a power splitter. The protection diode, broadband SPDT switch, attenuator, and RF switch are connected in sequence. The broadband SPDT switch is connected to the RF switch. The RF switch, coupler, and power splitter are connected in sequence. The protection diode model is 0402ESDA-MLP1, the broadband SPDT switch model is MASW-002103-13630G, the attenuator model is FAC0606P, and the RF switch model is PE42540.

[0056] Preferably, if Figure 5As shown, the A0.1 output of the power divider is converted to an intermediate frequency signal through a frequency conversion module. The frequency conversion module includes a programmable attenuator, an SPDT switch, a power amplifier, an SPDT switch, a high-pass filter, a mixer, a low-pass filter, and a power amplifier, which are cascaded and output one by one. The programmable attenuator used is HMC624ALP4, the SPDT switch used is HMC232ALP4, the power amplifier used is SBB-3089, and the mixer used is M1-0008.

[0057] Preferably, if Figure 6 As shown in the figure, the clock module is mainly used to generate the Lo signal required by the RF conditioning circuit and the sampling clock signal required by the high-speed acquisition circuit. The VCO output frequency range of PLL2 in the HMC7044 is 2.4GHz to 3.2GHz. The clock signal fanned out by the HMC7044 is multiplied by the PLL chip ADF4355 to obtain the required Lo signal and DAC sampling clock signal B0.3.

[0058] Preferably, if Figure 7 As shown in the figure, the detection circuit includes devices such as attenuator, power amplifier, logarithmic detector, sample and hold, and SPDT. It is mainly used to detect the RF signal output by the RF conditioning module and output its pulse envelope signal for acquisition and analysis by the high-speed acquisition circuit. The attenuator used is PAT0510S, the power amplifier used is PHA-1+, the logarithmic detector used is ADL5511, the sample and hold is AD781, and the SPDT switch is NC7WV07P6X.

[0059] Preferably, if Figure 8 As shown in the figure, the high-speed acquisition circuit is mainly used to complete the data acquisition of RF signals and detection signals for the embedded controller to perform statistical analysis to obtain high-precision spectrum estimation and measurement and analysis of pulse envelope parameters. The ADC used is AD9208, which is a dual-channel, 14-bit, 3GSPS analog-to-digital converter.

[0060] Preferably, if Figure 9 As shown in the figure, the comparison circuit is mainly used to set the trigger level for the detection signal to generate a trigger signal. The generation of the trigger level is mainly achieved by AD5623. After B0.5 is sent to the controller, the controller can flexibly generate a sampling trigger signal according to the needs and the characteristics of the secondary radar and other factors.

[0061] Preferably, if Figure 10 As shown in the figure, the trigger circuit is mainly used to receive external trigger signals and transmit them to the controller for logic processing. Its main components include protection diode 0402ESD-MLP1, trigger 74LVCG132, etc.

[0062] Preferably, if Figure 11 As shown, the control circuit is mainly used to realize the control of various chips in the power frequency meter, the reading of sampled data, the processing of trigger signals and other logic, and transmit the data to the embedded controller through the PCIe bus to realize information interaction with the embedded controller. The FPGA chip model used in the present invention is XC7A200T-AFBG484I.

[0063] Preferably, if Figure 12 As shown, the power frequency meter's RF input and conditioning module can accept continuous RF signals or pulse-modulated signals within the -20dBm to +20dBm range. After entering the power frequency meter, the measured signal first passes through a large attenuation channel for initial power measurement. After determining the approximate input power range, an appropriate attenuation channel is selected and split into two paths by a power divider. One path is fed into a mixer for downconversion. The downconverted signal is then fed into a high-speed acquisition module for data acquisition. The other path is fed into a detection circuit, where a logarithmic detection module performs precise logarithmic detection on the signal to generate a detection signal. To maintain the measured signal's pulse width and edge characteristics, the logarithmic detection module must not alter the measured signal's envelope characteristics. The detection signal is ultimately fed into a high-speed acquisition circuit for acquisition and analysis of the pulse envelope characteristics and power level. The clock circuit provides the LO signal required for downconversion to the RF input and conditioning module and a high-speed sampling clock signal to the high-speed acquisition circuit. The comparator circuit compares the input detection signal with the set trigger level to generate the required sampling trigger signal. The control circuit controls the sampling and reading of the high-speed acquisition circuit using signals from the comparison circuit or external trigger circuit. The control circuit reads back and accumulates the collected data, which is then analyzed by the embedded controller using a combined FFT and CZT algorithm. Correction algorithms such as interpolation and deflection correction are then used to accurately estimate the signal frequency.

[0064] Because the FFT algorithm has a fence effect and limited sampling, the spectrum of the signal to be measured changes from a continuous spectrum to a discrete spectrum. Discrete spectral lines only appear at integer multiples of the position, so the actual spectral lines may be blocked and lost. Therefore, increasing the number of FFT calculation points can improve the spectral resolution. However, due to the limitation of short-term pulses, it is impossible to obtain sufficient limited data. Therefore, the number of calculation points is appropriately increased through accumulation. On this basis, according to the basic principle of CZT, it can be known that it can perform local sampling on the unit circle on the Z plane, that is, perform spectral analysis within a limited frequency range, that is, perform a denser spectral analysis between several FFT sampling points on the unit circle. This joint algorithm embodies a wavelet processing idea of ​​local amplification, which can greatly improve the spectral resolution while increasing the limited amount of calculation, thereby improving the frequency measurement accuracy.

[0065] The power frequency meter is mainly used to measure the power and frequency of short-duration pulses of air traffic control equipment. The power and frequency of the pulse carrier are the main parameters of pulse radar. The power frequency meter integrates the power and frequency measurement functions into a single module, which greatly reduces the volume of the system and is very conducive to the miniaturization of the system. The present invention realizes the accurate measurement of the carrier frequency of short-duration pulses through high-speed acquisition and the use of FFT and CZT combined algorithms, as well as signal processing algorithms such as interpolation correction methods. At the same time, in response to the needs of general radio frequency signal performance testing of air traffic control equipment, on the basis of frequency measurement, the power and pulse parameter tests are integrated. Through signal processing and trigger control of secondary radar, DME, VOR, etc., high-speed acquisition of single pulses of various signal formats and analysis and testing of pulse parameters are realized, and the measurement of parameters such as pulse rising edge, falling edge, pulse width, pulse spacing, top unevenness, and sequence unevenness can be flexibly completed.

[0066] Compared with existing technologies, power frequency meters have the following advantages:

[0067] 1) By combining the frequency measurement principle of a spectrum analyzer, the present invention reduces the cost of pulse carrier frequency testing compared to desktop spectrum analyzers and power meters, while achieving measurement accuracy similar to that of desktop instruments. Due to the use of a spectrum estimation algorithm, carrier frequency measurement is not limited to pulse modulation methods, thus having a wider range of applications.

[0068] 2) This invention combines the working principle of a desktop power meter to reduce the testing cost of pulse power compared to a desktop power meter, while achieving measurement accuracy similar to that of a desktop power meter. Combined with flexible triggering methods, it can flexibly track the power characteristics of a single pulse in a pulse train.

[0069] 3) The present invention adopts a method of high-speed acquisition of detection signals and statistical analysis of the acquired data, which flexibly realizes the measurement capability of pulse parameters such as pulse width, pulse spacing, rising edge, falling edge, pulse top unevenness, pulse sequence unevenness, etc., and combines the understanding of the simulation of the signal to be measured to design the corresponding trigger mode, which can flexibly observe any specified pulse waveform;

[0070] 4) The present invention combines the encoding and decoding functions of the secondary radar and can flexibly generate trigger signals according to the working mode of the secondary radar, facilitating independent analysis of any pulse power, frequency, pulse parameters, etc. of the secondary radar;

[0071] 5) The present invention adopts the PXIe bus and the form of a 3U board card, which is miniaturized and universal in structure, is more conducive to system integration, and is conducive to the control of the power frequency meter and data transmission and processing through the embedded controller.

[0072] The other parts of this embodiment are the same as those of embodiment 1 or 2, and therefore will not be described in detail.

[0073] Example 4:

[0074] This embodiment is optimized based on any one of Embodiments 1-3. The amplitude and phase consistency test card is mainly used to test parameters such as amplitude and phase consistency, isolation, and standing wave between channels of TR components, and is customized for testing requirements such as digital TR components.

[0075] like Figure 21 As shown, the amplitude and phase consistency test card uses a DDS signal source to generate a swept or fixed frequency signal, which can be selectively output to the device under test through Port 1 or Port 2. After the device responds, the signal is returned to the amplitude and phase consistency test card through Port 1 or Port 2. The amplitude and phase consistency test card uses a mixer to down-convert the transmitted or reflected signal coupled by the directional coupler into an intermediate frequency signal. The sampling circuit samples and analyzes the intermediate frequency signal to obtain the S parameters of the device under test. The local oscillator and clock circuit provides clock and local oscillator signals for the various chips in the amplitude and phase consistency test card and can also receive external local oscillator signals for the mixer. The reference clock circuit provides a highly stable reference clock for the card and can also receive an external reference clock. The control circuit controls the various chips on the card, reads the sampled data from the ADC chip, and uploads it to the embedded controller via the PCIe bus.

[0076] The standing wave test is a single-channel test. The RF signal transmitted by the DDS and the RF signal reflected by the device under test are coupled through a directional coupler and then sampled and analyzed to calculate the standing wave ratio of the device under test.

[0077] The amplitude and phase consistency test sends an RF signal of a certain frequency to the device under test through Port 1. The device under test sends the response signal back to the board through Port 2. The board couples the sent and received RF signals through a directional coupler and sends them to the sampling circuit for acquisition and analysis. The difference in amplitude and phase between the return channel and the transmit channel is thus obtained. By switching the return channels one by one, the amplitude and phase consistency of the return channels can be indirectly compared.

[0078] The isolation test sends a radio frequency signal of a certain frequency to the device under test through Port 1. The device under test sends the response signal back to the board through Port 2. The board couples the sent and received radio frequency signals through a directional coupler and sends them to the sampling circuit for collection and analysis. The difference in amplitude between the return channel and the transmit channel is obtained, and the isolation between the two channels is measured.

[0079] The main chips sampled by the amplitude and phase consistency test card include: the mixer model is ADE-11X, the AD chip model used in the sampling circuit is ADS6445, and the directional coupler model is SCBD-10-63HP+.

[0080] The rest of this embodiment is the same as any of Embodiments 1-3, so they will not be described in detail.

[0081] Example 5:

[0082] This embodiment is optimized based on any one of the embodiments 1-4. Figure 13 As shown in Figure 1, the signal exciter consists of two main components: a baseband signal processing unit and a radio frequency signal processing unit. The signal exciter design is based on software-defined radio (SDR) principles and a common hardware architecture. It enables functional performance testing of avionics equipment such as secondary radar, TACAN, DME, and VOR through embedded controller software configuration or FPGA program changes.

[0083] The present invention can also receive GPS signals through the GPS antenna to generate the required position and time information. Figure 14 As shown, the baseband signal processing unit of the present invention mainly realizes the encoding and decoding of secondary radar inquiry and response signals through FPGA, and can also receive GPS signals to generate corresponding time, position and other information. At the same time, the baseband signal processing unit also realizes information exchange with the embedded controller through the PXIe bus, thereby realizing the control of the exciter by the embedded controller.

[0084] Preferably, if Figure 14 As shown, the baseband signal processing unit is the core unit of the present invention. It needs to receive instructions from the main control system and complete functions such as encoding, parsing, and statistics of query and response signals. This module uses the high-speed PXIe bus to communicate with the single-board computer, facilitating high-speed and large-scale data information transmission. Its main functions include:

[0085] a. Interrogator interrogation coding and reply decoding, transponder interrogation decoding and reply coding, simulation and reception of ADS-B broadcast signals, and statistical analysis of signals;

[0086] b. Perform encryption and decryption algorithms for Modulo 4 and Modulo 5 query and response data through the DSP. The encrypted and decrypted data is sent to the FPGA via the EMIF bus for further processing.

[0087] c. Encoding and decoding of TACAN, DME and VOR signals;

[0088] d. Also has the function of GPS / BD receiver.

[0089] The baseband signal processing unit has multiple working modes:

[0090] ① GPS receiver mode: The MCU receives the encoded positioning information sent by GPS / BD and generates the CPR code. The FPGA reads the CPR value and uses it to send the ADS-B position message information.

[0091] ② Interrogator mode: The digital signal processing module sends interrogation signals in A and C modes (ASK modulation), S mode (DPSK modulation), mode 4 and mode 5 (MSK modulation), with a transmission frequency of 190 MHz and a transmission power of ≤0 dBm (programmable). The response decoding is completed using baseband video signals (with low-speed AD) + FPGA.

[0092] ③ Transponder mode: The digital signal processing module sends A, C (ASK modulation), S mode (ASK modulation), Mode 4, and Mode 5 (MSK modulation) response signals with a transmission frequency of 190 MHz and a transmission power ≤ 0 dBm (programmable). S-mode interrogation decoding is implemented using IF (with high-speed AD) + video (with low-speed AD) + FPGA (IF implements DPSK demodulation, and video completes frame extraction). A and C mode interrogation decoding is implemented using video + FPGA, and Mode 4 and Mode 5 interrogation decoding is implemented using IF (with high-speed AD) + FPGA + DSP.

[0093] ④ Interrogator-transponder mode: can perform interrogation and response simulation simultaneously to form an interrogation-response communication link.

[0094] ⑤ Signal simulation mode: It can simulate the query and response signals of modes such as A, C, S, Mode 4, and Mode 5.

[0095] ⑥ Signal analysis mode: It can receive inquiry and response signals in modes such as A, C, S, Mode 4, and Mode 5, decode the signals, and upload them to the embedded controller.

[0096] Preferably, if Figure 13 、 Figure 15 As shown, the radio frequency signal processing unit of the present invention mainly realizes the function of conditioning the radio frequency signal of the inquiry response, and is mainly composed of a radio frequency receiving circuit, a radio frequency transmitting circuit, a power amplifier circuit and an antenna interface circuit 4.

[0097] RF transmitting circuit: such as Figure 15 As shown, it receives a 190MHz IF modulated signal with a modulation bandwidth of ±12MHz and up-converts it to 1030MHz / 1090MHz ±0.01MHz. The IF signal is filtered and mixed with the Lo signal. The up-converted signal is then filtered and output. The main chips used are: HMC830 phase-locked loop, EAR-15M op amp, ADE-11X mixer, etc.

[0098] Power amplifier circuit: such as Figure 15As shown, it is used to amplify the 1030MHz / 1090MHz RF signal emitted by the RF transmitter circuit to the required -20dBm to +20dBm pulse power at the output port. The main chips used are: EAR-85M power amplifier, GVA-91+, etc.

[0099] RF receiving circuit: such as Figure 15 As shown, it receives 1030MHz / 1090MHz RF modulated signals with a modulation bandwidth of ±12MHz and down-converts them to a 190MHz IF signal with a receiving dynamic range of >65dB. It also features hardware detection of video signals and feeds the detected video signals into the baseband signal processing unit. The chips used include the HMC830 phase-locked loop, EAR-15M op amp, ADE-11X mixer, EAR-35M op amp, and ADL5513 detector.

[0100] Antenna interface circuit: such as Figure 15 As shown, the circulator is used to transform the signal path during RF transmission and reception, providing anti-burnout protection, impedance matching, and power supply for the antenna and feeder system. A block diagram of its operating principle is shown below. The main chip used is the WH2525X-2 circulator.

[0101] The signal exciter can simulate a secondary radar interrogator and is controlled by an embedded controller via the PXIe bus. It generates an interrogation IF signal through the baseband signal processing unit, which is up-converted to 1030MHz by the RF signal processing unit and sends interrogation signals of various modes to the product under test. At the same time, the signal exciter can receive the response signal sent back by the device under test through the RF front end. After down-conversion and detection processing, the signal is sent to the baseband signal processing unit for response decoding, and the decoding result is uploaded to the embedded controller for display and related processing.

[0102] The signal exciter can also simulate a secondary radar transponder, receiving the interrogation signal of the interrogator under test through the RF front end, and after down-conversion processing, sending the intermediate frequency and video signals to the baseband signal processing unit for interrogation decoding. According to the decoding result and the configuration of the baseband signal processing unit by the embedded controller, the corresponding response coding is performed, and the encoded intermediate frequency signal is sent to the interrogator under test after up-conversion to form an interrogation response loop.

[0103] Compared with the existing technology, the signal exciter has the following advantages:

[0104] 1) Based on FPGA technology and mature secondary radar interrogation and response encoding and decoding technology, the design complexity is greatly simplified, which is conducive to the miniaturization of the equipment;

[0105] 2) Based on the concept of software radio, on the basis of existing hardware, by burning different IP cores, it can flexibly realize the signal simulation of secondary radar, DME, VOR and other equipment;

[0106] 3) The 3U standard board design based on the PXIe bus makes the equipment miniaturized, universal, and easy to integrate into the system;

[0107] 4) Combined with signal simulation applications, it is designed with a flexible configuration interface to facilitate cooperation with embedded controller programs to achieve signal simulation in various application scenarios.

[0108] The rest of this embodiment is the same as any of Embodiments 1-4, and therefore will not be described in detail.

[0109] Example 6:

[0110] This embodiment is optimized based on any one of the embodiments 1-5. Figures 16-20 As shown, the RF host RF adapter interface is divided into two parts based on the principle of functional aggregation, using a modular and miniaturized design concept. The host adapter interface unit can be designed according to different models of the product under test, while the universal switch control module provides versatility and broad compatibility. The two are connected via an LRM connector. Simply replacing the host adapter interface can quickly meet the RF interface adaptation test requirements of different models of products under test.

[0111] Preferably, the host radio frequency adaptation interface mainly consists of two parts, the front part is the host adaptation interface unit, and the rear part is the universal switch control module, and the two are connected to each other through the module LRM connector inserted into the backplane.

[0112] Preferably, the front part of the host RF adapter interface consists of 8 host adapter interface units that correspond one-to-one to the RF interface of the product to be tested. Taking a certain type of host RF adapter interface as an example, it mainly includes the upper antenna, lower antenna, ΣL, ΣR, △L, △R, ΩL, and ΩR of the N-type head.

[0113] Preferably, the host RF adapter interface unit is divided into a high-power signal synthesis and attenuation unit primarily based on coaxial components, and a small-signal distribution and conditioning unit primarily based on chip-level components such as electronic switches. The two are cascaded via a cable. By rationally utilizing the advantages of chip components and coaxial components, the reliability of the test channel is effectively improved, and the introduction of systematic and random errors is reduced.

[0114] Preferably, the high-power signal synthesis attenuation unit is designed with coaxial devices with strong power handling capability to withstand the high-power RF signal injected by the product under test. Figure 18As shown, the multiple antenna interface signals output by the DUT are combined into one channel by a high-power combiner and then fed into a fixed attenuator for power adjustment. A coaxial switch controls the signal direction. When the signal is directed to RF_X1, it is further processed by the small-signal conditioning and distribution unit and then fed to the VN port 2 for S-parameter testing such as phase consistency. When the signal is directed to the directional coupler, two signals are output after coupling. The low-power signal RF_X2 is fed to the small-signal conditioning and distribution unit and ultimately connected to the power frequency meter test port for power and frequency performance testing. The high-power signal is conditioned through a circulator and programmable attenuator, forming an interrogation and response loop with varying attenuation levels, and ultimately connected to the exciter port for interrogation and response testing, as well as sensitivity and dynamic range testing. The Ω signal, conditioned by the small-signal conditioning and distribution unit, is fed into the RF_X3 port and can also be switched with the exciter via a coaxial switch, forming a test loop for the DUT's Ω signal.

[0115] Preferably, the small signal distribution conditioning unit: Figure 19 As shown, the signal, after pre-conditioning by the high-power signal combining and attenuating unit, is further regulated and distributed using RF chip components such as electronic switches, attenuators, and circulators. While these components have a relatively low power handling capacity, they are compact, offer good repeatability, and are easily integrated on a PCB. This reduces cable connections and improves stability. The small signal distribution and conditioning unit is connected to the high-power combining and attenuating unit via a coaxial cable.

[0116] After being pre-processed by the high-power signal synthesis and attenuation unit, the signal strength is within the tolerance range of general RF chip devices. Through the cascade design of multi-way electronic switches, the signal is distributed to the corresponding test ports according to different test requirements. Through the design of power amplifiers, programmable attenuators, and fixed attenuators, the signal strength is adjusted to the optimal test conditions of the instrument to ensure the accuracy of the test results.

[0117] Preferably, if Figure 20 As shown, the universal switch control module is the control core of the RF host RF adapter interface. It adopts a separate structural design from the host RF interface. Through the universal control interface, the interface controller can control different RF host RF adapter interfaces. The universal switch control module is mainly composed of an FPGA main control chip and peripheral circuits. It provides multiple control interfaces such as RS422 by converting interface signals. The peripheral drive circuit design can generate multiple drive control signals to control the coaxial switch, programmable attenuator, electronic switch circuit, and signal conditioning circuit inside the host adapter interface. Its control signal output port adopts a unified universal definition design to adapt to different host RF interfaces.

[0118] The RF host RF adapter interface can be used in the test system for the secondary radar interrogation transponder to complete the construction of the RF test topology of the device under test, and assist the test instrument to realize the testing of the device's transmit power, frequency, pulse parameters, receiving decoding sensitivity, receiving dynamic range, transmitting channel amplitude and phase consistency, receiving channel amplitude and phase consistency, sum and difference channel phase difference, sum and difference channel isolation, channel phase shift step, channel weighting step and other indicator parameters.

[0119] The operating principle is as follows: After the multi-channel RF signals (typically high power) output by the secondary radar interrogator (i.e., the product under test) are connected to the host adapter interface unit, they are first pre-processed by the high-power signal synthesis and attenuation unit, including power adjustment and synthesis. These signals are then processed into lower-power signals and fed into the small-signal distribution and conditioning unit. The small-signal distribution and conditioning unit then receives the drive control signals from the universal switch control module. It further synthesizes, adjusts power, and switches channels after pre-processing to ensure signal strength reaches the optimal test range for the test instrument. These signals are then fed into the universal switch control module via a board-to-board LRM connector and routed to the instrument test interface for performance testing or to form an interrogation-response loop. The universal switch control module receives external power and control bus signals through the LRM connector, receives control commands from the embedded controller, and generates response control signals (typically discrete lines) and drive signals after protocol parsing. These signals are then connected to the host adapter interface via an onboard connector. For compatibility and applicability, the switch control module provides multiple drive control signals and bus control signals, accommodating the control requirements of host adapter interfaces of varying complexity.

[0120] Compared with existing technologies, the host RF adapter interface has the following advantages:

[0121] 1) Adopting a modular design concept, the system is functionally divided into two parts: the universal interface control and the host RF interface. These parts can be installed and debugged independently without affecting each other. At the same time, the universal interface design enables the universal switch control module to adapt to different host RF interfaces, meeting the testing requirements of various models of products under test;

[0122] 2) Supports interrogation and response function testing for the product under test, and builds test loops for test items such as power, frequency, S parameters, and amplitude and phase consistency;

[0123] 3) The port has a strong power handling capability and can withstand secondary radar interrogation and response signals of ≮+70dBm. It can be directly connected to the product under test without additional signal conditioning.

[0124] 4) Based on the distinction between high-power signals and low-power signals, the host RF interface is divided into two parts. The high-power part uses an RF coaxial switch, and the low-power part uses an electronic switch. This greatly reduces the size of the host RF adapter interface and facilitates the miniaturization design of the host RF adapter interface.

[0125] 5) According to the characteristics of the measurement parameters of the signal to be tested, the channels with special requirements for amplitude and phase consistency are designed with passive components, which greatly reduces the impact on the amplitude and phase consistency test.

[0126] The rest of this embodiment is the same as any of Embodiments 1-5, so they will not be described in detail.

[0127] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiment based on the technical essence of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A flexible integrated avionics system, characterized in that: The system includes a host RF adapter interface, a PXIe backplane, an embedded controller, a signal exciter, an amplitude and phase consistency test card, a power frequency meter, and a universal control interface card. The PXIe backplane is connected to the universal control interface card, the amplitude and phase consistency test card, the power frequency meter, and the embedded controller respectively. The host RF adapter interface is connected to the device under test and the amplitude and phase consistency test card, the power frequency meter, the signal exciter, and the external RF adapter respectively. The universal control interface card is connected to the device under test via the universal control interface. The host RF adapter interface is used to build a test topology. The adaptation interface includes a host adaptation interface unit and a universal switch control module, and the universal switch control module is respectively connected to the embedded controller and the external RF adapter; the host adaptation interface unit includes a high-power signal synthesis and attenuation unit and a small signal distribution and conditioning unit, and the high-power signal synthesis and attenuation unit is connected to the end of the product to be tested, and is connected to the universal switch control module through the small signal distribution and conditioning unit. The small signal distribution and conditioning unit is provided with several test branches, and the test branches are provided with electronic switches, and are correspondingly connected to the amplitude and phase consistency test card, power frequency meter, and signal exciter.

2. A flexible integrated avionics system according to claim 1, characterized in that: The high-power signal synthesis and attenuation unit is provided with a power combiner, a fixed attenuator, a first coaxial switch, and a coupler corresponding to the product to be tested. The power combiner is used to receive and synthesize the multi-channel antenna interface signals output by the product to be tested. The first coaxial switch is respectively connected to the small signal distribution and conditioning unit and the coupler, and is used to output the RF_X1 signal to the small signal distribution and conditioning unit. The output end of the coupler is connected to the small signal distribution and conditioning unit, and is used to output the power signal RF_X2 to the small signal distribution and conditioning unit; the small signal distribution and conditioning unit is respectively provided with an RF_X1 signal test branch and an RF_X2 signal test branch, the RF_X2 signal test branch is connected to the third electronic switch, the third electronic switch is connected to the fourth electronic switch, and the fourth electronic switch is connected to the power frequency meter; the RF_X1 signal test branch is connected to the fifth electronic switch, and the fifth electronic switch is connected to the vector network port2 port for phase consistency testing.

3. The flexible integrated avionics system according to claim 2, characterized in that: The high-power signal synthesis attenuation unit also includes a first circulator, a second circulator, and a second coaxial switch, which are arranged in sequence from front to back. A fixed attenuator and a programmable attenuator are connected in parallel between the first circulator and the second circulator; the output end of the coupler is also connected to the first circulator, and the small signal distribution and conditioning unit is correspondingly provided with an RF_X3 signal test branch for outputting the Ω signal of the product to be tested. A third circulator and a fourth circulator are sequentially arranged on the RF_X3 signal test branch, and a programmable attenuator and a fixed attenuator are arranged in parallel between the third circulator and the third circulator. The fourth circulator is connected to the second electronic switch, and the second electronic switch is sequentially connected to the amplifier and the third electronic switch; the second coaxial switch is respectively connected to the RF_X3 signal test branch and the exciter.

4. A flexible integrated avionics system according to any one of claims 1 to 3, characterized in that: The small signal distribution and conditioning unit also includes an external source test branch, on which a ninth electronic switch is provided. The ninth electronic switch is connected to the fourth electronic switch and the eighth electronic switch, respectively. A first N-FET switch, a second N-FET switch, a second amplifier, and a third amplifier are sequentially provided between the eighth and ninth electronic switches.

5. The flexible integrated avionics system according to claim 1, characterized in that: The amplitude and phase consistency test card includes a port1 port, a port2 port, a transmitting module, a return module, a sampling circuit, a DDS signal source, a control circuit, a local oscillator and a clock circuit. The sampling circuit is respectively connected to the transmitting module and the return module. The transmitting module includes a first directional coupler and a second directional coupler connected in sequence from front to back, and a first mixer and a second mixer connected in sequence from front to back. The first directional coupler and the second directional coupler are respectively connected to the sampling circuit through the first mixer and the second mixer, and the second directional coupler is connected to the port1 port; the transmitting module includes a third directional coupler, a fourth directional coupler, a third mixer and a fourth mixer. The output end of the third directional coupler is connected to the fourth directional coupler, the third directional coupler and the fourth directional coupler are respectively connected to the sampling circuit through the third mixer and the fourth mixer, and the third directional coupler is connected to the port2 port. The DDS signal source is respectively connected to the first directional coupler and the fourth directional coupler, and the local oscillator and the clock circuit are respectively connected to the first mixer and the fourth mixer.

6. The flexible integrated avionics system according to claim 1, characterized in that: The signal exciter includes a baseband signal processing unit and a radio frequency signal processing unit that are interconnected. The radio frequency signal processing unit includes a radio frequency transmitting circuit, a power amplifier circuit, an antenna interface circuit, and a radio frequency receiving circuit that are connected in sequence from front to back; the radio frequency receiving circuit includes a second attenuator, a power divider, a second operational amplifier, a detector, and a frequency source, a phase-locked loop, an attenuator, a filter, a first operational amplifier, a mixer, and a filter that are connected in sequence from front to back. The second attenuator is connected to the power divider, and the power divider is respectively connected to the second operational amplifier and the detector. The second operational amplifier is connected to the mixer through a bandpass filter. The second attenuator is connected to the antenna interface circuit, the detector is connected to the baseband signal processing unit, and the mixer is connected to the baseband signal processing unit through a filter.

7. The flexible integrated avionics system according to claim 6, characterized in that: The baseband signal processing unit includes an FPGA and a microcontroller unit MCU connected to the FPGA, a digital signal processing module, a low-speed ADC, a high-speed ADC, and a digital-to-analog converter. The FPGA is connected to the embedded controller via a PXIe bus, the FPGA is connected to the radio frequency transmission circuit via a digital-to-analog converter, the detector is connected to the low-speed ADC, and the mixer is connected to the high-speed ADC via a filter; the FPGA is connected to the GPS / BD receiver via the microcontroller unit MCU, and the GPS / BD receiver is connected to the GPS antenna.

8. The flexible integrated avionics system according to claim 1, characterized in that: The power frequency meter includes a high-speed acquisition circuit, a trigger circuit, and a clock module, a radio frequency input and conditioning module, a detection circuit, a comparison circuit, and a control circuit connected in sequence from front to back. The control circuit is connected to the embedded controller through a PXIe bus; the high-speed acquisition circuit is respectively connected to the clock module, the radio frequency input and conditioning module, the detection circuit, and the control circuit, and the control circuit is connected to the trigger circuit; the clock module is used to provide a clock signal for the high-speed acquisition circuit, and the high-speed acquisition circuit is used to collect the detection signal and the intermediate frequency signal; the radio frequency input and conditioning module includes a protection diode, a broadband SPDT switch, an attenuator, a radio frequency switch, and a distributor connected in sequence from front to back, and the broadband SPDT switch is connected to the radio frequency switch; the output end of the distributor is respectively connected to the frequency conversion module and the detection circuit, the frequency conversion module is connected to the high-speed acquisition circuit, and the frequency conversion module is used to down-convert the signal to be measured into an intermediate frequency signal.

9. The flexible integrated avionics system according to claim 8, characterized in that: The frequency conversion module includes a programmable attenuator, a first SPDT switch, a first power amplifier, a second SPDT switch, a high-pass filter, a mixer, a low-pass filter and a second power amplifier, which are connected in sequence from front to back.

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