A chip power-on detection circuit, method and FPGA chip

Abstract

The present invention provides a chip power-on detection circuit, comprising: a core power module, a power-on detection module, a first I / O power module, and a second I / O power module. The power-on detection module includes a first circuit node, a second circuit node, and a first switch unit. The first switch unit is configured to synchronize the logic levels of the first and second circuit nodes, and is opposite to the output logic level of the power-on detection module. This circuit provides a solution for synchronously detecting the power-on status of the core power supply and I / O power supplies, preventing chip startup from occurring when either power supply falls below its normal operating voltage, thereby ensuring chip operational stability and reliability. The present invention also provides a chip power-on detection method and FPGA chip, which have corresponding advantages.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to an on-chip power-on detection circuit and a corresponding on-chip power-on detection method, and an FPGA chip. Background Art

[0002] In integrated circuit systems, the power-on process can create uncertain states. Existing technologies incorporate power-on reset circuits to address this problem. Chips typically have multiple power supplies, and different power supplies often have different power-up sequences. For example, FPGAs typically require two voltages to operate: a core power supply voltage and an IO power supply voltage (input and output voltage). Each voltage is provided by a separate power pin. The core power supply voltage, also known as the chip's core power supply voltage (also referred to as VCCINT in this article), is used to power the logic gates and flip-flops within the FPGA. This voltage has become increasingly lower with FPGA development. The core power supply voltage is generally fixed and determined by the FPGA mode. The IO power supply voltage (also referred to as VCCIO in this article) is used to power the FPGA's input and output modules (IO pins). This voltage must match the voltage of other devices connected to the FPGA. When the chip's core and IO power supplies are properly powered on, a signal is generated. Upon receiving this signal, the chip's internal logic begins operation. Because different power supplies have different power-on sequences, for the same chip, when the core power supply and IO power supply are unstable, the IO status will be triggered incorrectly, causing the chip's external pins to receive and send data incorrectly, and the FPGA chip will not work properly.

[0003] Existing power-on reset circuit designs and corresponding power-on detection methods generally implement power-on detection and reset for a single power supply, lacking a solution for simultaneous detection of both the core power supply voltage and the external I / O power supply voltage. At the beginning of power-on, when the external I / O power supply voltage is low and the core power supply voltage does not meet requirements, a lack of monitoring measures prevents false I / O state triggering, even with a reset circuit. Therefore, to prevent issues such as uncertain chip input / output interfaces and internal logic states caused by varying power-on timings between different power supplies, a chip power-on detection circuit and corresponding chip power-on detection method are urgently needed to further improve chip reliability in practical applications. Summary of the Invention

[0004] The present invention aims to address all or part of the problems of the above-mentioned prior art. On one hand, the present invention provides a chip power-on detection circuit capable of detecting whether the chip core power supply voltage (VCCINT) and the chip IO power supply voltage (VCCIO) are synchronously and normally powered on. On the other hand, the present invention provides a chip power-on detection method that synchronously detects the chip core power supply voltage (VCCINT) and the chip IO power supply voltage (VCCIO), and controls the output logic level based on the detection results to output a normal power-on signal to the system. The present invention also provides an FPGA chip incorporating the chip power-on detection circuit of the present invention.

[0005] In one aspect, the present invention provides a chip power-on detection circuit, comprising: a core power supply module, a power-on detection module, a first I / O power supply module, and a second I / O power supply module; the power-on detection module comprises a first circuit node, a second circuit node, and a first switch unit; the core power supply module is used to power on the core power supply to obtain a supply voltage, and its output end is connected to the first circuit node via a second switch unit; the first I / O power supply module and the second I / O power supply module are used to power on the I / O power supplies to obtain a supply voltage, wherein the output end of the first I / O power supply module is connected to the first circuit node, and the output end of the second I / O power supply module is connected to the second circuit node; the first switch unit is used to control the synchronization of the logic levels of the first and second circuit nodes (to be simultaneously high or simultaneously low), and to control the logic level to be opposite to the output logic level of the power-on detection module; (when the logic levels of the first and second circuit nodes are high, the output logic level of the power-on detection module is low, and vice versa). The output logic level is used to control whether the chip starts operating. The power-on detection module's OUT signal will only become high when both VCCINT and VCCIO are powered on normally and reach the chip's required power supply voltage. Otherwise, the OUT signal remains low. When the system receives this high-level signal, the power-on state is stable and the chip can operate normally.

[0006] The core power module includes a first configuration resistor; the second switch unit includes a first gating switch; a first end of the first configuration resistor is connected to a power-on pin of the core power module, and a second end is connected to an input end of the first gating switch to form a third circuit node; the first gating switch is grounded and an output end is connected to the first circuit node; the third circuit node is connected to a power line node of the first IO power module.

[0007] The first selection switch is a first NMOS transistor; the gate of the first NMOS transistor is connected to the third circuit node, the source is grounded, and the drain is connected to the first circuit node.

[0008] The first IO power supply module includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor; the gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are respectively connected to the power line node; the drain of the first PMOS transistor is connected to the power-on pin of the first IO power supply module, and the source is connected to the drain of the second PMOS transistor; the source of the second PMOS transistor is connected to the drain of the third PMOS transistor; and the source of the third PMOS transistor is connected to the first circuit node.

[0009] The first switch unit includes a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth circuit node, a fifth circuit node and a voltage line node; the gate of the second NMOS transistor is connected to the power line node, the source is grounded, and the drain and the source of the fourth PMOS transistor are connected to the fifth circuit node; the gate of the fourth PMOS transistor is connected to the power line node, and the drain is connected to the source of the fifth PMOS transistor; the drain of the fifth PMOS transistor is connected to the second circuit node, and the gate is connected to the fourth circuit node; the source of the third NMOS transistor is grounded, the gate and the gate of the seventh PMOS transistor are connected to the first circuit node, and the drain and the source of the seventh PMOS transistor are connected to the fourth circuit node; the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor are connected to the voltage line node; the gate of the sixth PMOS transistor is connected to the fifth circuit node, and the drain is connected to the second circuit node.

[0010] The first switch unit also includes a fourth NMOS transistor, a fifth NMOS transistor, an eighth PMOS transistor and a ninth PMOS transistor; the source of the fourth NMOS transistor is grounded, and the gate and the gate of the eighth PMOS transistor are connected to the fourth circuit node; the drain of the eighth PMOS transistor is connected to the voltage line node; the drain of the fourth NMOS transistor, the source of the eighth PMOS transistor, the gate of the fifth NMOS transistor, and the gate of the ninth PMOS transistor are connected to each other; the source of the fourth NMOS transistor is grounded, and the drain and the source of the ninth PMOS transistor are connected to the output signal pin of the power-on detection module; the drain of the ninth PMOS transistor is connected to the voltage line node.

[0011] The second IO power supply module includes a sixth NMOS transistor and a tenth PMOS transistor; the source of the sixth NMOS transistor is grounded, and the drain is connected to the second circuit node together with the source of the tenth PMOS transistor; the drain of the tenth PMOS transistor is connected to the power-on pin of the second IO power supply module; and the gate of the sixth NMOS transistor and the gate of the tenth PMOS transistor are connected together to form a sixth circuit node.

[0012] The chip power-on detection circuit also includes an ESD protection module for preventing voltage transients caused by electrostatic discharge. The ESD protection module is connected to the sixth circuit node, and when the IO power supply is powered on, the logic level of the sixth circuit node is low. The inclusion of the ESD protection module in the chip power-on detection circuit further prevents circuit damage or instability caused by voltage transients due to electrostatic discharge (ESD), thereby ensuring chip reliability.

[0013] The ESD protection module includes a second configuration resistor, a capacitor unit, a seventh NMOS transistor, an eighth NMOS transistor and an eleventh PMOS transistor; the first end of the second configuration resistor, the drain of the eleventh PMOS transistor and the drain of the eighth NMOS transistor are commonly connected to the input end of the IO power supply voltage; one end of the capacitor unit is grounded, and the other end is commonly connected with the second end of the second configuration resistor to form a seventh circuit node; the gate of the seventh NMOS transistor and the gate of the eleventh PMOS transistor are commonly connected to the seventh circuit node; the source of the seventh NMOS transistor is grounded, and the drain and the source of the eleventh PMOS transistor are commonly connected to the sixth circuit node; the source of the eighth NMOS transistor is grounded, and the gate is connected to the sixth circuit node.

[0014] Another aspect of the present invention provides a chip power-on detection method, implemented based on the chip power-on detection circuit of the present invention, comprising: presetting a first threshold for the core power supply voltage and a second threshold for the IO power supply voltage; synchronously detecting the core power supply voltage and the IO power supply voltage; obtaining the current core power supply voltage and the current IO power supply voltage, and setting an output logic level to a high level only when the current core power supply voltage reaches the first threshold and the current IO power supply voltage reaches the second threshold; and controlling the chip to start operating when the output logic level is high. At the beginning of power-on, if the external IO power supply voltage is low and does not reach the second threshold, or if the core power supply voltage does not reach the first threshold required for normal operation, the output logic level is detected to be a low level. Only when both requirements are met does the output logic level become a high level, indicating that the system has powered on normally. The chip can start normally only when the output logic level is high, thereby preventing the system from operating when the internal voltage is not properly established, which may cause internal logic state disturbances in the chip.

[0015] The process of setting the output logic level to a high level includes: obtaining that the current IO power supply voltage reaches a second threshold value, and when the current core power supply voltage does not reach the first threshold value, the logic level of the first circuit node is a high level; the third NMOS transistor is turned on, the logic level of the fourth circuit node is a low level, and the fifth PMOS transistor is turned on; when there is no power on the power line node, the fourth PMOS transistor is turned on, and the logic level of the fifth circuit node is a high level; the sixth PMOS transistor is turned off, there is no power on the voltage line node, and the output logic level is a low level; when obtaining that the current core power supply voltage reaches the first threshold value, the logic level of the power line node is set to a high level, the second NMOS transistor is turned on, and the logic level of the fifth circuit node is pulled to a low level; the sixth PMOS transistor is turned on, and the voltage line node obtains the operating voltage; the first NMOS transistor is turned on, the logic level on the first circuit node is pulled to a low level, the logic level of the fourth circuit node is set to a high level, and the output logic level is set to a high level.

[0016] The present invention also provides an FPGA chip, comprising the chip power-on detection circuit of the present invention; when the output logic level of the chip power-on detection circuit is high, the operation is started.

[0017] Compared with the prior art, the present invention has the following main beneficial effects:

[0018] 1. A chip power-on detection circuit of the present invention provides a solution for synchronously detecting the power-on status of the core power supply and the IO power supply. It can avoid triggering chip operation when either the core power supply or the IO power supply does not reach the normal operating voltage, ensuring the controllable logic state of the chip, and facilitating further optimization of the stability and reliability of chip operation.

[0019] 2. The chip power-on detection method of the present invention synchronously detects whether the current core power supply voltage and IO power supply voltage have reached the voltage values ​​required for normal operation. Only when both meet the normal operation requirements at the same time, the output logic level is set to a high level. The high and low output logic levels are used to control whether the chip starts working. This effectively prevents the system from running when the internal voltage is not correctly established, causing uncontrollable IO state triggering and logic disorder, thereby ensuring the reliability of chip operation.

[0020] 3. The FPGA chip of the present invention includes the chip power-on detection circuit of the present invention, which has high working stability and reliability, further optimizes the performance of the FPGA chip, and is conducive to the in-depth application of the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1( a ) and FIG1 ( b ) are schematic diagrams of a power-on timing sequence of an FPGA chip according to an embodiment of the present invention.

[0022] Figure 2 Schematic diagram of an on-chip power-on detection circuit according to an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of an ESD protection module according to an embodiment of the present invention.

[0024] Figure 4 Schematic diagram of an on-chip electrical detection method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following is a clear and complete description of the technical solutions in the specific embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0026] To better understand the present invention without limiting it in any way, Figures 1(a) and 1(b) illustrate the power-on sequence of an FPGA chip. In this embodiment, the core power supply voltage is denoted as VCCINT, the IO (input / output) power supply voltage is denoted as VCCIO, and the output signal of the chip power-on detection circuit is denoted as OUT. The core and IO power supplies may have different power-on sequences. As shown in Figures 1(a) and 1(b), the core power supply may power up before the IO power supply, meaning that VCCINT reaches the normal operating voltage before VCCIO. Alternatively, VCCIO may reach the normal operating voltage, but VCCINT may lag behind and not yet reach the normal operating voltage. In both cases, the logic level of the output signal OUT is low. The logic level of the output signal OUT only becomes high after both VCCINT and VCCIO reach their respective normal operating voltages.

[0027] An embodiment of the present invention provides an FPGA chip including a chip power-on detection circuit. In addition to detecting the power-on of the external IO power supply voltage VCCIO, the exemplary chip power-on detection circuit can also be used to monitor the core power supply voltage VCCINT. Its output validity uses OUT=1 and a high-level signal as a check for successful power-on. The chip power-on detection circuit is suitable for power monitoring of multi-power systems or controllable integrated modules, ensuring the power-on testability of the system, and can be used to implement comprehensive power-on detection. In the exemplary FPGA chip, operation is started when the output logic level of the chip power-on detection circuit is high.

[0028] like Figure 2As shown, the chip power-on detection circuit provided in this embodiment includes a core power module 1, a first IO power module 2, a power-on detection module 3, and a second IO power module 4. The power-on detection module 3 includes a first circuit node NETB, a second circuit node NETD, and a first switch unit. The core power module 1 is used to power up the core power supply to obtain a supply voltage VCCINT. Its output is connected to the first circuit node NTEB via a second switch unit 5. The exemplary second switch unit 5 includes a first selection switch, which is a field-effect transistor, namely a first NMOS transistor NM0. In some embodiments, the first selection switch can be configured according to actual application requirements or implemented using multiple transistors, without limiting the specific embodiment.

[0029] The exemplary first IO power module 2 and second IO power module 4 are both used to power up the IO power supply to obtain the supply voltage VCCIO, wherein the output end of the first IO power module 2 is connected to the first circuit node NETB, and the output end of the second IO power module 4 is connected to the second circuit node NETD. Figure 2 The example has only one second IO power supply module, but in some embodiments, according to the specific design of the FPGA chip IO power supply pin, there may be more than one second IO power supply module, which is not limited.

[0030] The exemplary first switch unit is used to control the logic level synchronization of the first circuit node NETB and the second circuit node NETD, and is opposite to the output logic level of the power-on detection module 3. The output logic level of the output signal OUT is used to control whether the FPGA chip starts working.

[0031] Figure 2 In the example, the core power module 1 includes a first configuration resistor R1. The core power module 1 can be specifically designed based on actual application requirements and may also include other electrical components or more configuration resistors, without limitation herein. In the example, the first configuration resistor R1 can be an active resistor, which is more conducive to saving chip area and improving area utilization compared to using passive components.

[0032] The first end of the exemplary first configuration resistor R1 is connected to the power-on pin of core power module 1 to obtain VCCINT. The second end and the gate of the first NMOS transistor NM0 are connected to a third circuit node NETA. The source of the first NMOS transistor NM0 is grounded, and the drain is connected to the first circuit node NETB. The third circuit node NETA is connected to the power line node POW of the first IO power module 2.

[0033] Figure 2 In the exemplary case, the first IO power supply module 2 includes a first PMOS transistor MP0 , a second PMOS transistor MP1 , and a third PMOS transistor MP2 .

[0034] The gates of the first PMOS transistor MP0, the second PMOS transistor MP1, and the third PMOS transistor MP2 are each connected to the power line node POW. The drain of the first PMOS transistor MP0 is connected to the power-on pin of the first IO power module 2 to obtain VCCIO, and the source is connected to the drain of the second PMOS transistor MP1. The source of the second PMOS transistor MP1 is connected to the drain of the third PMOS transistor MP2. The source of the third PMOS transistor MP2 and the drain of the first PMOS transistor MP0 are commonly connected to the first circuit node NETB. In some embodiments, the first IO power module 2 may have other designs tailored to specific application requirements, and the inclusion of other electrical components is not limiting.

[0035] Figure 2 In the illustrated embodiment, the first switch unit includes a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, a fourth circuit node NETC, a fifth circuit node NETF, and a voltage line node VPW. The gate of the second NMOS transistor NM1 is connected to the power line node POW, the source is grounded, and the drain is connected to the fifth circuit node NETF with the source of the fourth PMOS transistor MP3. The gate of the fourth PMOS transistor MP3 is connected to the power line node POW, and the drain is connected to the source of the fifth PMOS transistor MP4. The drain of the fifth PMOS transistor MP4 is connected to the second circuit node NETD, and the gate is connected to the fourth circuit node NETC. The source of the third NMOS transistor MN2 is grounded, the gate is connected to the first circuit node NETB with the gate of the seventh PMOS transistor MP6, and the drain is connected to the fourth circuit node NETC with the source of the seventh PMOS transistor MP6. The source of the sixth PMOS transistor MP5 is connected to the drain of the seventh PMOS transistor MP6 with the voltage line node VPW. The sixth PMOS transistor MP5 has a gate connected to the fifth circuit node NETF, and a drain connected to the second circuit node NETD.

[0036] For some good examples, see Figure 2The first switch unit of the example further includes a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, an eighth PMOS transistor MP7, and a ninth PMOS transistor MP8. The source of the fourth NMOS transistor MN3 is grounded, and its gate is connected to the fourth circuit node NETC together with the gate of the eighth PMOS transistor MP7. The drain of the eighth PMOS transistor MP7 is connected to the voltage line node VPW. The drain of the fourth NMOS transistor MN3, the source of the eighth PMOS transistor MP8, the gate of the fifth NMOS transistor MN4, and the gate of the ninth PMOS transistor MP8 are connected to each other. The source of the fourth NMOS transistor MN3 is grounded, and its drain is connected to the output pin of the output signal OUT of the power-on detection module 3 together with the source of the ninth PMOS transistor MP8. The drain of the ninth PMOS transistor MP8 is connected to the voltage line node VPW.

[0037] Figure 2 In the illustrated embodiment, only one second IO power supply module 4 is provided, comprising a sixth NMOS transistor MN5 and a tenth PMOS transistor MP9. The source of the sixth NMOS transistor MN5 is grounded, and its drain is connected to a second circuit node NETD, along with the source of the tenth PMOS transistor MP9. The drain of the tenth PMOS transistor MP9 is connected to a power-on pin of the second IO power supply module 4 to receive the IO power supply voltage VCCIO. The gates of the sixth NMOS transistor MN5 and the tenth PMOS transistor MP9 are connected to form a sixth circuit node NETE.

[0038] In some preferred embodiments, the chip power-on detection circuit may further include an ESD protection module 6 for preventing voltage transients caused by electrostatic discharge. The ESD protection module 6 is connected to the sixth circuit node NETE. The circuit diagram of the ESD protection module 6 is such that when the IO power supply is properly powered on, the logic level of the sixth circuit node NETE is low.

[0039] In a specific example, Figure 3 As shown, the ESD protection module 6 includes a second configuration resistor R2, a capacitor unit, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, and an eleventh PMOS transistor MP10. The capacitor unit is implemented as a capacitor C1. In some embodiments, the capacitor unit may have more than one capacitor, which is not limited here.

[0040] The first end of the second configuration resistor R2, the drain of the eleventh PMOS transistor MP10, and the drain of the eighth NMOS transistor MN6 are connected to the input terminal of the IO power supply voltage VCCIO. One end of the capacitor C1 is grounded, and the other end is connected to the second end of the second configuration resistor R2 to form the seventh circuit node NETG. The gate of the seventh NMOS transistor MN6 and the gate of the eleventh PMOS transistor MP10 are connected to the seventh circuit node NETG. The source of the seventh NMOS transistor MN6 is grounded, and its drain is connected to the source of the eleventh PMOS transistor MP10 to the sixth circuit node NETE. The source of the eighth NMOS transistor MN7 is grounded, and its gate is connected to the sixth circuit node NETE. In other embodiments, the ESD protection module 6 can also have other designs depending on the specific chip circuit, and the specific situation is not limited here. The power-on detection circuit including the ESD protection module 6 can prevent transient voltage instability caused by electrostatic discharge, and cooperate with the power-on detection module 3 to further improve the reliability of chip operation.

[0041] Combine Figure 3 An example of an on-chip power-on detection method implemented by the on-chip power-on detection circuit of this embodiment is given. The on-chip power-on detection method provided in this embodiment is as follows: Figure 4 As shown, the system includes: presetting a first threshold for the core power supply voltage VCCINT and a second threshold for the IO power supply voltage VCCIO; synchronously detecting the core power supply voltage and the IO power supply voltage: obtaining the current core power supply voltage and the current IO power supply voltage, and setting the output logic level to a high level only when the current core power supply voltage reaches the first threshold and the current IO power supply voltage reaches the second threshold; and controlling the chip to start operating when the output logic level is high. The first and second thresholds can be set based on the operating voltage values ​​required to meet the normal operation of the chip in actual applications, and are not limited to these values.

[0042] Combine Figure 2The exemplary process of setting the output logic level to a high level includes: when the IO power supply voltage VCCIO reaches the second threshold and the core power supply voltage VCCINT does not reach the first threshold, the logic level of the first circuit node NETB is high; the third NMOS transistor MN2 is turned on, the logic level of the fourth circuit node NETC is low, and the fifth PMOS transistor MP4 is turned on; when there is no power on the power line node POW, the fourth PMOS transistor MP3 is turned on, and the logic level of the fifth circuit node NETF is high; the sixth PMOS transistor MP5 is turned off, there is no power on the voltage line node VPW, and the output logic level is low, that is, OUT = 0. When the core power supply voltage VCCIO reaches the first threshold, the logic level of the power line node POW is set to a high level, the second NMOS transistor MN1 is turned on, and the logic level of the fifth circuit node NETF is pulled to a low level; the sixth PMOS transistor MP5 is turned on, and the voltage line node VPW receives the operating voltage VDDIO. The first NMOS transistor MN0 is turned on, pulling the logic level on the first circuit node NETB to a low level. The logic level on the fourth circuit node NETC is set to a high level, and the output logic level is set to a high level, that is, the output signal OUT = 1. When OUT = 1, it indicates that the system has completed power-up and can start normal operation. The chip receives a high level output signal and starts operation. This significantly improves the reliability and operational stability of the FPGA chip.

[0043] When the core power supply voltage VCCINT is zero or has not yet reached a specified level (e.g., a first threshold), the output signal OUT at the output terminal is low. When the external IO power supply voltage VCCIO does not reach a specified level (e.g., below a second threshold), OUT is also low. In this embodiment of the chip power-on detection method, the output signal OUT only goes high when both the core and IO power supplies are powered on properly and both the core power supply voltage VCCINT and the IO power supply voltage VCCIO meet the chip's required voltages. Otherwise, the output signal OUT remains low. The chip's startup is controlled based on the logic level of the output signal OUT.

[0044] The present invention uses some common English nouns or letters for the sake of clarity, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

Claims

1. A chip power-on detection circuit, characterized in that: include: Core power module, power-on detection module, first IO power module and second IO power module; The power-on detection module includes a first circuit node, a second circuit node and a first switch unit; The core power supply module is used to power on the core power supply to obtain the supply voltage, and the output end of the core power supply module is connected to the first circuit node through the second switch unit; The first IO power supply module and the second IO power supply module are used to power up the IO power supply to obtain a supply voltage, wherein the output end of the first IO power supply module is connected to the first circuit node, and the output end of the second IO power supply module is connected to the second circuit node; The first switch unit is used to control the synchronization of the logic levels of the first circuit node and the second circuit node, and is opposite to the output logic level of the power-on detection module; wherein the first switch unit includes a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth circuit node, a fifth circuit node and a voltage line node; the gate of the second NMOS transistor is connected to the power line node, the source is grounded, and the drain and the source of the fourth PMOS transistor are commonly connected to the fifth circuit node; the gate of the fourth PMOS transistor is connected to the power line node, and the drain is connected to the source of the fifth PMOS transistor; the drain of the fifth PMOS transistor is connected to the second circuit node, and the gate is connected to the fourth circuit node; the source of the third NMOS transistor is grounded, the gate and the gate of the seventh PMOS transistor are commonly connected to the first circuit node, and the drain and the source of the seventh PMOS transistor are commonly connected to the fourth circuit node; the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor are commonly connected to the voltage line node; the gate of the sixth PMOS transistor is connected to the fifth circuit node, and the drain is connected to the second circuit node; The output logic level is used to control whether the chip starts working.

2. The on-chip power-on detection circuit according to claim 1, wherein: The core power supply module includes a first configuration resistor; the second switch unit includes a first gate switch; A first end of the first configuration resistor is connected to the power-on pin of the core power module, and a second end is connected to the input end of the first gating switch to form a third circuit node; The first gating switch is grounded and has an output terminal connected to the first circuit node; The third circuit node is connected to a power line node of the first IO power module.

3. The on-chip power-on detection circuit according to claim 2, wherein: The first selection switch is a first NMOS transistor; the gate of the first NMOS transistor is connected to the third circuit node, the source is grounded, and the drain is connected to the first circuit node.

4. The on-chip power-on detection circuit according to claim 2, wherein: The first IO power supply module includes a first PMOS transistor, a second PMOS transistor and a third PMOS transistor; The gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are respectively connected to the power line node; The drain of the first PMOS transistor is connected to the power-on pin of the first IO power module, and the source is connected to the drain of the second PMOS transistor; The source of the second PMOS transistor is connected to the drain of the third PMOS transistor; A source of the third PMOS transistor is connected to the first circuit node.

5. The on-chip power-on detection circuit according to claim 1, wherein: The first switch unit further includes a fourth NMOS transistor, a fifth NMOS transistor, an eighth PMOS transistor and a ninth PMOS transistor; The source of the fourth NMOS transistor is grounded, and the gate thereof and the gate of the eighth PMOS transistor are connected to the fourth circuit node; The drain of the eighth PMOS transistor is connected to the voltage line node; The drain of the fourth NMOS transistor, the source of the eighth PMOS transistor, the gate of the fifth NMOS transistor, and the gate of the ninth PMOS transistor are connected in common; The source of the fourth NMOS transistor is grounded, and the drain and the source of the ninth PMOS transistor are connected to the output signal pin of the power-on detection module; A drain of the ninth PMOS transistor is connected to the voltage line node.

6. The on-chip power-on detection circuit according to claim 1, wherein: The second IO power supply module includes a sixth NMOS transistor and a tenth PMOS transistor; The source of the sixth NMOS transistor is grounded, and the drain thereof and the source of the tenth PMOS transistor are commonly connected to the second circuit node; The drain of the tenth PMOS transistor is connected to the power-on pin of the second IO power module; The gate of the sixth NMOS transistor and the gate of the tenth PMOS transistor are connected together to form a sixth circuit node.

7. The on-chip power-on detection circuit according to claim 6, wherein: It also includes an ESD protection module for preventing voltage transients caused by electrostatic discharge; the ESD protection module is connected to the sixth circuit node, and when the IO power supply is powered on, the logic level of the sixth circuit node is low.

8. The on-chip power-on detection circuit according to claim 7, wherein: The ESD protection module includes a second configuration resistor, a capacitor unit, a seventh NMOS transistor, an eighth NMOS transistor and an eleventh PMOS transistor; The first end of the second configuration resistor, the drain of the eleventh PMOS transistor, and the drain of the eighth NMOS transistor are commonly connected to the input end of the IO power supply voltage; One end of the capacitor unit is grounded, and the other end is connected to the second end of the second configuration resistor to form a seventh circuit node; The gate of the seventh NMOS transistor and the gate of the eleventh PMOS transistor are connected to the seventh circuit node; The source of the seventh NMOS transistor is grounded, and the drain thereof and the source of the eleventh PMOS transistor are commonly connected to the sixth circuit node; The source of the eighth NMOS transistor is grounded, and the gate is connected to the sixth circuit node.

9. A chip electrical detection method, characterized in that: The on-chip power-on detection circuit according to any one of claims 1 to 8 is implemented, comprising: presetting a first threshold value of a core power supply voltage and a second threshold value of an IO power supply voltage; Synchronous detection of core power supply voltage and IO power supply voltage: The current core power supply voltage and the current IO power supply voltage are obtained, and the output logic level is set to a high level when and only when the current core power supply voltage reaches the first threshold and the current IO power supply voltage reaches the second threshold; wherein the process of setting the output logic level to a high level includes: obtaining that the current IO power supply voltage reaches the second threshold and the current core power supply voltage does not reach the first threshold, the logic level of the first circuit node is a high level; the third NMOS transistor is turned on, the logic level of the fourth circuit node is a low level, and the fifth PMOS transistor is turned on; there is no power on the power line node, the fourth PMOS transistor is turned on, and the The logic level of the fifth circuit node is high; the sixth PMOS transistor is turned off, there is no power on the voltage line node, and the output logic level is low; when the current core power supply voltage reaches the first threshold, the logic level of the power line node is set to a high level, the second NMOS transistor is turned on, and the logic level of the fifth circuit node is pulled to a low level; the sixth PMOS transistor is turned on, and the voltage line node obtains the operating voltage; the first NMOS transistor is turned on, the logic level on the first circuit node is pulled to a low level, the logic level of the fourth circuit node is set to a high level, and the output logic level is set to a high level; When the output logic level is high, the control chip starts working.

10. An FPGA chip, characterized in that: The on-chip power-on detection circuit comprises the on-chip power-on detection circuit according to any one of claims 1 to 8; the on-chip power-on detection circuit starts working when the output logic level is high.

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