Startup circuit and chip for bandgap reference circuit

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a startup circuit and chip for a bandgap reference circuit. The startup circuit includes: a feedback circuit configured to: receive the output voltage of the bandgap reference circuit as a first control signal; receive a second control signal; and, when the second control signal is pulled high and maintained at a first level, output a third level in response to the first control signal being higher than 0 and lower than the second level; and a control circuit configured to control the startup voltage for the bandgap reference circuit to decrease in response to the second control signal being pulled high and maintained at the first level and the third level output by the feedback circuit. The first level is equal to or higher than a first turn-on voltage of the feedback circuit and the control circuit, the second level is lower than a target output voltage of the bandgap reference circuit, and the third level is higher than or equal to the second turn-on voltage of the control circuit. The present invention can significantly improve the reliability of the startup process of the bandgap reference circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a startup circuit and a chip for a bandgap reference circuit. Background Art

[0002] With the rapid development of today's electronics industry, reference sources, as fundamental circuit elements, are becoming increasingly important. Currently, the three most commonly used reference source circuits are buried Zener references, XFET references, and bandgap references. Bandgap references are the most widely used and popular. With the advancement of power management chips, bandgap references offer the advantage of being virtually independent of temperature, supply voltage, and process technology, and have become widely used in various power management chips. Bandgap reference circuits are extremely important circuits in power management chips, and their performance determines the quality of the chip. Bandgap reference circuits generally consist of a bandgap voltage generator, an operational amplifier, and a bias circuit.

[0003] The startup circuit is used to start the bandgap reference circuit. Its function is to ensure that the reference circuit exits the zero-current state upon power-up. Once the reference circuit is operating normally, the startup circuit automatically shuts down. Therefore, the startup circuit is directly related to whether the bandgap reference circuit can start up properly and operate stably. However, existing startup circuits for bandgap reference circuits have problems such as reliability and high power consumption. Therefore, ensuring reliable startup and reducing the power consumption of the startup circuit are urgent issues that need to be addressed. Summary of the Invention

[0004] The purpose of the present invention is to provide a startup circuit and chip for a bandgap reference circuit, which can control the startup voltage to be reduced based on the output voltage of the bandgap reference circuit after providing a startup voltage to the bandgap reference circuit, thereby greatly improving the reliability of the startup process of the bandgap reference circuit.

[0005] To achieve the above-mentioned objectives, the present invention provides, in a first aspect, a startup circuit for a bandgap reference circuit, the startup circuit comprising: a feedback circuit for performing the following operations: receiving the output voltage of the bandgap reference circuit as a first control signal; receiving a second control signal; and outputting a third level in response to the first control signal being higher than 0 and lower than the second level when the second control signal is pulled high and maintained at the first level; and a control circuit for controlling the startup voltage for the bandgap reference circuit to decrease in response to the second control signal being pulled high and maintained at the first level and the third level output by the feedback circuit, wherein the first level is equal to or higher than a first turn-on voltage of the feedback circuit and the control circuit, the second level is lower than a target output voltage of the bandgap reference circuit, and the third level is higher than or equal to the second turn-on voltage of the control circuit.

[0006] Preferably, the feedback circuit is further configured to, in response to the first control signal being 0, output the third level when the second control signal is maintained at the fourth level, wherein the fourth level is lower than the first turn-on voltage of the feedback circuit and the control circuit. Accordingly, the control circuit is further configured to, in response to the second control signal being maintained at the fourth level and the third level output by the feedback circuit, control the output of the start-up voltage.

[0007] Preferably, the feedback circuit includes: a first inverter, an input terminal of the first inverter being connected to the first control signal, and a turn-on level of the first inverter being equal to the second level; a first N-type MOS transistor, a gate terminal of the first N-type MOS transistor being connected to the output terminal of the first inverter; a second inverter, an input terminal of the second inverter being connected to the drain terminal of the first N-type MOS transistor, and a turn-on level of the second inverter being equal to the voltage of the drain power supply of the first N-type MOS transistor; and a first P-type MOS transistor, a gate terminal of the first P-type MOS transistor being connected to the second control signal, and a turn-on voltage of the first P-type MOS transistor being equal to the first turn-on voltage of the feedback circuit.

[0008] Preferably, the feedback circuit further includes: a current source, arranged between a connection point where the input terminal of the second inverter is connected to the drain of the first N-type MOS transistor and the drain power supply; and a capacitor, one plate of the capacitor being connected to the drain of the first N-type MOS transistor and the current source, and the other plate of the capacitor being connected to the source of the first N-type MOS transistor.

[0009] Preferably, the feedback circuit further includes: a second P-type MOS transistor, wherein the source of the second P-type MOS transistor is connected to the source of the first P-type MOS transistor, and the gate of the second P-type MOS transistor is connected to the output end of the second inverter; and a third P-type MOS transistor, wherein the gate of the third P-type MOS transistor is connected to the drain of the first P-type MOS transistor, the drain of the third P-type MOS transistor is connected to the input end of the second inverter, and the source of the third P-type MOS transistor is connected to the drain of the second P-type MOS transistor.

[0010] Preferably, the control circuit includes: a fourth P-type MOS transistor, wherein the gate of the fourth P-type MOS transistor is connected to the second control signal, the source of the fourth P-type MOS transistor is connected to the source of the first P-type MOS transistor, and the turn-on voltage of the fourth P-type MOS transistor is equal to the first turn-on voltage of the control circuit; a second N-type MOS transistor, wherein the gate of the second N-type MOS transistor is connected to the second control signal, the drain of the second N-type MOS transistor is connected to the drain of the fourth P-type MOS transistor, and the connection point is used to provide a startup voltage for the bandgap reference circuit, and the turn-on voltage of the second N-type MOS transistor is equal to the first turn-on voltage of the control circuit; and a third N-type MOS transistor, wherein the gate of the third N-type MOS transistor is connected to the output end of the second inverter, the drain of the third N-type MOS transistor is connected to the source of the second N-type MOS transistor, and the turn-on voltage of the third N-type MOS transistor is equal to the second turn-on voltage of the control circuit.

[0011] Preferably, the startup circuit further includes: a buffer, which is arranged between the second inverter and the third N-type MOS transistor.

[0012] Preferably, the feedback circuit is further configured to output the third level in response to the second control signal being pulled down to the fourth level when the first control signal satisfies the following abnormal conditions, wherein the fourth level is lower than the first turn-on voltage of the feedback circuit and the control circuit: within a first time period after the bandgap reference circuit is started, the first control signal cannot reach the target output voltage; or within a second time period after the first control signal reaches the target output voltage, the first control signal cannot be maintained at the target output voltage. Accordingly, the control circuit is further configured to re-output the startup voltage in response to the second control signal being maintained at the fourth level and the feedback circuit outputting the third level.

[0013] Preferably, the feedback circuit is further configured to, when the second control signal is pulled high and maintained at the first level, re-output the third level in response to the first control signal being higher than 0 and lower than the second level.

[0014] Through the above technical solution, the present invention creatively receives the output voltage of the bandgap reference circuit as a first control signal through a feedback circuit, and outputs a third level in response to the first control signal being higher than 0 and lower than the second level in response to the second control signal being pulled up to the second level and maintained at the first level; controls the startup voltage for the bandgap reference circuit to be lowered in response to the second control signal being pulled up and maintained at the first level and the third level output by the feedback circuit through the control circuit. Therefore, after providing the startup voltage to the bandgap reference circuit, the present invention can use the output voltage of the bandgap reference circuit as feedback to control the startup circuit to be shut down, so as to reduce the startup voltage, thereby greatly improving the reliability of the startup process of the bandgap reference circuit.

[0015] A second aspect of the present invention provides a chip, comprising: the startup circuit for the bandgap reference circuit.

[0016] For specific details and benefits of the chip provided by the embodiment of the present invention, please refer to the above description of the startup circuit for the bandgap reference circuit, which will not be repeated here.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0019] Figure 1 is a schematic structural diagram of a startup circuit provided by an embodiment of the present invention; and

[0020] Figure 2 4 is a circuit diagram of a startup circuit provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0022] Figure 1 FIG. 1 is a structural diagram of a startup circuit 20 for a bandgap reference circuit 10 provided by an embodiment of the present invention. Figure 1As shown, the startup circuit 20 may include: a feedback circuit 30, configured to perform the following operations: receive the output voltage of the bandgap reference circuit 10 as a first control signal; receive a second control signal; and output a third level in response to the first control signal being higher than 0 and lower than the second level when the second control signal is pulled high and maintained at the first level; and a control circuit 40, configured to control the startup voltage for the bandgap reference circuit 10 to decrease in response to the second control signal being pulled high and maintained at the first level and the third level output by the feedback circuit 30.

[0023] In this embodiment, the startup circuit is composed of two parts: one part is a control circuit, which is used to control the generation of the startup voltage; the other part is a feedback circuit, which is used to control the shutdown of the startup circuit.

[0024] The first level (for example, V DD ) is equal to or higher than a first turn-on voltage of the feedback circuit 30 and the control circuit 40 (for example, the turn-on voltage of the first P-type MOS transistor 34 (i.e., M6) described below, or the turn-on voltage of the fourth P-type MOS transistor 41 (i.e., M1) or the second N-type MOS transistor 42 (i.e., M2) described below), the second level (for example, 1.16V) is lower than the target output voltage of the bandgap reference circuit (for example, 1.2V), and the third level is higher than or equal to the second turn-on voltage of the control circuit 40 (for example, the turn-on voltage of the third N-type MOS transistor 43 (i.e., M3) described below).

[0025] In one embodiment, the feedback circuit 30 is further configured to, when the second control signal is maintained at a fourth level, output a third level in response to the first control signal being 0. The fourth level is lower than the first turn-on voltage of the feedback circuit 30 and the control circuit 40. In other words, the fourth level (e.g., 0) is lower than the first turn-on voltage of the feedback circuit 30 and the control circuit 40 (e.g., the turn-on voltage of the first P-type MOS transistor 34 (i.e., M6) described below, or the turn-on voltage of the fourth P-type MOS transistor 41 (i.e., M1) or the second N-type MOS transistor 42 (i.e., M2)).

[0026] Accordingly, the control circuit 40 is further configured to control the output of the startup voltage in response to the second control signal being maintained at the fourth level and the feedback circuit 30 outputting the third level.

[0027] like Figure 2As shown, the feedback circuit 30 may include: a first inverter 31, wherein the input end of the first inverter 31 is connected to the first control signal, and the turn-on level of the first inverter 31 is equal to the second level; a first N-type MOS transistor 32, wherein the gate of the first N-type MOS transistor 32 is connected to the output end of the first inverter 31; a second inverter 33, wherein the input end of the second inverter 33 is connected to the drain of the first N-type MOS transistor 32, and the turn-on level of the second inverter 33 is equal to the voltage of the drain power supply of the first N-type MOS transistor 32; and a first P-type MOS transistor 34, wherein the gate of the first P-type MOS transistor 34 is connected to the second control signal, and the turn-on voltage of the first P-type MOS transistor 34 is equal to the first turn-on voltage of the feedback circuit 30.

[0028] The first inverter 31 and the second inverter 33 may both be Schmitt inverters.

[0029] like Figure 2 As shown, the control circuit 40 may include: a fourth P-type MOS transistor 41, the gate of the fourth P-type MOS transistor 41 is connected to the second control signal, the source of the fourth P-type MOS transistor 41 is connected to the source of the first P-type MOS transistor 34, and the turn-on voltage of the fourth P-type MOS transistor 41 is equal to the first turn-on voltage of the control circuit 40; a second N-type MOS transistor 42, the gate of the second N-type MOS transistor 42 is connected to the second control signal, the drain of the second N-type MOS transistor 42 is connected to the fourth P-type MOS transistor The drain of the second N-type MOS transistor 41 is connected to the drain of the second N-type MOS transistor 41, and the connection point is used to provide a startup voltage for the bandgap reference circuit 10, and the turn-on voltage of the second N-type MOS transistor 42 is equal to the first turn-on voltage of the control circuit 40; and a third N-type MOS transistor 43, the gate of the third N-type MOS transistor 43 is connected to the output end of the second inverter 33, the drain of the third N-type MOS transistor 43 is connected to the source of the second N-type MOS transistor 42, and the turn-on voltage of the third N-type MOS transistor 43 is equal to the second turn-on voltage of the control circuit 40.

[0030] Specifically, in the initial state, the enable signal EN (i.e., the second control signal) is at the fourth level (e.g., low level 0V), and the output voltage of the bandgap reference circuit (i.e., the first control signal) is 0V. Therefore, the first P-type MOS transistor 34 (i.e., M6) is turned on; the gate voltage of the first N-type MOS transistor 32 (i.e., M0) is V DD , M0 is turned on; the second inverter 33 (ie ST1) outputs a high level (V DD Since the gate voltage of the third N-type MOS transistor 43 (ie M3) is V DD, so M3 is turned on (the startup circuit remains turned on). At the same time, since the enable signal EN (i.e., the second control signal) is at a low level of 0V, the fourth P-type MOS transistor 41 (i.e., M1) is turned on, and the second N-type MOS transistor 42 (i.e., M2) is turned off. Therefore, the control circuit 40 can output V DD , which is used as the starting voltage of the bandgap reference circuit 10 (the starting voltage is connected to the current mirror control gate of the bandgap reference source). At this time, since the starting voltage is at a high level, the bandgap reference circuit 10 does not operate.

[0031] Assuming that the target output voltage of the bandgap reference circuit 10 is 1.2V, the turn-on level of the first inverter 31 (ie, ST2) is equal to the second level (eg, 1.16V), and the turn-on level of the second inverter 33 (ie, ST1) is equal to the fifth level.

[0032] When the enable signal EN (ie, the second control signal) changes from the fourth level (eg, low level 0) to the first level (eg, high level V DD ), the output voltage of the bandgap reference circuit 10 (ie, the first control signal) gradually increases from 0. As the enable signal EN (ie, the second control signal) changes from low level 0 to high level V DD , the first P-type MOS transistor 34 (e.g., M6) is turned off. When the output voltage of the bandgap reference circuit 10 (i.e., the first control signal) gradually increases but is still lower than the second level (denoted as U2, for example, 1.16V), since the output voltage of the bandgap reference circuit 10 (i.e., the first control signal) is lower than the second level (i.e., the turn-on level of the first inverter 31 (i.e., ST2)), ST2 is not triggered and outputs a high level V DD , that is, the gate voltage of the first N-type MOS transistor 32 (ie, M0) is V DD , thus M0 is turned on; since the voltage at the input end of the second inverter 33 (ie ST1) is a low voltage (lower than V DD ), ST1 is not triggered and outputs the third level (high level V DD ); Since the third level is higher than or equal to the second turn-on voltage of the control circuit 40 (for example, the turn-on voltage of the third N-type MOS transistor 43 (i.e., M3)), M3 is turned on (the startup circuit remains turned on). At the same time, since the enable signal EN (i.e., the second control signal) is at a high level V DD , the fourth P-type MOS transistor 41 (i.e., M1) is turned off, and the second N-type MOS transistor 42 (i.e., M2) is turned on. Therefore, the voltage output by the control circuit 40 is pulled down. At this time, since the startup voltage is at a low level, the bandgap reference circuit 10 begins to operate.

[0033] like Figure 2As shown, the feedback circuit 30 may further include: a current source 38 (e.g., I_start), which is provided at a connection point between the input end of the second inverter 33 (e.g., ST1) and the drain of the first N-type MOS transistor 32 (e.g., M0) and the drain power supply (not shown, represented by V DD and a capacitor 34, one plate of the capacitor 34 is connected to the drain of the first N-type MOS transistor 32 and the current source (eg, I_start), and the other plate of the capacitor 34 is connected to the source of the first N-type MOS transistor 32.

[0034] Specifically, when the enable signal EN (ie, the second control signal) is maintained at the first level (eg, high level V DD ), when the output voltage of the bandgap reference circuit 10 (i.e., the first control signal) gradually rises to the second level (denoted as U2, for example, 1.16V), since the output voltage of the bandgap reference circuit 10 (i.e., the first control signal) is equal to the second level (i.e., the turn-on level of the first inverter 31 (i.e., ST2)), ST2 is triggered and the gate voltage of M0 is lowered, and M0 is turned off; at this time, the external current source I_start charges the capacitor 34 (i.e., C1), and the charging time is approximately equal to C*V DD / I_start. When the capacitor C1 is charged to a certain voltage but the voltage is lower than the start level of the second inverter 33 (ie ST1) (ie the fifth level, which is recorded as U5, for example V DD ), ST1 is not triggered and still outputs a high level (for example, V DD ), the gate voltage of the third N-type MOS transistor 43 (ie, M3) is high, and M3 is turned on. Since the enable signal EN (ie, the second control signal) is high, V DD Therefore, the fourth P-type MOS transistor 41 (ie, M1) is turned off, and the second N-type MOS transistor 42 (ie, M2) is turned on. Therefore, the voltage output by the control circuit 40 is still maintained at a low level.

[0035] When the capacitor C1 is charged to the fifth level (denoted as U5, for example, V DD ), since the voltage at the input terminal of the second inverter 33 (ie ST1) is V DD , ST1 is triggered and pulls down the gate voltage of the third N-type MOS transistor 43 (ie, M3), and M3 is turned off. Since the enable signal EN (ie, the second control signal) is at a high level V DD, the fourth P-type MOS transistor 41 (i.e., M1) is turned off, and the second N-type MOS transistor 42 (i.e., M2) is turned on. As a result, the voltage output by the control circuit 40 is delayed and transitions to a floating state. In other words, the feedback circuit 30 delays pulling down the gate voltage of M3 to 0V, delaying the shutdown of the control circuit 40, and the output terminal of the startup voltage becomes a high-impedance state.

[0036] In this embodiment, capacitor 34 is provided to delay the floating state of the startup voltage to a certain extent (and the extended time is controllable) to ensure the stability of the start-up process of the bandgap reference circuit. When the output voltage (i.e., the first control signal) of the bandgap reference circuit 10 reaches the target output voltage (e.g., 1.2V), the control circuit 40 is completely turned off, and the feedback circuit 30 is also completely under the control of a stable logic circuit. In addition to the leakage current of each MOS transistor, there is no other quiescent current. By selecting the appropriate size, the leakage current of the MOS transistor can be greatly reduced and can be ignored relative to other currents.

[0037] While the output voltage (i.e., the first control signal) of the bandgap reference circuit 10 gradually increases but is still lower than the second level (e.g., 1.16V), since the turn-on level of the first inverter 31 (i.e., ST2) is equal to the second level (e.g., 1.16V), ST2 outputs a high level; the first N-type MOS transistor 32 (i.e., M0) is turned on, and the external current source does not charge the capacitor C1 at this time.

[0038] In one embodiment, when the voltage of capacitor 35 reaches V DD After that, in order to keep the capacitor charged without using an external current source but keep the capacitor voltage at V DD In this embodiment, two P-type MOS tubes are provided.

[0039] The feedback circuit 30 may further include: a second P-type MOS transistor 36, wherein the source of the second P-type MOS transistor 36 is connected to the source of the first P-type MOS transistor 34, and the gate of the second P-type MOS transistor 36 is connected to the output end of the second inverter 33; and a third P-type MOS transistor 37, wherein the gate of the third P-type MOS transistor 37 is connected to the drain of the first P-type MOS transistor 34, the drain of the third P-type MOS transistor 37 is connected to the input end of the second inverter 33, and the source of the third P-type MOS transistor 37 is connected to the drain of the second P-type MOS transistor 36.

[0040] Specifically, when the enable signal EN (ie, the second control signal) is maintained at a high level V DDWhen the output voltage (i.e., the first control signal) reaches the second level (e.g., 1.16V), the first P-type MOS transistor 34 (e.g., M6) is turned off; the gate of the third P-type MOS transistor 37 (e.g., M4) is connected to the output end of the first inverter 31 (i.e., ST2) (or the gate of M0. According to the above description, the gate of M0 is at a low level at this time), so M4 is turned on; the gate of the second P-type MOS transistor 36 (e.g., M5) is connected to the output end of the second inverter 33 (e.g., ST1) (at a low level at this time), so M5 is turned on. In this way, the voltage of the capacitor 35 can be maintained at V by the internal drain power supply. DD .

[0041] This embodiment uses a feedback circuit to achieve the shutdown of the startup circuit. The reference voltage generated by the bandgap reference circuit is used as a feedback node. This feedback voltage is used to control the charging of the capacitor. After the capacitor is charged to the voltage of the drain power supply, M3 is turned off, thereby controlling the circuit to be shut down. At this time, the startup voltage is in a high-impedance state, and the startup circuit is shut down.

[0042] In order to achieve stable startup of the bandgap reference circuit 10, in this embodiment, it is also possible to determine whether the bandgap reference circuit is abnormal based on the feedback output voltage. When it is determined to be abnormal, the startup circuit is controlled to be turned on to provide a restart current at any time, thereby controlling the bandgap reference circuit to restart at any time.

[0043] In one embodiment, the feedback circuit 30 may be further configured to, when the second control signal is maintained at the fourth level, output the third level in response to the first control signal satisfying the following abnormal condition.

[0044] The fourth level (e.g., 0V) is lower than the first on-state voltage of the feedback circuit 30 and the control circuit 40 (e.g., the on-state voltage of the first P-type MOS transistor 34 (i.e., M6), or the on-state voltage of the fourth P-type MOS transistor 41 (i.e., M1) or the second N-type MOS transistor 42 (i.e., M2)).

[0045] The abnormal condition may include: the first control signal cannot reach the target output voltage within a first time period after the bandgap reference circuit 10 is started; or the first control signal cannot maintain the target output voltage within a second time period after the first control signal reaches the target output voltage. The first time period and the second time period may be the same or different and can be set according to actual needs.

[0046] Accordingly, the control circuit 40 is further configured to re-output the startup voltage in response to the second control signal being maintained at the fourth level and the feedback circuit 30 outputting the third level.

[0047] After the control circuit 40 re-outputs the start-up voltage, the feedback circuit 30 is further configured to re-output the third level in response to the first control signal being higher than 0 and lower than the second level when the second control signal is pulled high and maintained at the first level.

[0048] Specifically, when it is detected that the first control signal meets any of the above abnormal conditions, the feedback circuit 30 can also be used to respond to the enable signal EN (ie, the second control signal) from the high level V DD The voltage at the input of the second inverter 33 (i.e. ST1) is low (lower than V DD ), ST1 is not triggered and outputs the third level (i.e., high level). Since the third level is higher than or equal to the second conduction voltage of the control circuit 40 (for example, the conduction voltage of the third N-type MOS transistor 43 (i.e., M3)), M3 is turned on. At this time, the control circuit 40 can also output a ready signal (i.e., a high level signal) for use by subsequent circuits. Since the enable signal EN (i.e., the second control signal) is high level V DD The fourth P-type MOS transistor 41 (ie, M1) is turned on, and the second N-type MOS transistor 42 (ie, M2) is turned off. Therefore, the control circuit 40 can output V DD , to be used as the startup voltage of the bandgap reference circuit 10 (the startup voltage is connected to the current mirror control gate of the bandgap reference source). At this time, the bandgap reference circuit 10 does not operate.

[0049] Next, the feedback circuit 30 is configured to re-output the third level in response to the first control signal being higher than 0 and lower than the second level, when the second control signal is pulled high and maintained at the first level. The specific process of the feedback circuit re-outputting the third level (i.e., a low level) can be found in the above description and will not be further elaborated here.

[0050] like Figure 2 As shown, the startup circuit 20 may further include a buffer 50, which is disposed between the second inverter 33 and the third N-type MOS transistor 43. In this embodiment, the buffer 50 may also be used to further delay the floating state of the startup voltage to stabilize the startup process to a greater extent.

[0051] In the above embodiments, the output voltage of the bandgap reference source is detected by a feedback circuit, and the output voltage is used as a feedback node to shut down the startup circuit to reduce power consumption. A built-in delay circuit is also used to ensure a reliable and stable startup signal.

[0052] Therefore, the startup circuit is configured to: in response to the second control signal, transmit a startup voltage to the bandgap reference circuit to achieve stable startup of the bandgap reference circuit using the startup voltage; and, when the bandgap reference circuit is determined to be stable based on the output voltage, control the pre-startup circuit to shut down to reduce power consumption of the startup circuit. The feedback circuit is configured to detect the output voltage of the bandgap reference circuit and control the startup circuit to remain on or off based on the output voltage and the second control signal.

[0053] In summary, the present invention creatively receives the output voltage of the bandgap reference circuit as a first control signal through a feedback circuit, and outputs a third level in response to the first control signal being higher than 0 and lower than the second level in response to the second control signal being pulled high and maintained at the first level and the third level output by the feedback circuit; controls the startup voltage for the bandgap reference circuit to be lowered through the control circuit in response to the second control signal being pulled high and maintained at the first level and the third level output by the feedback circuit. Therefore, after providing the startup voltage to the bandgap reference circuit, the present invention can use the output voltage of the bandgap reference circuit as feedback to control the startup circuit to shut down, so as to reduce the startup voltage, thereby greatly improving the reliability of the startup process of the bandgap reference circuit.

[0054] An embodiment of the present invention further provides a chip, comprising: the startup circuit for the bandgap reference circuit.

[0055] For specific details and benefits of the chip provided by the embodiment of the present invention, please refer to the above description of the startup circuit for the bandgap reference circuit, which will not be repeated here.

[0056] Of course, the values ​​of the various levels in various embodiments of the present invention are not limited to the specific values ​​listed above. For example, the second level can be any reasonable value slightly lower than the target output voltage (e.g., 1.2V) (and not limited to 1.16V).

[0057] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.

[0058] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0059] Those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a single-chip microcomputer, chip or processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program code.

[0060] In addition, the various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A startup circuit for a bandgap reference circuit, characterized in that: The startup circuit comprises: A feedback circuit that performs the following operations: receiving an output voltage of the bandgap reference circuit as a first control signal; receiving a second control signal; and In the case where the second control signal is pulled high and maintained at the first level, in response to the first control signal being higher than 0 and lower than the second level, a third level is output, further configured to output the third level in response to the first control signal being 0 when the second control signal is maintained at a fourth level, wherein the fourth level is lower than the first turn-on voltage of the feedback circuit and the control circuit, and a control circuit for controlling a startup voltage for the bandgap reference circuit to decrease in response to the second control signal being pulled high and maintained at the first level and the third level being output by the feedback circuit; Accordingly, the control circuit is further configured to control the output of the start-up voltage in response to the second control signal being maintained at the fourth level and the third level output by the feedback circuit, wherein the first level is equal to or higher than the first turn-on voltage of the feedback circuit and the control circuit, the second level is lower than the target output voltage of the bandgap reference circuit, and the third level is higher than or equal to the second turn-on voltage of the control circuit.

2. The starting circuit according to claim 1, characterized in that: The feedback circuit comprises: a first inverter, wherein an input terminal of the first inverter is connected to the first control signal, and a turn-on level of the first inverter is equal to the second level; a first N-type MOS transistor, wherein a gate of the first N-type MOS transistor is connected to an output end of the first inverter; a second inverter, wherein an input terminal of the second inverter is connected to the drain of the first N-type MOS transistor, and a turn-on level of the second inverter is equal to a voltage of a drain power supply of the first N-type MOS transistor; and A first P-type MOS transistor, wherein a gate of the first P-type MOS transistor is connected to the second control signal, and a turn-on voltage of the first P-type MOS transistor is equal to a first turn-on voltage of the feedback circuit.

3. The starting circuit according to claim 2, characterized in that: The feedback circuit further includes: a current source provided between a connection point where the input terminal of the second inverter is connected to the drain of the first N-type MOS transistor and the drain power supply; and A capacitor, one plate of the capacitor is connected to the drain of the first N-type MOS transistor and the current source, and the other plate of the capacitor is connected to the source of the first N-type MOS transistor.

4. The starting circuit according to claim 3, characterized in that: The feedback circuit further includes: a second P-type MOS transistor, wherein a source of the second P-type MOS transistor is connected to the source of the first P-type MOS transistor, and a gate of the second P-type MOS transistor is connected to the output end of the second inverter; and a third P-type MOS transistor, wherein the gate of the third P-type MOS transistor is connected to the drain of the first P-type MOS transistor, the drain of the third P-type MOS transistor is connected to the input end of the second inverter, and the source of the third P-type MOS transistor is connected to the drain of the second P-type MOS transistor.

5. The starting circuit according to claim 2, characterized in that: The control circuit comprises: a fourth P-type MOS transistor, wherein a gate of the fourth P-type MOS transistor is connected to the second control signal, a source of the fourth P-type MOS transistor is connected to the source of the first P-type MOS transistor, and a turn-on voltage of the fourth P-type MOS transistor is equal to the first turn-on voltage of the control circuit; a second N-type MOS transistor, wherein the gate of the second N-type MOS transistor is connected to the second control signal, the drain of the second N-type MOS transistor is connected to the drain of the fourth P-type MOS transistor, and the connection point is used to provide a startup voltage for the bandgap reference circuit, and the turn-on voltage of the second N-type MOS transistor is equal to the first turn-on voltage of the control circuit; and a third N-type MOS transistor, wherein a gate of the third N-type MOS transistor is connected to the output end of the second inverter, a drain of the third N-type MOS transistor is connected to the source of the second N-type MOS transistor, and a turn-on voltage of the third N-type MOS transistor is equal to the second turn-on voltage of the control circuit.

6. The starting circuit according to claim 5, characterized in that: The startup circuit further includes: A buffer is provided between the second inverter and the third N-type MOS transistor.

7. The starting circuit according to claim 1, wherein: The feedback circuit is further configured to, in response to the second control signal being pulled down to a fourth level, output the third level when the first control signal satisfies the following abnormal condition, wherein the fourth level is lower than the first conduction voltage between the feedback circuit and the control circuit: The first control signal cannot reach the target output voltage within a first time period after the bandgap reference circuit is started; or During a second time period after the first control signal reaches the target output voltage, the first control signal cannot be maintained at the target output voltage. Correspondingly, the control circuit is further configured to, in response to the second control signal being maintained at the fourth level and the feedback circuit outputting the third level, re-output the startup voltage.

8. The starting circuit according to claim 7, characterized in that: The feedback circuit is further configured to, when the second control signal is pulled high and maintained at the first level, re-output the third level in response to the first control signal being higher than 0 and lower than the second level.

9. A chip, characterized in that: The chip includes: a startup circuit for a bandgap reference circuit according to any one of claims 1-8.

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