A data shifting method and a configurable barrel shifting device

The data is pre-processed and shifted through a five-stage pipeline structure, which solves the problem of the single function of the existing barrel shifter, realizes flexible processing of different data bit widths, reduces system latency and improves shifting speed.

CN116225536BActive Publication Date: 2025-10-03XIAN UNIV OF POSTS & TELECOMM
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202310165915.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-02-24
Publication Date
2025-10-03
Estimated Expiration
2043-02-24

AI Technical Summary

Technical Problem

Existing barrel shifters and shifting methods can only complete the shifting of specific data bit widths, and have problems such as long delay, large size, and relatively simple functions.

Method used

By presetting the number of shift bits and data bit width, a five-stage pipeline structure is used to preprocess and shift the data, including data discarding, copying, splicing and zero-filling operations. Combined with mask shielding, flexible configuration of different data bit widths and shift bits can be achieved.

Benefits of technology

It realizes flexible processing of different data bit widths, reduces system latency, and improves shift speed and system performance.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN116225536B_ABST
    Figure CN116225536B_ABST
Patent Text Reader

Abstract

The present invention provides a data shifting method and a configurable barrel shifter, which are used to solve the technical problems that existing barrel shifters and shifting methods can only complete shifting of specific data bit widths and have large delays, large volumes, and relatively simple functions. The shifting method of the present invention is as follows: 1] copying and splicing the upper M bits of data with a data bit width less than or equal to M; directly outputting data with a data bit width greater than M; 2] copying and splicing the upper x bits of data with a data bit width less than or equal to M output in step 1]; copying and splicing the upper x bits of data with a data bit width greater than M; shifting the processed data with a bit width greater than M according to i_shft[b-1:b-2]; 3] shifting the data processed in step 2] according to i_shft[b-3:b-5]; 4] shifting the data processed in step 3] according to i_shft[b-6:0]; 5] using a mask to mask the bits that are 0 in the data processed in step 4] to complete the data shift.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to a data shifting method and device, and particularly to a data shifting method and a configurable barrel shifter device. Background Art

[0002] A barrel shifter is a combinational logic circuit and is usually part of a microprocessor CPU. It has multiple data inputs, multiple data outputs, and control inputs specifying how to shift the external input data, specifying the shift direction, shift type, and shift number of bits. A barrel shifter is usually composed of multiple multiplexers and can shift the external input data by a specific number of bits within one clock cycle. However, the existing barrel shifters and shifting methods can only complete the shifting of specific data widths and have problems such as large time delay, large volume, and relatively single functions. Summary of the Invention

[0003] An object of the present invention is to provide a data shifting method and a configurable barrel shifter device for the technical problems that the existing barrel shifters and shifting methods can only complete the shifting of specific data widths and have large time delay, large volume, and relatively single functions.

[0004] To achieve the above object, the technical solution of the present invention is as follows:

[0005] A data shifting method, characterized in that it includes the following steps:

[0006] 1] Preset the shift number of bits b, and preprocess the external input data with a data width less than or equal to M to set the shift number of bits b to the minimum number of bits required for the maximum data width a supported by the barrel shifter;

[0007] If the data width of the external input data is less than or equal to M, set the data processing width to a, first discard the low (a - M) bits of the external input data, then copy the high M bits of the external input data and splice the copied data after the high M bits, and finally fill 0 at the low positions of the spliced data according to the data processing width a and output it as the first output data;

[0008] If the data width of the external input data is greater than M, directly output it as the first output data; where M = a - 32*(8*n), a > M; when 0 < a ≤ 32*24, n is 1; when 32*24 < a ≤ 32*25, n = 2; when 32*25 < a ≤ 32*26, n = 3, and so on;

[0009] 2] Process the first output data

[0010] If the data bit width of the first output data is less than or equal to M, the data processing width is set to 2M, the low (ax) bits of the first output data are discarded first, the high x bits of the first output data are copied and the copied data is spliced ​​after the high x bits, and finally the low bits of the spliced ​​data are padded with 0 according to the data processing width 2M and output as the second output data;

[0011] If the data bit width of the first output data is greater than M, the data processing width is set to 2a, the low (ax) bits of the first output data are first discarded, the high x bits of the first output data are copied and the copied data are spliced ​​after the high x bits, and finally the low bits after the spliced ​​data are padded with 0 according to the data processing width 2a to serve as the intermediate data; the corresponding bits of the intermediate data are then shifted according to i_shft[b-1:b-2], and the shifted data is output as the second output data; where x represents the actual bit width of the first output data, and i_shft[b-1:b-2] represents the shift signals of the highest bit and the second highest bit in the shift bit number b;

[0012] 3] Shift the corresponding bits of the second output data according to i_shft[b-3:b-5], and output the shifted data as the third output data; wherein i_shft[b-3:b-5] represents the shift signal from the third to the fifth most significant bit in the shift bit number b;

[0013] 4] Shift the corresponding bits of the third output data according to i_shft[b-6:0], and output the shifted data as the fourth output data; wherein i_shft[b-6:0] represents the shift signal from the sixth most significant bit to the least significant bit in the shift bit b;

[0014] 5] Mask the bits of the fourth output data that are 0 to complete the data shift.

[0015] Furthermore, the maximum data bit width supported by the barrel shifter is a=384;

[0016] The shift number b=9;

[0017] M=128;

[0018] The actual bit width x of the first output data ranges from 32, 64, 96, 128, 160, 224, 256, 288, 320, 352, and 384.

[0019] The present invention also provides a configurable barrel shift device for implementing the above-mentioned data shift method, which is special in that it includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, a fourth-stage pipeline, and a fifth-stage pipeline connected in sequence according to input and output order;

[0020] The first-stage pipeline includes a first data processing unit and a second register; the input end of the first data processing unit is used to receive external input data and perform corresponding preprocessing on the external input data according to the data bit width; the preprocessing is as follows: if the data bit width of the external input data is less than or equal to M, set the data processing width to a, first discard the low (a - M) bits of the external input data, then copy the high M bits of the external input data and splice the copied data after the high M bits, and finally fill 0 at the low positions of the spliced data according to the data processing width a as the first output data for output; if the data bit width of the external input data is greater than M, directly output it as the first output data; where M = a - 32*(8*n), a > M; when 0 < a ≤ 32*24, n is 1; when 32*24 < a ≤ 32*25, n = 2; when 32*25 < a ≤ 32*26, n = 3, and so on;

[0021] The input end of the second register is used to receive and store the preset i_shft[b - 1:0]; where, i_shft[b - 1:0] represents the shift signals from the highest bit to the lowest bit in the shift bit number b, and the shift bit number b is set to the minimum number of bits required for the maximum data bit width a supported by the barrel shifter;

[0022] The second-stage pipeline includes a second data processing unit, a third data processing unit, a first shift module and a third register; the input end of the second data processing unit is used to receive the first output data with a data bit width less than or equal to M, and the data processing width is set to 2M, and the low (ax) bit of the first output data is discarded first, and then the high x bits of the first output data are copied and the copied data are spliced ​​after the high x bits, and finally the low bits of the spliced ​​data are padded with 0 according to the data processing width 2M, and output as the second output data; the input end of the third data processing unit is used to receive the first output data with a data bit width greater than M, and the data processing width is set to 2a, and the low (ax) bit of the first output data is discarded first, and then the high x bits of the first output data are copied and the copied data are spliced ​​after the high x bits, and finally the low bits of the spliced ​​data are padded with 0 according to the data processing width Degree 2a fills the low bits of the spliced ​​data with 0 as intermediate data; two input ends of the first shift module are respectively connected to the output end of the third data processing unit and one output end of the second register, for shifting the corresponding bits of the intermediate data according to i_shft[b-1:b-2] in i_shft[b-1:0], and outputting the shifted data as second output data; the input end of the third register is connected to the other output end of the second register, for receiving and storing i_shft[b-3:0]; wherein i_shft[b-1:b-2] represents the shift signals on the highest bit and the second highest bit in the shift number b, i_shft[b-3:0] represents the shift signal from the third highest bit to the lowest bit in the shift number b, and x represents the actual bit width of the first output data;

[0023] The third-stage pipeline includes a first selection module, a second shift unit, and a sixth register; two input ends of the first selection module are respectively connected to the output end of the second data processing unit and the output end of the first shift module, for selecting the second output data with a data bit width less than or equal to M and the second output data with a data bit width greater than M; two input ends of the second shift unit are respectively connected to the output end of the first selection module and an output end of the third register, for shifting the corresponding bits of the second output data selected by the first selection module according to i_shft[b-3:b-5] in i_shft[b-3:0], and outputting the shifted data as the third output data; an input end of the sixth register is connected to the other output end of the third register, for receiving and storing i_shft[b-6:0]; wherein i_shft[b-6:0] represents a shift signal from the sixth highest bit to the lowest bit in the shift bit b;

[0024] The fourth-stage pipeline includes a third shift unit; two input terminals of the third shift unit are respectively connected to the output terminal of the sixth register and the output terminal of the second shift unit, and is used to shift corresponding bits of the third output data according to i_shft[b-6:0] and output the shifted data as the fourth output data;

[0025] The input end of the fifth stage pipeline is connected to the output end of the third shift unit, and is used to mask the bits of 0 in the fourth output data in a mask form, and its output end serves as the output of the barrel shift device.

[0026] Furthermore, the first data processing unit includes a first judgment module, a first data processing module, a first selector and a first register;

[0027] The first judgment module is used to receive external input data and judge whether the data bit width of the external input data is less than or equal to M or greater than M. The two output ends of the first judgment module are respectively connected to the input end of the first data processing module and one input end of the first selector, and is used to send the external input data with a data bit width less than or equal to M to the first data processing module, and send the external input data with a data bit width greater than M to one input port of the first selector;

[0028] The first data processing module is used to pre-process external input data with a data bit width less than or equal to M, and its output end is connected to the other input end of the first selector;

[0029] The first selector selects pre-processed data with a data bit width less than or equal to M or external input data with a data bit width greater than M, and the selected data serves as the first output data;

[0030] The storage capacity of the first register is a, and its input end is connected to the output end of the first selector for storing the first output data, and its output is sent to the second data processing unit or the third data processing unit.

[0031] Furthermore, the second stage pipeline further includes a second judgment module, an eighteenth register and a nineteenth register;

[0032] The second data processing unit includes a second data processing module, a second selector and a fourth register;

[0033] The third data processing unit includes a third data processing module, a third selector and a fifth register;

[0034] The input end of the second judgment module is connected to the output end of the first register, and is used to receive the first output data and judge whether the data bit width of the first output data is less than or equal to M or greater than M. The two output ends of the second judgment module are respectively connected to the input end of the second data processing module and the input end of the third data processing module;

[0035] The second data processing module is configured to first discard the low (ax) bits of the first output data having a data bit width less than or equal to M, then copy the high x bits thereof and concatenate the copied data after the high x bits, and finally fill the low bits of the concatenated data with 0s according to the data processing width of 2M; the multiple input ends of the second selector are respectively connected to the corresponding multiple output ends of the second data processing module, for selecting data of different bit widths processed by the second data processing module and outputting the selected data as the second output data; the storage capacity of the fourth register is 2M, the input end of the fourth register is connected to the output end of the second selector, and the output end of the fourth register is connected to the input end of the eighteenth register, for sequentially sending the second output data to the fourth register and the eighteenth register for storage at two levels before outputting the data; the output end of the eighteenth register is connected to an input end of the first selection module;

[0036] The third data processing module is used to first discard the low (ax) bits of the first output data whose data bit width is greater than M, then copy its high x bits and splice the copied data after the high x bits, and finally fill the low bits of the spliced ​​data with 0 according to the data processing width 2a; the multiple input ends of the third selector are respectively connected to the corresponding multiple output ends of the third data processing module, for selecting data of different bit widths processed by the third data processing module, and using the selected data as intermediate data; the storage capacity of the fifth register is 2a, and its input end is connected to the output end of the third selector; the two input ends of the first shift module are respectively connected to an output end of the second register and the output end of the fifth register, for shifting the corresponding bits of the selected intermediate data through i_shft[b-1:b-2] in i_shft[b-1:0], and outputting the shifted data as the second output data; the input end of the nineteenth register is connected to the output end of the first shift module, and its output end is connected to the other input end of the first selection module.

[0037] Furthermore, the second selector is 2 k-2 Multiplexer with select 1, the third selector is 2 k-1 A multiplexer that selects 1; k is the number of binary digits that satisfies the maximum data bit width a.

[0038] Furthermore, the first selection module includes a fourth selector and a seventh register; the input end of the fourth selector is connected to the output end of the eighteenth register and the output end of the nineteenth register respectively, and the output end thereof is connected to the input end of the seventh register;

[0039] The second shift unit includes a second shift module, a first storage module and an eleventh register;

[0040] Two input terminals of the second shift module are respectively connected to an output terminal of the third register and an output terminal of the seventh register, and are used to shift corresponding bits of the data in the seventh register according to i_shft[b-3:b-5] in i_shft[b-3:0];

[0041] The input end of the first storage module is connected to the output end of the second shift module, and is used to store the value after each shift;

[0042] The input end of the eleventh register is connected to the output end of the first storage module, and the output end of the eleventh register is connected to the input end of the third shift unit.

[0043] Furthermore, the third shift unit includes a third shift module, a second storage module and a twelfth register;

[0044] The two input terminals of the third shift module are respectively connected to the output terminal of the eleventh register and the output terminal of the sixth register, and are used to shift the data in the eleventh register according to i_shft[b-6:0];

[0045] The input end of the second storage module is connected to the output end of the third shift module, and is used to store the value after each shift;

[0046] The input end of the twelfth register is connected to the output end of the second storage module, and the output end thereof is connected to the input end of the fifth stage pipeline.

[0047] Furthermore, the fifth stage pipeline includes a mask shielding module and a seventeenth register;

[0048] The input end of the mask shielding module is connected to the output end of the twelfth register, and is used to shield the bits of the fourth output data that are 0 in the form of a mask;

[0049] The input end of the seventeenth register is connected to the output end of the mask shielding module for storing the masked data, and the output end thereof serves as the output of the barrel shift device.

[0050] Furthermore, the maximum data bit width supported by the barrel shifter is a=384;

[0051] The shift bit b=9; M=128;

[0052] The actual bit width x of the first output data ranges from 32, 64, 96, 128, 160, 224, 256, 288, 320, 352, and 384;

[0053] The second selector is a 4-to-1 multiplexer, and the third selector is an 8-to-1 multiplexer.

[0054] The beneficial effects of the present invention compared to the prior art are:

[0055] 1. The present invention provides a data shifting method that preprocesses input data with a data width less than or equal to M and greater than M before shifting. The method has simple and flexible control and fast shifting speed, and is suitable for high-performance and low-latency designs.

[0056] 2. The present invention provides a configurable barrel shifter, which uses a five-stage pipeline setting to pre-process input data with a data width less than or equal to M and greater than M before shifting. It supports different data widths and different shift bit numbers, and realizes the configurability of data width and shift bit numbers. It has simple control, more flexible structure, fast shifting speed, reduced system latency, and improved system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the structure of the first-stage pipeline and the second-stage pipeline in an embodiment of the present invention;

[0058] Figure 2 Schematic diagram of the structure of the third-stage pipeline, the fourth-stage pipeline and the fifth-stage pipeline in an embodiment of the present invention, wherein Figure 2 The input of the third stage pipeline and Figure 1 The output terminal of the second stage pipeline is connected;

[0059] Figure 3 The data bit width of the input data, the binary expression of the data bit width, the binary expression that satisfies the maximum data bit width, and the corresponding data of the discarded bits in the embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] In this embodiment, input data with a data bit width ranging from 32 to 384 bits is shifted, the input data is left-aligned, and 32 bits is used as a unit. Shifting of input data with a data bit width that is an integral multiple of 32 can be achieved.

[0062] A data shifting method comprises the following steps:

[0063] 1] Preset the number of shift bits b and preprocess the external input data with a data width less than or equal to M

[0064] The number of shift bits b is set to the minimum number of bits required by the maximum data bit width a supported by the barrel shifter; since the maximum data bit width a of the input data in this embodiment is 384 bits, by 2 8 <384<2 9, we know that the minimum number of bits required is 9, that is, the number of shift bits b is 9 bits, which is specifically expressed as i_shft[8:0] (representing the shift signal from the highest bit to the lowest bit in the shift number b).

[0065] Determine the data preprocessing method based on the data bit width of the external input data:

[0066] In this embodiment, M is 128 bits. If the data bit width of the external input data is less than or equal to 128 bits, the data processing width is set to 384 bits to pre-process the external input data. Specifically, the lower 256 bits of the external input data are discarded, and then the upper 128 bits of the external input data are copied and the copied data is spliced ​​after the upper 128 bits. Finally, according to the set data processing width of 384 bits, the lower bits of the spliced ​​data are padded with 0s and output as the first output data. If the data bit width of the input data is greater than 128 bits, it is directly output as the first output data.

[0067] 2] Process the first output data

[0068] Determine the data processing method based on the data bit width of the first output data:

[0069] If the data bit width of the first output data is less than or equal to 128 bits, the data processing width is set to 256 bits to process the first output data. Specifically, the first output data is processed by first discarding the low-order (ax) bits of the first output data, then copying the high-order x bits of the first output data and concatenating the copied data after the high-order x bits, and finally padding the low-order bits of the concatenated data with 0s according to the set data processing width of 256 bits, and outputting the data as the second output data, where x represents the actual bit width of the first output data. Specifically, in this embodiment, the first output data with a data bit width less than or equal to 128 bits includes four data types: 128 bits, 96 bits, 64 bits, and 32 bits. If the data bit width of the first output data is 128 bits, the lower 256 bits of the first output data are discarded, and the upper 128 bits of the first output data are copied and spliced ​​after the upper 128 bits, that is, the upper 256 bits are intercepted; if the data bit width of the first output data is 96 bits, the lower 288 bits of the first output data are discarded, and the upper 96 bits of the first output data are copied and spliced ​​after the upper 96 bits, and finally the lower 64 bits are padded with 0s; if the data bit width of the first output data is 64 bits, the lower 320 bits of the first output data are discarded, and the upper 64 bits of the first output data are copied and spliced ​​after the upper 64 bits, and finally the lower 128 bits are padded with 0s; if the data bit width of the first output data is 32 bits, the lower 352 bits of the first output data are discarded, and the upper 32 bits of the first output data are copied and spliced ​​after the upper 32 bits, and finally the lower 192 bits are padded with 0s.

[0070] If the data bit width of the first output data is greater than 128 bits, the data processing width is set to 768 bits to process the first output data. Specifically, the first output data is processed by first discarding the low (ax) bits of the first output data, then copying the high x bits of the first output data and splicing the copied data after the high x bits, and finally padding the low bits of the spliced ​​data with 0s according to the set data processing width of 768 bits to serve as intermediate data; then, the intermediate data is shifted according to i_shft[8:7] in i_shft[8:0] (representing the shift signals for the highest and second highest bits in the shift bit b), and the shifted data is output as the second output data. Specifically, in this embodiment, the first output data with a data bit width greater than 128 bits are 8 data types: 384 bits, 352 bits, 320 bits, 288 bits, 256 bits, 224 bits, 192 bits, and 160 bits. If the data bit width of the first output data is 384 bits, the high 384 bits of the first output data are copied and the copied data are spliced ​​after the high 384 bits; if the data bit width of the first output data is 352 bits, the low 32 bits of the first output data are discarded first, the high 352 bits are copied and the copied data are spliced ​​after the high 352 bits, and finally the low 64 bits are filled with 0s; if the data bit width of the first output data is 320 bits, the low 64 bits of the first output data are discarded first, the high 320 bits are copied and the copied data are spliced ​​after the high 320 bits, and finally the low 128 bits are filled with 0s; if the data bit width of the first output data is 288 bits, the low 96 bits of the first output data are discarded first, the high 288 bits are copied and the copied data are spliced ​​after the high 288 bits, and finally the low 192 bits are filled with 0s; if the data bit width of the first output data is 256 If the data width of the first output data is 224 bits, the lower 128 bits of the first output data are discarded first, the upper 256 bits are copied and the copied data is spliced ​​after the upper 256 bits, and finally the lower 256 bits are filled with all 0s. If the data width of the first output data is 224 bits, the lower 160 bits of the first output data are discarded first, the upper 224 bits are copied and the copied data is spliced ​​after the upper 224 bits, and finally the lower 320 bits are filled with all 0s. If the data width of the first output data is 192 bits, the lower 192 bits of the first output data are discarded first, the upper 192 bits are copied and the copied data is spliced ​​after the upper 192 bits, and finally the lower 384 bits are filled with all 0s. If the data width of the first output data is 160 bits, the lower 224 bits of the first output data are discarded first, the upper 160 bits are copied and the copied data is spliced ​​after the upper 160 bits, and finally the lower 448 bits are filled with all 0s. Then, the corresponding bits of the intermediate data are shifted according to i_shft[8:7], that is, the highest and second highest bits of the shift bit number b.Since i_shft[8] and i_shft[7] cannot be 1 at the same time, first determine the value of i_shft[8]. If i_shft[8] is 1, that is, i_shft[7] is 0, indicating that the data needs to be shifted left by 256 bits, then the lower 512 bits of the intermediate data are intercepted. If i_shft[8] is 0, determine the value of i_shft[7]. If i_shft[7] is 1, that is, i_shft[8] is 0, indicating that the data needs to be shifted left by 128 bits, then the [639:128] bits of the intermediate data are intercepted. If i_shft[7] is 0 and i_shft[8] is also 0, indicating that the data does not shift, then the [767:256] bits of the intermediate data are intercepted.

[0071] 3] Shift the corresponding bits of the second output data according to i_shft[6:4] (representing the shift signal from the 6th bit to the 4th bit in the shift bit b)

[0072] First, determine the value of i_shft[6]. If i_shft[6] is 1, it indicates that the data needs to be shifted 64 bits to the left, so the lower 448 bits of the second output data are intercepted. If i_shft[6] is 0, it indicates that the input data is not shifted, so the upper 448 bits of the second output data are intercepted. Then determine the value of i_shft[5]. If i_shft[5] is 1, it indicates that the data needs to be shifted 32 bits to the left, so the lower 416 bits of the data after i_shft[6] shift are intercepted. If i_shft[5] is 1, it indicates that the data needs to be shifted 32 bits to the left, so the lower 416 bits of the data after i_shft[6] shift are intercepted. When [5] is 0, it indicates that the data is not shifted, so the upper 416 bits of the data after i_shft[6] shift are intercepted; then the value of i_shft[4] is judged. If i_shft[4] is 1, it indicates that the data is to be shifted left by 16 bits, so the lower 400 bits of the data after i_shft[5] shift are intercepted. If i_shft[4] is 0, it indicates that the data is not shifted, so the upper 400 bits of the data after i_shft[5] shift are intercepted, and the intercepted value is output as the third output data.

[0073] 4] Shift the corresponding bit of the third output data according to i_shft[3:0]

[0074] First, determine the value of i_shft[3]. If [3] is 1, it indicates that the data needs to be shifted 8 bits to the left, and the lower 392 bits of the third output data are intercepted. If [3] is 0, it indicates that the data does not shift, and the upper 392 bits of the third output data are intercepted. Then determine the value of i_shft[2]. If i_shft[2] is 1, it indicates that the data needs to be shifted 4 bits to the left, and the lower 388 bits of the data after i_shft[3] shift are intercepted. If i_shft[2] is 0, it indicates that the input data does not shift, and the upper 388 bits of the data after i_shft[3] shift are intercepted. Then determine the value of i_shft[1]. If i_shft[ When i_shft[1] is 1, it indicates that the data needs to be shifted left by 2 bits, and the lower 386 bits of the data after i_shft[2] shift are intercepted. If i_shft[1] is 0, it indicates that the data does not shift, and the upper 386 bits of the data after i_shft[2] shift are intercepted. Then the value of i_shft[0] is judged. If i_shft[0] is 1, it indicates that the data needs to be shifted left by 1 bit, and the lower 384 bits of the data after i_shft[1] shift are intercepted. If i_shft[0] is 0, it indicates that the data does not shift, and the upper 384 bits of the data after i_shft[1] shift are intercepted, and the intercepted value is output as the fourth output data.

[0075] 5] Use a mask to mask the bits of the fourth output data that are 0 to complete the data shift.

[0076] The present invention also provides a configurable barrel shift device for implementing the above-mentioned data shift method, which includes a five-stage pipeline, such as Figure 1 、 Figure 2 As shown, there are specifically a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, a fourth-stage pipeline and a fifth-stage pipeline connected in sequence according to input and output.

[0077] The first stage pipeline includes a first judgment module, a first data processing module, a first selector, a first register and a second register. The first judgment module is used to receive external input data and judge whether the data width of the external input data is less than or equal to 128 bits or greater than 128 bits. Figure 3As shown, since the data bit width range of the external input data in this embodiment is 32-384 bits, its corresponding binary number i_datw is set to 4 bits, namely 1111-0001; and since the maximum data bit width a of the input data is 384 bits, the number of bits k that satisfies the binary expression of 384 bits is 4 bits, and its highest bit to lowest bit is specifically represented by dat_w[3:0]. Therefore, in this embodiment, dat_w[3], that is, the highest bit of the binary expression, is used to determine whether the data bit width is less than or equal to 128 bits or greater than 128 bits; specifically, when dat_w[3] is 1, it indicates that the data bit width of the input data is less than or equal to 128 bits, and when dat_w[3] is 0, it indicates that the data bit width of the input data is greater than 128 bits. The two output ends of the first judgment module are respectively connected to the input end of the first data processing module and an input end of the first selector, for sending input data with a data bit width less than or equal to 128 bits to the first data processing module, and sending input data with a data bit width greater than 128 bits to an input port of the first selector. The first data processing module is used to set the data processing width to 384 bits to preprocess input data with a data bit width less than or equal to 128 bits. Specifically, the lower 256 bits of the external input data are discarded, the upper 128 bits of the external input data are copied and the copied data is spliced ​​after the upper 128 bits, and finally, the lower bits of the spliced ​​data are padded with 0s according to the data processing width of 384 bits.

[0078] The other input end of the first selector is connected to the output end of the first data processing module, and is used to select pre-processed data with a data bit width less than or equal to 128 bits or external input data with a data bit width greater than 128 bits, and the selected data is used as the first output data. The storage capacity of the first register is 384 bits, and its input end is connected to the output end of the first selector, and is used to store the first output data. The input end of the second register is used to receive and store a preset number of shift bits b; according to the calculation results in step 1 of the above method, the number of shift bits b in this embodiment is set to 9 bits, specifically expressed as i_shft[8:0]. The output of the first register and the output of the second register are respectively used as the two inputs of the second-stage pipeline.

[0079] The second-stage pipeline includes a second judgment module, a second data processing module, a second selector, a fourth register, an eighteenth register, a third data processing module, a third selector, a fifth register, a first shift module, a nineteenth register and a third register.

[0080] The second judgment module has an input connected to the output of the first register, is configured to receive the first output data, and determine whether the data width of the first output data is less than or equal to 128 bits or greater than 128 bits. The specific determination method is the same as that used by the first judgment module in the first-stage pipeline. The second judgment module's two outputs are connected to the inputs of the second data processing module and the third data processing module, respectively, to send first output data with a data width less than or equal to 128 bits to the second data processing module, and first output data with a data width greater than 128 bits to the third data processing module.

[0081] The second data processing module is used to further process the first output data with a data bit width less than or equal to 128 bits. Since there are four data with a data bit width less than or equal to 128 bits in this embodiment, specifically 128 bits, 96 bits, 64 bits, and 32 bits, and dat_w[1:0] (representing the second and first bits in the binary expression that satisfies 384 bits) can represent these four data, the second data processing module is provided with four output terminals, and the corresponding second selector is provided as a 4-to-1 multiplexer; the four output terminals of the second data processing module are respectively connected to the four input terminals of the second selector, for selecting one of the above four data and outputting the selected data as the second output data. The storage capacity of the fourth register is 256 bits, and its input terminal is connected to the output terminal of the second selector, for storing the second output data. Specifically, if dat_w[1:0]=00, indicating that the data bit width of the first output data is 128 bits, the lower 256 bits of the first output data are discarded first, and then the upper 128 bits of the first output data are copied and the copied data is spliced ​​after the upper 128 bits, that is, the upper 256 bits are intercepted and temporarily stored in the fourth register; if dat_w[1:0]=01, indicating that the data bit width of the first output data is 96 bits, the lower 288 bits of the first output data are discarded first, and then the upper 96 bits of the first output data are copied and the copied data is spliced ​​after the upper 96 bits, and finally the lower 64 bits are padded with 0 and temporarily stored in the fourth register In the example, if dat_w[1:0]=10, indicating that the data bit width of the first output data is 64 bits, the lower 320 bits of the first output data are discarded first, the upper 64 bits of the first output data are copied and the copied data is spliced ​​after the upper 64 bits, and finally the lower 128 bits are padded with 0s before being temporarily stored in the fourth register; if dat_w[1:0]=11, indicating that the data bit width of the first output data is 32 bits, the lower 352 bits of the first output data are discarded first, the upper 32 bits of the first output data are copied and the copied data is spliced ​​after the upper 32 bits, and finally the lower 192 bits are padded with 0s before being temporarily stored in the fourth register. The input end of the eighteenth register is connected to the output end of the fourth register, and is used to register the second output data with a data bit width less than or equal to 128 bits for another level. The output of the eighteenth register serves as the first input of the third-level pipeline.

[0082] The third data processing module is configured to preprocess the first output data with a data bit width greater than 128 bits. In this embodiment, there are eight data types with a data bit width greater than 128 bits and less than or equal to 384 bits, specifically 384 bits, 352 bits, 320 bits, 288 bits, 256 bits, 224 bits, 192 bits, and 160 bits. Since dat_w[2:0] (representing the third to first bits in the binary expression satisfying 384 bits) can represent these eight data types, the third data processing module is configured with eight output terminals, and the corresponding third selector is configured as an 8-to-1 multiplexer. The eight output terminals of the third data processing module are respectively connected to the eight input terminals of the third selector, for selecting one of the eight data types and using the selected data as the intermediate data. The fifth register has a storage capacity of 768 bits, and its input terminal is connected to the output terminal of the third selector for storing the intermediate data.Specifically, if dat_w[2:0]=000, indicating that the data bit width of the first output data is 384 bits, the high 384 bits of the first output data are copied and the copied data are spliced ​​after the high 384 bits, and then temporarily stored in the fifth register; if dat_w[2:0]=001, indicating that the data bit width of the first output data is 352 bits, the low 32 bits of the first output data are discarded first, and then the high 352 bits are copied and the copied data are spliced ​​after the high 352 bits, and finally the low 64 bits are filled with 0s and temporarily stored in the fifth register; if dat_w[2:0]=010, If the data width of the first output data is 320 bits, the lower 64 bits of the first output data are discarded first, and then the upper 320 bits are copied and the copied data is spliced ​​after the upper 320 bits, and finally the lower 128 bits are filled with 0s and temporarily stored in the fifth register; if dat_w[2:0]=011, it means that the data width of the first output data is 288 bits, the lower 96 bits of the first output data are discarded first, and then the upper 288 bits are copied and the copied data is spliced ​​after the upper 288 bits, and finally the lower 192 bits are filled with 0s and temporarily stored in the fifth register; if dat_w[2:0]= 100, indicating that the data bit width of the first output data is 256 bits, then discard the lower 128 bits of the first output data, then copy its upper 256 bits and splice the copied data after the upper 256 bits, finally fill the lower 256 bits with 0s and temporarily store them in the fifth register; if dat_w[2:0]=101, indicating that the data bit width of the first output data is 224 bits, then discard the lower 160 bits of the first output data, then copy its upper 224 bits and splice the copied data after the upper 224 bits, finally fill the lower 320 bits with 0s and temporarily store them in the fifth register; if dat_w [2:0]=110, indicating that the data bit width of the first output data is 192 bits, then the lower 192 bits of the first output data are discarded first, then the upper 192 bits are copied and the copied data is spliced ​​after the upper 192 bits, and finally the lower 384 bits are padded with 0s and temporarily stored in the fifth register; if dat_w[2:0]=111, indicating that the data bit width of the first output data is 160 bits, then the lower 224 bits of the first output data are discarded first, then the upper 160 bits are copied and the copied data is spliced ​​after the upper 160 bits, and finally the lower 448 bits are padded with 0s and temporarily stored in the fifth register.

[0083] The two input ends of the first shift module are respectively connected to an output end of the second register and an output end of the fifth register, and are used to shift the corresponding bits of the intermediate data stored in the fifth register according to i_shft[8:7] in i_shft[8:0], and use the shifted data as the second output data; specifically, since i_shft[8] and i_shft[7] cannot be 1 at the same time, the value of i_shft[8] is first judged. If i_shft[8] is 1, that is, i_shft[7] is 0, it indicates that the input If the data needs to be shifted left by 256 bits, the lower 512 bits of the data in the fifth register are intercepted. If i_shft[8] is 0, the value of i_shft[7] is determined. If i_shft[7] is 1, that is, i_shft[8] is 0, indicating that the input data needs to be shifted left by 128 bits, the [639:128] bits of the data in the fifth register are intercepted. If i_shft[7] is 0 and i_shft[8] is also 0, indicating that the input data does not shift, the [767:256] bits of the data in the fifth register are intercepted. In this embodiment, the first shift module uses two 2-to-1 selectors to implement the data shift of i_shft[8:7]. The input end of the nineteenth register is connected to the output end of the first shift module, and its output serves as the second input of the third-stage pipeline.

[0084] The input end of the third register is connected to the other output end of the second register, and is used to receive and store i_shft[8:0], and output i_shft[6:0] therein as the third input of the third stage pipeline.

[0085] The third-stage pipeline includes a first selection module, a second shift module, a first storage module, an eleventh register, and a sixth register. The first selection module includes a fourth selector and a seventh register. In this embodiment, the fourth selector is a 2-to-1 selector, whose input end is connected to the output end of the eighteenth register and the output end of the nineteenth register, respectively, for selecting the second output data with a data bit width less than or equal to 128 bits and the second output data with a data bit width greater than 128 bits. The storage capacity of the seventh register is set to 512 bits, and its input end is connected to the output end of the fourth selector, for storing the data selected by the fourth selector. Specifically, when dat_w[3] is 1, the fourth selector selects the second output data with a data bit width less than or equal to 128 bits and temporarily stores it in the seventh register. When dat_w[3] is 0, the fourth selector selects the second output data with a data bit width greater than 128 bits and temporarily stores it in the seventh register.

[0086] The two input ends of the second shift module are respectively connected to an output end of the third register and an output end of the seventh register, and are used to shift the corresponding bits of the data in the seventh register according to i_shft[6:4] in i_shft[6:0], and output the shifted data as the third output data. The first storage module includes an eighth register, a ninth register, and a tenth register. In this embodiment, the storage capacity of the eighth register is set to 448 bits, the storage capacity of the ninth register is set to 416 bits, and the storage capacity of the tenth register is set to 400 bits. Specifically, the value of i_shft[6] is first determined. If i_shft[6] is 1, it indicates that the data needs to be shifted left by 64 bits, then the lower 448 bits of the data in the seventh register are intercepted. If i_shft[6] is 0, it indicates that the data does not need to be shifted, then the upper 448 bits of the data in the seventh register are intercepted, and the intercepted value is temporarily stored in the eighth register. Then the value of i_shft[5] is determined. If i_shft[5] is 1, it indicates that the data needs to be shifted left by 32 bits, then the lower 416 bits of the data in the eighth register are intercepted. 6Bit, if i_shft[5] is 0, indicating that the data is not shifted, the high 416Bits of the data in the eighth register are intercepted, and the intercepted value is temporarily stored in the ninth register; then the value of i_shft[4] is judged. If i_shft[4] is 1, indicating that the data needs to be shifted left by 16Bits, the low 400Bits of the data in the ninth register are intercepted. If i_shft[3] is 0, indicating that the data is not shifted, the high 400Bits of the data in the ninth register are intercepted, and the intercepted value is temporarily stored in the tenth register. In this embodiment, the second shift module uses three 2-to-1 selectors to implement i_shft[6:4] to shift the corresponding bits of the data. The input end of the eleventh register is connected to the output end of the tenth register for storing the third output data, and its output serves as an input of the fourth-stage pipeline.

[0087] The input end of the sixth register is connected to another output end of the third register for receiving i_shft[6:0] and outputting i_shft[3:0] therein as another input of the fourth stage pipeline.

[0088] The fourth-stage pipeline includes a third shift module, a second storage module, and a twelfth register. The two input terminals of the third shift module are connected to the output terminals of the eleventh register and the sixth register, respectively, for shifting corresponding bits of the third output data according to i_shft[3:0] and outputting the shifted data as the fourth output data. The second storage module includes a thirteenth register, a fourteenth register, a fifteenth register, and a sixteenth register. In this embodiment, the storage capacity of the thirteenth register is set to 392 bits, the storage capacity of the fourteenth register is set to 388 bits, the storage capacity of the fifteenth register is set to 386 bits, and the storage capacity of the sixteenth register is set to 384 bits. Specifically, first determine the value of i_shft[3]. If i_shft[3] is 1, it indicates that the data needs to be shifted left by 8 bits, then the lower 392 bits of the third output data are intercepted. If i_shft[3] is 0, it indicates that the data does not shift, then the upper 392 bits of the third output data are intercepted, and the intercepted value is temporarily stored in the thirteenth register. Then determine the value of i_shft[2]. If i_shft[2] is 1, it indicates that the input data needs to be shifted left by 4 bits, then the lower 388 bits of the data in the thirteenth register are intercepted. If i_shft[2] is 0, it indicates that the input data does not shift, then the upper 388 bits of the data in the thirteenth register are intercepted, and the intercepted value is temporarily stored in the fourteenth register. Then determine The value of i_shft[1] is: if i_shft[1] is 1, it indicates that the input data needs to be shifted left by 2 bits, then the lower 386 bits of the data in the fourteenth register are intercepted; if i_shft[1] is 0, it indicates that the input data does not shift, then the upper 386 bits of the data in the fourteenth register are intercepted and the intercepted value is temporarily stored in the fifteenth register; then the value of i_shft[0] is judged. If i_shft[0] is 1, it indicates that the input data needs to be shifted left by 1 bit, then the lower 384 bits of the data in the fifteenth register are intercepted; if i_shft[0] is 0, it indicates that the input data does not shift, then the upper 384 bits of the data in the fifteenth register are intercepted and the intercepted value is temporarily stored in the sixteenth register. In this embodiment, the third shift module uses four 2-to-1 selectors to implement i_shft[3:0] to shift the corresponding bits of the data. The input end of the twelfth register is connected to the output end of the sixteenth register for storing the fourth output data, and its output serves as the input of the fifth-stage pipeline.

[0089] The fifth-stage pipeline includes a mask shielding module and a seventeenth register connected in sequence according to the input and output order. The input end of the mask shielding module is connected to the output end of the twelfth register, and is used to mask the bits of the fourth output data that are 0 in the form of a mask; since the data bit width range of the input data in this embodiment is 32-384 bits, which contains 12 data, the mask is set to 12 bits, and each 1 bit represents 32 bits of the output data of the fourth-stage pipeline; specifically, when i_datw is 0001, the mask format is 1000_0000_0000, and when i_datw is 0001, the mask format is 1000_0000_0000. When tw is 0010, the mask format is 1100_0000_0000. When i_datw is 0011, the mask format is 1110_0000_0000. Similarly, when i_datw is 1011, the mask format is 1111_1111_1110. A bit with a 1 in the corresponding mask indicates that the corresponding bit of the fourth-stage pipeline output data is valid and retained. A bit with a 0 indicates that the corresponding bit of the fourth-stage pipeline output data is invalid and set to zero. The storage capacity of the seventeenth register is set to 384 bits, which is used to store data processed by the mask shielding module. The output result of the seventeenth register serves as the final output of the barrel shifter, and the output data is left-aligned.

[0090] This embodiment uses a 5-stage pipeline to realize data shifting, and its data bit width and shift bit number are configurable. This embodiment is simulated on QuartusⅡ20.2 version. The selected chip is Intel Altera's Arria10GX-1150 series, model 10AX115N2F45E1SG, and the board clock frequency is constrained to 500MHz. After integration, the maximum clock frequency can reach 580MHz.

[0091] The above description is only used to illustrate the technical solution of the present invention, rather than to limit it. For ordinary professional and technical personnel in this field, the specific technical solutions recorded in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution protected by the present invention.

Claims

1. A data shifting method, characterized in that: The following steps are involved: 1] Preset the number of shift bits b and pre-process the external input data with a data width less than or equal to M to set the number of shift bits b to the minimum number of bits required for the maximum data width a supported by the barrel shifter; If the data bit width of the external input data is less than or equal to M, the data processing width is set to a, the low (aM) bits of the external input data are discarded first, then the high M bits are copied and the copied data is spliced ​​after the high M bits, and finally the low bits at the end are padded with 0 according to the data processing width a, and output as the first output data; If the data bit width of the external input data is greater than M, it is directly output as the first output data; where M = a-32*(8*n), n = b-8; 2] Process the first output data If the data bit width of the first output data is less than or equal to M, the data processing width is set to 2M, the low (ax) bits of the first output data are discarded, the high x bits are copied and the copied data is spliced ​​after the high x bits, and finally the low bits at the end are padded with 0 according to the data processing width of 2M, and the data is output as the second output data; If the data bit width of the first output data is greater than M, the data processing width is set to 2a. The low-order (ax) bits of the first output data are first discarded, and then the high-order x bits are copied and the copied data is spliced ​​after the high-order x bits. Finally, the low-order bits at the end are padded with 0 according to the data processing width 2a to serve as the intermediate data. The corresponding bits of the intermediate data are then shifted according to i_shft[b-1:b-2], and the shifted data is output as the second output data. Wherein, x represents the actual bit width of the first output data, and i_shft[b-1:b-2] represents the shift signals of the highest and second-highest bits in the shift number b. 3] Shift the corresponding bits of the second output data according to i_shft[b-3:b-5], and output the shifted data as the third output data; wherein i_shft[b-3:b-5] represents the shift signal from the third to the fifth most significant bit in the shift bit number b; 4] Shift the corresponding bits of the third output data according to i_shft[b-6:0], and output the shifted data as the fourth output data; wherein i_shft[b-6:0] represents the shift signal from the sixth most significant bit to the least significant bit in the shift bit b; 5] Mask the bits of the fourth output data that are 0 to complete the data shift.

2. A data shifting method according to claim 1, characterized in that: The maximum data bit width a supported by the barrel shifter is 384; The shift number b=9; M=128; The actual bit width x of the first output data ranges from 32, 64, 96, 128, 160, 224, 256, 288, 320, 352, and 384.

3. A configurable barrel shift device for implementing a data shift method according to claim 1 or 2, characterized in that: It includes a first-stage pipeline, a second-stage pipeline, a third-stage pipeline, a fourth-stage pipeline, and a fifth-stage pipeline connected in sequence according to the input and output order; The first-stage pipeline includes a first data processing unit and a second register; the input end of the first data processing unit is used to receive external input data and perform corresponding preprocessing on the external input data according to the data bit width; the preprocessing is as follows: if the data bit width of the external input data is less than or equal to M, then the data processing width is set to a, the low (aM) bits of the external input data are first discarded, then the high M bits are copied and the copied data are spliced ​​after the high M bits, and finally, according to the data processing width a, the low bits behind are padded with 0s and output as the first output data; if the data bit width of the external input data is greater than M, then it is directly output as the first output data; wherein M=a-32*(8*n), n=b-8; the input end of the second register is used to receive and store a preset i_shft[b-1:0]; wherein i_shft[b-1:0] represents a shift signal from the highest bit to the lowest bit in the shift bit b, and the shift bit b is set to the minimum number of bits required for the maximum data bit width a supported by the barrel shifter; The second-stage pipeline includes a second data processing unit, a third data processing unit, a first shift module and a third register; the input end of the second data processing unit is used to receive the first output data with a data bit width less than or equal to M, and the data processing width is set to 2M, and the low (ax) bit of the first output data is first discarded, and then the high x bits thereof are copied and the copied data are spliced ​​after the high x bits, and finally the low bits at the end are padded with 0 according to the data processing width 2M, and output as the second output data; the input end of the third data processing unit is used to receive the first output data with a data bit width greater than M, and the data processing width is set to 2a, and the low (ax) bit of the first output data is first discarded, and then the high x bits thereof are copied and the copied data are spliced ​​after the high x bits, and finally the low bits at the end are padded with 0 according to the data processing width 2a. The lower bits of the sides are padded with 0 as intermediate data; the two input ends of the first shift module are respectively connected to the output end of the third data processing unit and an output end of the second register, for shifting the corresponding bits of the intermediate data according to i_shft[b-1:b-2] in i_shft[b-1:0], and outputting the shifted data as the second output data; the input end of the third register is connected to the other output end of the second register, for receiving and storing i_shft[b-3:0]; wherein i_shft[b-1:b-2] represents the shift signals on the highest bit and the second highest bit in the shift number b, i_shft[b-3:0] represents the shift signal from the third highest bit to the lowest bit in the shift number b, and x represents the actual bit width of the first output data; The third-stage pipeline includes a first selection module, a second shift unit, and a sixth register; two input ends of the first selection module are respectively connected to the output end of the second data processing unit and the output end of the first shift module, for selecting the second output data with a data bit width less than or equal to M and the second output data with a data bit width greater than M; two input ends of the second shift unit are respectively connected to the output end of the first selection module and an output end of the third register, for shifting the corresponding bits of the second output data selected by the first selection module according to i_shft[b-3:b-5] in i_shft[b-3:0], and outputting the shifted data as the third output data; an input end of the sixth register is connected to the other output end of the third register, for receiving and storing i_shft[b-6:0]; wherein i_shft[b-6:0] represents a shift signal from the sixth highest bit to the lowest bit in the shift bit b; The fourth-stage pipeline includes a third shift unit; two input terminals of the third shift unit are respectively connected to the output terminal of the sixth register and the output terminal of the second shift unit, and is used to shift corresponding bits of the third output data according to i_shft[b-6:0] and output the shifted data as the fourth output data; The input end of the fifth stage pipeline is connected to the output end of the third shift unit, and is used to mask the bits of 0 in the fourth output data in a mask form, and its output end serves as the output of the barrel shift device.

4. A configurable barrel shifting device according to claim 3, characterized in that: The first data processing unit includes a first judgment module, a first data processing module, a first selector and a first register; The first judgment module is used to receive external input data and judge whether the data bit width of the external input data is less than or equal to M or greater than M. The two output ends of the first judgment module are respectively connected to the input end of the first data processing module and one input end of the first selector, and is used to send the external input data with a data bit width less than or equal to M to the first data processing module, and send the external input data with a data bit width greater than M to one input port of the first selector; The first data processing module is used to pre-process external input data with a data bit width less than or equal to M, and its output end is connected to the other input end of the first selector; The first selector selects pre-processed data with a data bit width less than or equal to M or external input data with a data bit width greater than M, and the selected data serves as the first output data; The storage capacity of the first register is a, and its input end is connected to the output end of the first selector for storing the first output data, and its output is sent to the second data processing unit or the third data processing unit.

5. The configurable barrel shifting device according to claim 4, characterized in that: The second stage pipeline further includes a second judgment module, an eighteenth register and a nineteenth register; The second data processing unit includes a second data processing module, a second selector and a fourth register; The third data processing unit includes a third data processing module, a third selector and a fifth register; The input end of the second judgment module is connected to the output end of the first register, and is used to receive the first output data and judge whether the data bit width of the first output data is less than or equal to M or greater than M. The two output ends of the second judgment module are respectively connected to the input end of the second data processing module and the input end of the third data processing module; The second data processing module is configured to first discard the lower (ax) bits of the first output data having a data bit width less than or equal to M, then copy the upper x bits thereof and concatenate the copied data after the upper x bits, and finally fill the lower bits with 0s according to the data processing width 2M; the plurality of input ends of the second selector are respectively connected to the corresponding plurality of output ends of the second data processing module, for selecting data of different bit widths processed by the second data processing module, and outputting the selected data as the second output data; The storage capacity of the fourth register is 2M, the input end of the fourth register is connected to the output end of the second selector, and the output end of the fourth register is connected to the input end of the eighteenth register, and is used to sequentially send the second output data to the fourth register and the eighteenth register for storage at two levels before outputting; the output end of the eighteenth register is connected to an input end of the first selection module; The third data processing module is used to first discard the low (ax) bits of the first output data whose data bit width is greater than M, then copy its high x bits and splice the copied data after the high x bits, and finally fill the low bits at the end with 0 according to the data processing width 2a; the multiple input ends of the third selector are respectively connected to the corresponding multiple output ends of the third data processing module, for selecting data of different bit widths processed by the third data processing module, and using the selected data as intermediate data; the storage capacity of the fifth register is 2a, and its input end is connected to the output end of the third selector; the two input ends of the first shift module are respectively connected to an output end of the second register and the output end of the fifth register, for shifting the corresponding bits of the selected intermediate data through i_shft[b-1:b-2] in i_shft[b-1:0], and outputting the shifted data as the second output data; the input end of the nineteenth register is connected to the output end of the first shift module, and its output end is connected to the other input end of the first selection module.

6. The configurable barrel shifting device according to claim 5, characterized in that: The second selector is 2 k-2 Multiplexer with select 1, the third selector is 2 k-1 A multiplexer that selects 1; k is the number of binary digits that satisfies the maximum data bit width a.

7. A configurable barrel shifting device according to any one of claims 3 to 6, characterized in that: The first selection module includes a fourth selector and a seventh register; the input end of the fourth selector is connected to the output end of the eighteenth register and the output end of the nineteenth register respectively, and the output end thereof is connected to the input end of the seventh register; The second shift unit includes a second shift module, a first storage module and an eleventh register; Two input terminals of the second shift module are respectively connected to an output terminal of the third register and an output terminal of the seventh register, and are used to shift corresponding bits of the data in the seventh register according to i_shft[b-3:b-5] in i_shft[b-3:0]; The input end of the first storage module is connected to the output end of the second shift module, and is used to store the value after each shift; The input end of the eleventh register is connected to the output end of the first storage module, and the output end of the eleventh register is connected to the input end of the third shift unit.

8. The configurable barrel shifting device according to claim 7, characterized in that: The third shift unit includes a third shift module, a second storage module and a twelfth register; The two input terminals of the third shift module are respectively connected to the output terminal of the eleventh register and the output terminal of the sixth register, and are used to shift the data in the eleventh register according to i_shft[b-6:0]; The input end of the second storage module is connected to the output end of the third shift module, and is used to store the value after each shift; The input end of the twelfth register is connected to the output end of the second storage module, and the output end thereof is connected to the input end of the fifth stage pipeline.

9. The configurable barrel shifting device according to claim 8, characterized in that: The fifth stage pipeline includes a mask shielding module and a seventeenth register; The input end of the mask shielding module is connected to the output end of the twelfth register, and is used to shield the bits of the fourth output data that are 0 in the form of a mask; The input end of the seventeenth register is connected to the output end of the mask shielding module for storing the masked data, and the output end thereof serves as the output of the barrel shift device.

10. The configurable barrel shifting device according to claim 9, characterized in that: The maximum data bit width a supported by the barrel shifter is 384; The shift bit b=9; M=128; The actual bit width x of the first output data ranges from 32, 64, 96, 128, 160, 224, 256, 288, 320, 352, and 384; The second selector is a 4-to-1 multiplexer, and the third selector is an 8-to-1 multiplexer.

Citation Information

Patent Citations

  • Cyclic shift device, cyclic shift method, ldpc decoding device, television receiver, and receiving system

    CN102171936A

  • Computer implemented data parsing for DSP

    US20040193848A1