A sampling data validity checking method under a relay protection dual-CPU architecture

Abstract

The application discloses a kind of sampling data validity checking methods under the double CPU architecture of relay protection, comprising: protection device detects and judges whether sampling value is established, judges to be established with the same phase sampling value as synchronous reference quantity and carries out forward zero-crossing protection sampling adjustment, synchronously double CPU sampling;The deviation of the sampling value of double CPU is compared to judge whether double CPU sampling is inconsistent, if it is judged that it is inconsistent, then protection device sends corresponding alarm information and locks corresponding protection element.The application can adjust the sampling period according to the sampling value of CPU, ensure that double CPU is in consistent sampling beat, realize the effectiveness check of sampling data by the method of double CPU information sharing in the protection application level, solve the problem of isolated sampling data of double CPU, improve the stability of protection device, and have good application prospect.

Description

Technical Field

[0001] This invention relates to the field of power system relay protection, and in particular to a method for validating the validity of sampled data under a dual-CPU architecture for relay protection. Background Technology

[0002] Relay protection devices are an important component of power systems. As power systems continue to develop, the requirements for the reliability of protection device operation are also constantly increasing.

[0003] Among the factors affecting the reliability of protection devices, the accuracy of secondary-side analog signal sampling is crucial, directly impacting the correctness of protective element operation. Currently, protection devices typically determine the usability of sampled data based on the testing results of hardware such as analog-to-digital converter sampling chips. If an anomaly is detected in the sampling-related hardware, the entire device is usually locked out. In a dual-CPU architecture, both CPUs sample independently, without a unified sampling cycle, and Fourier calculations are also performed independently. The sampled data from both CPUs form information silos. If a sampling anomaly occurs in the AD circuit of one CPU, and the front-end sampling circuit does not detect the anomaly, the protection application will also fail to perceive the data anomaly. This CPU will then use the abnormal data for calculations, potentially leading to incorrect operation of the protective elements. Currently, there is no effective method to verify the validity of dual-CPU sampled data. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for validating the validity of sampled data under a dual-CPU architecture for relay protection, so that the two CPUs are in a consistent sampling cycle, and the validity of the sampled data is realized at the protection application level through the method of information sharing between the two CPUs.

[0005] To solve the above-mentioned technical problems, the present invention is implemented using the following solution:

[0006] This invention provides a method for validating sampled data under a dual-CPU architecture in relay protection, comprising:

[0007] The protection device detects and determines whether the sampling value has been established. If it is determined that the sampling value of the same phase has been established, the positive zero-crossing protection sampling adjustment is performed using the sampling value of the same phase as the synchronization reference quantity, and the dual CPU sampling is synchronized.

[0008] The device determines whether the sampling of the two CPUs is inconsistent by comparing the deviation of the sampling values. If the discrepancy is found, the protection device issues a corresponding alarm message and locks the corresponding protection element.

[0009] The system employs dual CPUs for independent sampling; and uses the same phase sample value as a synchronization reference for positive zero-crossing protection sampling adjustment, including:

[0010] Select the first sampling point after the positive zero crossing of this wave;

[0011] Calculate the angle corresponding to the selected sampling point of this current wave and the sampling time deviation of the selected sampling point of this current wave from the zero crossing point;

[0012] After entering the next cycle, adjust the sampling time at the zero point.

[0013] Preferably, the protection device detects and determines whether a sampled value has been established, including:

[0014] When N1≥0.04In and N2≥0.04In, it is determined that the sampled value has been established; otherwise, it is determined that the sampled value has not been established.

[0015] Where N1 and N2 are the fundamental effective values ​​of the sampled values ​​of CPU1 and CPU2, respectively, and In is the rated value of the secondary side of the voltage or current.

[0016] Preferably, using the same phase sample value as the synchronization reference includes:

[0017] Based on the principle of phase voltage priority, the sampling values ​​of phase A, phase B and phase C are detected in real time in sequence;

[0018] The result of a phase voltage or phase current selected by the main CPU is sent to the slave CPU.

[0019] Preferably, the first sampling point after the positive zero crossing of this current wave is selected, including:

[0020] Select the first sampling point of this current wave that meets the selection criteria, record the sampled value and number it as 0;

[0021] The selection criteria are: the current sample value is greater than or equal to 0, and the previous sample value is less than 0.

[0022] Preferably, the formula for calculating the angle corresponding to the sampling point selected this week is:

[0023]

[0024] In the formula, U a u is the fundamental effective value of the sampled value of this phase of the current wave. a0 It is the instantaneous value of the first sampling point after the zero crossing.

[0025] Preferably, the formula for calculating the sampling time deviation between the selected sampling point and the zero-crossing point of this current wave is:

[0026]

[0027] In the formula, T is the sampling interval, S is the number of sampling points per cycle, and φ is the angle corresponding to the sampling point.

[0028] Preferably, the sampling time at the zero-crossing point is adjusted after entering the next cycle, including:

[0029] Adjust the sampling interval of the next cycle to T-T0 to ensure that the next cycle is sampled at the positive zero crossing point and the sampling number is 0.

[0030] Preferably, the two CPUs exchange sampled values ​​in real time via a high-speed bus, with a transmission delay of 1 to 2 ms. The transmitted sampled values ​​are assigned a sample number, which corresponds to the sampled data in the CPU cache.

[0031] Preferably, determining whether the sampling of the two CPUs is inconsistent by comparing the deviation of the sampling values ​​of the two CPUs includes:

[0032] Obtain the effective value and instantaneous value of each voltage or current analog sample from the dual CPUs.

[0033] Based on conditions one and two, it is determined whether the sampling of the two CPUs is inconsistent. When condition one is met for 10ms or condition two is met for 6 out of 10 sampling points, it is determined that the sampling of the two CPUs is inconsistent, and the protection device issues the corresponding alarm information and locks the corresponding protection element.

[0034] Condition one is:

[0035] |X1-X2|≥K1*max{|X1|,|X2|}

[0036] In the formula, X1 and X2 are the real-time fundamental effective values ​​of the sampling points of CPU1 and CPU2, respectively, and K1 is the set proportional coefficient;

[0037] Condition two is:

[0038] |X3-X4|≥K2*max{|X3|,|X4|}

[0039] In the formula, X3 represents the number of cycles of CPU1. arrive Passing the exam arrive The instantaneous value of the sampling point, X4 is the CPU2's... arrive Passing the exam arrive The instantaneous value of the sampling point, S is the number of sampling points per cycle, and K2 is the tuning proportional coefficient.

[0040] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The present invention can adjust the sampling period according to the sampling value of the CPU, ensuring that the two CPUs are in a consistent sampling rhythm. At the protection application level, the validity verification of the sampling data is realized through the method of information sharing between the two CPUs, which solves the problem of the sampling data of the two CPUs being isolated from each other, improves the stability of the protection device, and has good application prospects. Attached Figure Description

[0041] Figure 1 This is a flowchart of a method for validating sampled data under a dual-CPU architecture for relay protection, provided by an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of positive zero-crossing sampling adjustment in a method for validating the validity of sampled data under a dual-CPU architecture for relay protection provided in an embodiment of the present invention; Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0044] like Figure 1 and 2 As shown in the figure, this invention provides a method for validating the validity of sampled data under a dual-CPU architecture for relay protection. Figure 1 As shown, it includes the following steps:

[0045] Step 1: Power on for protection, dual CPUs independently sample

[0046] When the protection device is powered on, the dual CPUs perform independent sampling according to the sampling frequency and sampling interval.

[0047] Step 2: Determine if the sampled values ​​have been established

[0048] The protection device detects and determines whether the sampled value has been established: when N1≥0.04In and N2≥0.04In, it is determined that the sampled value has been established; otherwise, it is determined that the sampled value has not been established. Wherein, N1 and N2 are the fundamental effective values ​​of the sampled values ​​of CPU1 and CPU2, respectively, and In is the rated value of the secondary side of the voltage or current.

[0049] Step 3: Adjust positive zero-crossing protection sampling and synchronous dual-CPU sampling.

[0050] After the judgment is established, the same phase sample value is used as the synchronization reference for positive zero-crossing protection sampling adjustment, and synchronous dual-CPU sampling is performed, such as... Figure 2 As shown, it includes:

[0051] The method for determining the sampled value of the same phase is as follows: based on the principle of phase voltage priority, with the priority of phase A → phase B → phase C, the sampled value is detected in real time, and the result of a phase voltage or a phase current selected by the main CPU is sent to the slave CPU, thereby determining the same phase as the synchronization reference quantity;

[0052] (1) Select the first sampling point after the positive zero crossing of this wave.

[0053] Select the first sampling point of this current wave that satisfies the condition "the current sample value is greater than or equal to 0 and the previous sample value is less than 0", record the sample value and number it 0.

[0054] (2) Calculate the angle corresponding to the selected sampling point of this current wave and the sampling time deviation of the selected sampling point of this current wave from the zero crossing point.

[0055] After this wave ends, according to the formula Calculate the angle corresponding to the sampling point numbered 0 where the current wave crosses zero in the positive direction, where U a u is the fundamental effective value of the sampled value of this phase of the current wave. a0 It is the instantaneous value of the first sampling point after the zero crossing; according to the formula Calculate the sampling time deviation between the sampling point numbered 0 and the zero-crossing point for each positive zero-crossing of the current cycle, where S is the number of sampling points per cycle and φ is the angle corresponding to the sampling point. T is the sampling interval, and f is the sampling frequency.

[0056] (3) Adjust the sampling time of the zero-crossing point after entering the next cycle.

[0057] After entering the next cycle, adjust the sampling interval to T-T0 to ensure that the next cycle is sampled at the positive zero crossing point and the sampling number is 0. Subsequently, restore the sampling interval to T.

[0058] After the above three steps, synchronous sampling of dual CPUs is achieved.

[0059] Step 4: Logic Detection of Inconsistent Sampling between Dual CPUs

[0060] The discrepancy between the sampled values ​​from the two CPUs is compared to determine whether the sampling is inconsistent, and thus the validity of the sampled data is determined. The specific steps are as follows:

[0061] Two CPUs exchange sampled values ​​in real time via a high-speed bus with a transmission delay of 1-2ms. To address the mismatch caused by time differences in sampled values, the CPU cache stores the sampled values' sampling numbers, and the transmitted sampled values ​​also carry the sampling numbers. The sampling numbers can be used to address and map the corresponding sampled data in the CPU cache.

[0062] After the sampling cycles of the two CPUs are synchronized, the criterion for judging the inconsistency of sampling between the two CPUs is as follows: compare the effective value and instantaneous value of each voltage or current analog quantity sampled by the two CPUs respectively. If the difference is greater than a set threshold, it is judged as sampling inconsistency. The two discrimination conditions for effective value and instantaneous value are ORed. Among them, the effective value discrimination condition (condition one) is: |X1-X2|≥K1*max{|X1|,|X2|}, where X1 and X2 are the real-time fundamental effective values ​​of the sampling points of CPU1 and CPU2 respectively, and K1 is the set proportional coefficient; the instantaneous value discrimination condition (condition two) is: |X3-X4|≥K2*max{|X3|,|X4|}, where X3 is the effective value of each cycle of CPU1. arrive Passing the exam arrive The instantaneous values ​​of the sampling points, namely the 5 points near the peak and the 5 points near the trough, X4 is the CPU2's... arrive Passing the exam arrive The instantaneous value of the sampling point, S is the number of sampling points per cycle, and K2 is the set proportional coefficient; if condition one is met for 10ms or condition two is met for 6 out of 10 sampling points, it is determined that the sampling values ​​of the dual CPUs are inconsistent, and the protection device issues relevant alarm information and locks the relevant protection elements.

[0063] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for validating the validity of sampled data under a dual-CPU architecture for relay protection, characterized in that, include: The protection device detects and determines whether the sampling value has been established. If it is determined that the sampling value of the same phase has been established, the positive zero-crossing protection sampling adjustment is performed using the sampling value of the same phase as the synchronization reference quantity, and the dual CPU sampling is synchronized. The device determines whether the sampling of the two CPUs is inconsistent by comparing the deviation of the sampling values. If the discrepancy is found, the protection device issues a corresponding alarm message and locks the corresponding protection element. The system employs dual CPUs for independent sampling; and uses the same phase sample value as a synchronization reference for positive zero-crossing protection sampling adjustment, including: Select the first sampling point after the positive zero crossing of this wave; Calculate the angle corresponding to the selected sampling point of this current wave and the sampling time deviation of the selected sampling point of this current wave from the zero crossing point; Adjust the sampling time at the zero-crossing point after entering the next wave; The formula for calculating the angle corresponding to the sampling point selected this week is: ； In the formula, This is the fundamental effective value of the sampled value for this phase of the current wave. The instantaneous value of the first sampling point after the zero crossing; The formula for calculating the sampling time deviation between the selected sampling point and the zero-crossing point of this current wave is: ； In the formula, The sampling interval is... The number of sampling points per cycle, The angle corresponding to the location of the sampling point; After entering the next wave, adjust the sampling time at the zero-crossing point, including: Adjust the sampling interval of the next cycle to This ensures that the next wave will be sampled at the positive zero-crossing point and the sampling number will be 0.

2. The method for validating sampled data under a dual-CPU architecture for relay protection according to claim 1, characterized in that, The protection device detects and determines whether the sampled value has been established, including: When N1≥0.04In and N2≥0.04In, it is determined that the sampled value has been established; otherwise, it is determined that the sampled value has not been established. Where N1 and N2 are the fundamental effective values ​​of the sampled values ​​of CPU1 and CPU2, respectively, and In is the rated value of the secondary side of the voltage or current.

3. The method for validating sampled data under a dual-CPU architecture for relay protection according to claim 1, characterized in that, Using the same phase sample value as a synchronization reference, including: Based on the principle of phase voltage priority, the sampling values ​​of phase A, phase B and phase C are detected in real time in sequence; The result of a phase voltage or phase current selected by the main CPU is sent to the slave CPU.

4. The method for validating sampled data under a dual-CPU architecture for relay protection according to claim 1, characterized in that, The first sampling point after the positive zero crossing of this wave is selected, including: Select the first sampling point of this current wave that meets the selection criteria, record the sampled value and number it as 0; The selection criteria are: the current sample value is greater than or equal to 0, and the previous sample value is less than 0.

5. The method for validating sampled data under a dual-CPU architecture for relay protection according to claim 1, characterized in that, The two CPUs exchange sampled values ​​in real time via a high-speed bus with a transmission delay of 1-2ms. The transmitted sampled values ​​are assigned a sample number, which corresponds to the sampled data in the CPU cache.

6. The method for validating sampled data under a dual-CPU architecture for relay protection according to claim 1, characterized in that, Determining whether the sampling of the two CPUs is inconsistent by comparing the deviation of their sampled values ​​includes: Obtain the effective value and instantaneous value of each voltage or current analog sample from the dual CPUs. Based on conditions one and two, it is determined whether the sampling of the two CPUs is inconsistent. When condition one is met for 10ms or condition two is met for 6 out of 10 sampling points, it is determined that the sampling of the two CPUs is inconsistent, and the protection device issues the corresponding alarm information and locks the corresponding protection element. Condition one is: ； In the formula, X1 and X2 are the real-time fundamental effective values ​​of the sampling points of CPU1 and CPU2, respectively, and K1 is the set proportional coefficient; Condition two is: ； In the formula, X3 represents the number of cycles of CPU1. One to The and the first One to The instantaneous value of the sampling point, X4 is the CPU2 sampling point. One to The and the first One to The instantaneous value of each sampling point. K is the number of sampling points per cycle, and K2 is the tuning scaling factor.

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