A universal valve-based electronic device with online repair function

Abstract

The application discloses a general valve-based electronic device with an online maintenance function, which comprises a CPU unit with a redundant configuration, a triggering unit and a back-checking unit with a double-core design. The CPU unit is used for checking data of a control and protection device, receiving control commands and synchronization signals, sending state signals and tripping signals, and sending real-time states of the device and a valve group to a monitoring system. The triggering unit is used for communicating with a TE board in the valve group, sending triggering commands, and realizing control over the valve group. The back-checking unit is used for communicating with the TE board in the valve group, receiving states of the valve group, and realizing monitoring of the valve group. Through the redundant design on the hardware, the triggering pulse logic and the back-checking logic can be adjusted on the software, so that the triggering and control requirements of different power electronic devices are met. Meanwhile, the non-stop maintenance function of the primary system and the secondary system is realized through the test, maintenance and data blocking function design, so that forced outage accidents caused by the damage of single components are avoided.

Description

Technical Field

[0001] This invention belongs to the fields of power system automation and industrial control, and more specifically relates to a general-purpose valve-based electronic device with online maintenance function. Background Technology

[0002] Valve-Based Electronics (VBEs) are the ground control units for thyristor valve assemblies. Any power electronic device based on thyristor valves requires a VBE for monitoring and control. Different types of equipment use the same control method: controlling the thyristor electronic board (TE) to turn on the thyristors by driving their gates at the expected time. The main difference between different manufacturers and equipment lies in the trigger pulse interaction logic. For example, UHVDC transmission systems and SVCs use five-pulse triggering logic, while controllable high-voltage reactors use pulse group triggering logic. Furthermore, their feedback logic is defined according to different equipment manufacturers. These differences in triggering and feedback logic create interface barriers between primary equipment and the VBE. Currently, relevant standards have standardized the interface between VBEs and control and protection systems, but the interface between VBEs and valve assemblies is not yet standardized, leading to the need for customized development for different projects and equipment manufacturers.

[0003] VBE (Voltage Beam Regulator) devices are primarily used for monitoring and controlling valve assemblies. Based on the characteristics of thyristor valve assemblies, each assembly is calculated using multiple thyristors according to the number of regulation stages and the voltage level of each stage, requiring a significant number. As the equipment voltage increases, the number of thyristors connected in series in the valve assembly also increases, making its reliability crucial, especially for power electronic equipment used in power lines. Their operation is dependent on the line's commissioning and decommissioning; every power outage for maintenance requires a corresponding line shutdown. However, currently, most power electronic equipment requires a complete power outage if a single thyristor or its drive circuit fails, significantly impacting equipment availability. A typical valve assembly contains nearly 1000 main components, including thyristors, TE (Transmission Equipment) boards, equalizing capacitors, and equalizing resistors. Although the valve assembly design has a certain margin, and a few component failures do not affect operation, there is still a significant need for live maintenance. According to the relevant requirements for UHV (Ultra-High Voltage) equipment, the failure of a single component cannot force a shutdown of the entire system.

[0004] Since the TE board and VBE channels are in one-to-one correspondence, although the VBE device CPU can achieve redundant design, due to the uniqueness of the trigger and return check channels, the trigger and return check unit is designed as a single system in the past design experience. With this design, it is not possible to achieve true live replacement of the unit under certain operating conditions.

[0005] Low-pressure triggering test is a necessary test to verify the quality of valve group, but the device wiring needs to be changed during the test, and current methods cannot achieve maintenance without power interruption. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention provides a universal valve-based electronic device with online maintenance capabilities. This universal valve-based electronic device is communicatively connected to both a control and protection system and a monitoring system. The universal valve-based electronic device includes a CPU unit, multiple triggering units, and a feedback unit. The CPU unit employs a redundant design. The triggering units and feedback units employ a core redundancy design.

[0007] The back-check unit is used to: receive the status of each TE board detection valve group as a back-check pulse and send it to each CPU unit;

[0008] The CPU unit is used to: generate a trigger pulse based on the received synchronization signal and trigger command of the control and protection system combined with the set trigger logic, and send the trigger pulse to each trigger unit; it is also used to extract the valve group status based on the received return pulses of each return unit, and send the valve group status and the status of the general valve-based electronic device to the monitoring system.

[0009] The triggering unit is used to: receive trigger pulses from each CPU unit and send the trigger pulses to the TE board corresponding to each thyristor in the valve group, thereby realizing the control of the thyristors.

[0010] Preferably, the core of the triggering unit and the return check unit includes: a logic calculation unit;

[0011] The back-check pulse includes encoding the valve group status according to the valve group position.

[0012] Preferably, the trigger pulse includes a pulse identifier, which includes at least one or more of the following: a main system identifier, a backup system identifier, and a device maintenance identifier.

[0013] Preferably, the CPU unit has the following operating modes: running, standby, maintenance, and testing.

[0014] Preferably, when the general-purpose valve-based electronic device is operating normally: one set of CPU units operates in running mode, and the other set of CPU units operates in standby mode, and the operating modes of the one set of CPU units and the other set of CPU units can be switched.

[0015] Preferably, when the operating mode of any CPU unit is maintenance: the CPU unit in maintenance mode sends a blocking logic to any redundant core in the triggering unit and / or any redundant core in the return check unit.

[0016] When the CPU unit receives any data from a locked trigger unit redundant core or a check unit redundant core, it performs a masking process.

[0017] Preferably, when any CPU unit is in test mode: the CPU unit only receives maintenance synchronization signals and control commands, and cooperates with VTE to complete a low-voltage trigger test without changing any wiring.

[0018] Preferably, the core redundancy between each CPU unit and the trigger unit, and the core redundancy between the CPU unit and the return check unit, will send their main system / backup system status to each other; and the main system / backup system adopts a cross-connection method.

[0019] Preferably, the length of both the trigger pulse and the return pulse is one cycle.

[0020] Preferably, the triggering logic is tuned based on the length and meaning of the trigger pulse; the interval, length, triggering logic form, meaning, and related logic of each trigger pulse are defined by parameters;

[0021] The return check command is tuned based on its length and meaning, and the interval in which each return check command appears is defined by parameters.

[0022] Preferably, each CPU unit, trigger unit, and return detection unit communicates with each other via an independent high-speed data bus; the high-speed data bus enables bidirectional data interaction; and each trigger unit and return detection unit is connected to the TE board corresponding to each thyristor in the valve group via an independent optical fiber channel.

[0023] Preferably, the redundancy design employs cross redundancy, and the single-system configuration and redundancy configuration are configurable.

[0024] Preferably, the CPU unit includes: a control and protection system synchronization signal and control interface and a maintenance synchronization signal and control interface; both the control and protection system synchronization signal and control interface and the maintenance synchronization signal and control interface are hardware interfaces; the maintenance synchronization signal and control interface is connected to the valve group low-pressure triggering fixture.

[0025] Preferably, the CPU unit is further configured to: record the status of each module, trigger pulse, and return pulse inside the general valve-based electronic device in real time using a pre-recorded waveform method, and generate a waveform recording file; and then send the recorded waveform file to the monitoring system;

[0026] The waveform recording function is triggered either manually or under certain conditions.

[0027] The waveform recording file is in the standard comtrade format.

[0028] Preferably, the CPU unit includes at least four Ethernet interfaces, each Ethernet interface being configured with a different communication module; the CPU unit communicates with different monitoring systems through the different communication modules.

[0029] Preferably, each phase valve group is equipped with a universal valve base electronic device, and the three-phase universal valve base electronic devices at each stage ensure the consistency of the main system / standby system status and the consistency of control commands through fiber optic verification.

[0030] Preferably, there are no fewer than 72 pairs of interfaces between a single general-purpose valve-based electronic device and the TE board;

[0031] The number of thyristors controlled by the general-purpose valve-based electronic device is set by parameters according to the equipment requirements of different voltage levels.

[0032] Preferably, the universal valve-based electronic device further includes a dual-path independently configured power supply module for supplying power to each unit in the universal valve-based electronic device.

[0033] Preferably, the CPU unit is further configured to: generate a valve group status matrix in real time based on the valve group status and the set return check command, and realize the real-time criterion for valve margin insufficient protection according to the preset valve margin parameters.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] This invention provides a universal valve-based electronic device with online maintenance capabilities, comprising: a CPU unit, a triggering unit, and a feedback unit; the CPU unit adopts a redundant design; the triggering unit and the feedback unit adopt a core redundancy design; on the one hand, its triggering logic and feedback logic can be tuned by parameters, allowing different devices and products to complete data interaction with the valve group simply by tuning parameters; on the other hand, when the device switches to a specific operating condition, it can achieve live maintenance without interruption of operation, and no external cables need to be modified during the maintenance process. Attached Figure Description

[0036] Figure 1 The diagram shown is a structural schematic of the present invention;

[0037] Figure 2 The diagram shown is a schematic of the CPU unit interface of the present invention. Detailed Implementation

[0038] This invention discloses a universal valve-based electronic device with online maintenance capabilities, comprising a CPU unit, a trigger unit connected to the CPU unit via a first high-speed bus, and a feedback unit connected to the CPU unit via a second high-speed bus. The CPU unit verifies data with the control and protection device via an optical fiber interface, receives control commands and synchronization signals, sends status signals and trip signals, and transmits the real-time status of the VBE device and the valve group to the monitoring system via an Ethernet interface. The trigger unit communicates with the TE board in the valve group via optical fiber, sending trigger commands to control the valve group. The feedback unit communicates with the TE board in the valve group via optical fiber, receiving the valve group's status to monitor the valve group. Through hardware features including dual power supply configuration, redundant CPU unit configuration, dual-core design for the trigger and feedback units, and independent dual-system data bus design, the software employs adjustable trigger pulse logic and feedback logic to meet the triggering and control requirements of different power electronic devices. Furthermore, through testing, maintenance, and data blocking functions, it achieves uninterrupted maintenance for both the primary and secondary systems, avoiding forced shutdowns caused by single component failures. To better understand this invention, the following description, in conjunction with the accompanying drawings and examples, will further illustrate the invention.

[0039] Example 1

[0040] This invention provides a universal valve-based electronic device with online maintenance capabilities. This device is communicatively connected to both a control and protection system and a monitoring system. It meets the requirements for high-reliability operation under ultra-high voltage conditions and features uninterrupted maintenance. Specifically, it includes a CPU unit, multiple triggering units, and a feedback unit. The CPU unit employs a redundant design. The triggering and feedback units also feature core redundancy, with the core being a logic calculation unit. Furthermore, the universal valve-based electronic device includes dual independent power supplies. All units are designed according to a standard 6U structure and installed in a 6U chassis. Each unit communicates via an independent bus. A schematic diagram of the device is shown below. Figure 1 As shown.

[0041] The feedback unit is used to: receive the status of each TE board's detection valve group as a feedback pulse and send it to each CPU unit; the feedback pulse here includes: encoding the valve group status according to the valve group position.

[0042] The CPU unit is used for: generating trigger pulses based on the received synchronization signals and trigger commands from the control and protection system, combined with the set trigger logic, and sending the trigger pulses to each core redundancy of the trigger unit; extracting the valve group status based on the received return pulses from each return unit, and sending the valve group status and the status of the general valve-based electronic device to the monitoring system; and generating a valve group status matrix in real time based on the valve group status and the set return commands, and realizing real-time judgment of insufficient valve margin protection according to preset valve margin parameters.

[0043] The trigger pulse includes a pulse identifier, which includes at least one or more of the following: a main system identifier, a backup system identifier, and a device maintenance identifier.

[0044] The transmission interval of CPU status information in the trigger pulse is the non-trigger interval. The trigger unit first parses the CPU status information, determines that the data set is the main system data to be sent, and then clears the CPU status information in the trigger pulse to zero through an AND gate, and sends it through each independent optical fiber channel.

[0045] The triggering unit is used to: receive trigger pulses from each CPU unit and send the trigger pulses to the TE board corresponding to each thyristor in the valve group, thereby realizing the control of the thyristors.

[0046] The trigger logic and return detection logic parameter setting function of the above-mentioned device is that the trigger logic form can be set according to requirements, such as five-pulse trigger logic or pulse group trigger logic, and then the meaning and associated logic, generation interval and pulse width length of each pulse are defined. The return detection logic is also set in this way, and the definition of the return detection interval is realized through parameter setting.

[0047] The control and monitoring functions of the valve group in the aforementioned device are as follows: It receives synchronization signals and control commands from the control and protection device via optical fiber. The synchronization signal is a square wave signal based on a sine wave, and the control command is in the format of an encoding or pulse. The control commands include both triggered and non-triggered types. Upon receiving a triggered command, a trigger pulse is generated at the optimal trigger time, taking into account the optical fiber trigger delay to ensure minimal impact during triggering. Upon receiving a non-triggered command, the pulse only includes inspection information for data interaction with the TE board. The CPU unit simultaneously sends trigger commands to multiple trigger units via an independent data bus. After receiving the commands, the trigger units transmit them to the TE board via independent optical fiber channels, with a transmission period of once every half power cycle. Each inspection unit receives the valve group status detected by the TE board via an independent optical fiber channel and sends the valve group status to the CPU unit. The CPU unit then implements interlocking or tripping based on the valve group status.

[0048] The maintenance function of the aforementioned device is determined by the operating mode of the CPU unit, which includes running, standby, maintenance, and testing. The redundantly configured CPU units operate with one set running and the other on standby during normal operation, allowing for manual switching and automatic switching in case of fault. The main core of the trigger unit only executes commands from the main CPU. When the device is in maintenance mode, it blocks any fault information to prevent fault signals from being sent to the control and protection system during maintenance, thus preventing malfunctions and lockouts. Simultaneously, when a downstream unit receives a maintenance flag, it will not parse the trigger commands of its local system. The testing mode is used for low-pressure triggering tests of the valve assembly. In terms of hardware interfaces, in addition to the synchronization signal and control command interfaces for communication with the control and protection system, the device also has additional synchronization signal and control command interfaces for maintenance. In maintenance mode, by cooperating with low-pressure triggering fixtures, low-pressure triggering functionality can be achieved without any wiring modifications. The CPU unit can respond only to commands from a specific control terminal via switching commands issued by the monitoring system, enabling the switching of remote and local control.

[0049] Specifically:

[0050] When the general-purpose valve-based electronic device is operating normally: one set of CPU units is in operation mode and the other set of CPU units is in standby mode, and the operation modes of the one set of CPU units and the other set of CPU units can be switched.

[0051] When any CPU unit is in maintenance mode: the CPU unit in maintenance mode sends a blocking logic to any redundant core in the triggering unit and / or any redundant core in the return check unit.

[0052] When the CPU unit receives any data from the core of the trigger unit redundancy or the core of the return check unit redundancy, it performs masking processing.

[0053] When any CPU unit is in test mode: the CPU unit only receives maintenance synchronization signals and control commands, and works with VTE to complete a low-voltage trigger test without changing any wiring.

[0054] Here, the core redundancy between each CPU unit and the trigger unit, and the core redundancy between the CPU unit and the return check unit, will send their own main system / backup system status to each other; and the main system / backup system adopts a cross-connection method.

[0055] The aforementioned device employs a semi-redundant structural design, meaning the power supply unit and CPU unit use independent boards, while the triggering unit and feedback unit adopt a dual-core design, thus ensuring redundancy for each unit with logical functions. Its master-slave logic is as follows: the CPU unit, triggering unit, and feedback unit are all cross-connected, with each unit automatically switching between master and slave roles and exchanging master-slave results for verification.

[0056] To ensure effective data blocking during maintenance, each unit is equipped with data transmission blocking and data reception blocking modes. When this mode is activated, other units will assume that the data of this unit is good, but in reality, the data sent to the backend will still be the actual state.

[0057] To achieve full-range monitoring of the entire VEB device's operation at all stages, the device is designed with a real-time waveform recording function. The recorded waveforms include, but are not limited to, trigger pulses, feedback pulses, synchronization signals, control commands, and device status information returned by the triggering unit. The waveform recording function starts immediately upon device startup, recording the device status for the most recent 5 seconds. When the waveform recording condition is triggered, the status for the 5 seconds before and after the trigger time is sent to the monitoring system in comtrade format.

[0058] By adopting the above scheme, in addition to satisfying the monitoring and control functions of valve groups with various topologies and principles, the present invention realizes online maintenance of VBE devices and valve groups through both software design and hardware interface, which meets the reliability requirements of UHV transmission lines, effectively solves the problem of forced equipment shutdown caused by the failure of a single component, and improves the availability of equipment.

[0059] Example 2

[0060] The following is a specific example to illustrate the universal valve-based electronic device with uninterrupted online maintenance provided by this invention.

[0061] The universal valve-based electronic device of this invention has an interface scale that meets the control scale of valve groups at ultra-high voltage levels and above. Simultaneously, its uninterrupted maintenance function meets the requirement that failure of a single component in ultra-high voltage transmission should not cause forced equipment shutdown. The configuration principle of this device is one VBE device per phase valve group. The following detailed explanation of the technical solution of this invention uses a single-stage, single-phase VBE device as an example.

[0062] The structural diagram of the device is shown in Figure 1. A VBE device includes the following components: two independently powered power modules, two redundant CPU units, and multiple dual-core triggering and feedback units. Each triggering and feedback unit is designed with multiple optical channels. The number of triggering and feedback units is determined based on the number of valve layers in the single-phase valve group. The main functions and interfaces of each unit are shown below:

[0063] 1) Power module, used to convert 220V DC to 5V and 24V to power other units. The power supply bus is designed in parallel to ensure that if one line fails, the other line can reliably supply power.

[0064] 2) The CPU unit is used to generate trigger pulses and process the feedback logic. It has multiple fiber optic channels and Ethernet interfaces, and its interface definitions are as follows:Figure 2 As shown, the CPU unit receives control commands and synchronization signals from the control and protection system, control commands and synchronization signals from the low-voltage trigger test fixture, and linkage signals from other phases of the VBE device at this level via a fiber optic interface; it sends trip signals, linkage signals at this level, and VBE device and status signals, and communicates with the monitoring system. The CPU unit performs monitoring and control of the entire device, waveform recording, receiving trigger commands and generating trigger pulses after synchronization signal conditioning, sending them to the trigger unit, receiving valve group status from the return inspection unit, generating interlocking and tripping logic based on valve group status and equipment status, and performing related functions for online maintenance.

[0065] 3) Trigger unit, equipped with multiple fiber optic transmission channels, is used to receive trigger commands from the CPU unit and send them to the TE board through the fiber optic channels.

[0066] 4) The feedback unit has multiple fiber optic feedback channels to receive the status of the TE board and realize the monitoring of the entire valve group.

[0067] The device is designed to meet the functional requirements of ultra-high voltage, high reliability, and online maintenance:

[0068] 1) The hardware interface meets the configuration requirements of the redundant system, with more than 72 communication interfaces with TE, meeting the requirements of the number of valve layers in UHV projects. Each item is equipped with one VBE device, and the number of devices can be configured according to the needs.

[0069] 2) Realize the status monitoring of the entire data channel and logical channel from data reception to data transmission, and realize bidirectional communication between each unit and the status of each unit interact with each other;

[0070] 3) Multiple data encoding formats are adopted, such as square wave, code with check, pulse with check, and frequency signal, to meet different real-time and reliability requirements;

[0071] 4) Redundant system design: For systems where independent units can be implemented in principle, a redundant system with independent units is adopted; for systems where independent units cannot be implemented, a dual-core system is adopted. Each core uses an independent bus to prevent interference. Cross-redundancy is employed, allowing for manual switching or automatic switching in case of failure.

[0072] 5) An independent maintenance hardware interface is set up. In test mode, it can be used with low-voltage trigger test fixtures to perform low-voltage trigger tests on a certain level without changing the wiring.

[0073] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0074] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0076] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0077] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0078] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A universal valve-based electronic device with online maintenance function, characterized in that: The general-purpose valve-based electronic device is communicatively connected to the control and protection system and the monitoring system, respectively; the general-purpose valve-based electronic device includes: a CPU unit, multiple triggering units and a feedback unit; the CPU unit adopts a redundant design; the triggering units and feedback units adopt a core redundancy design; The back-check unit is used to: receive the status of each TE board detection valve group as a back-check pulse and send it to each CPU unit; The CPU unit is used to: generate a trigger pulse based on the received synchronization signal and trigger command of the control and protection system combined with the set trigger logic, and send the trigger pulse to each trigger unit; it is also used to extract the valve group status based on the received return pulses of each return unit, and send the valve group status and the status of the general valve-based electronic device to the monitoring system. The triggering unit is used to: receive trigger pulses from each CPU unit and send the trigger pulses to the TE board corresponding to each thyristor in the valve group, thereby realizing the control of the thyristor; Each CPU unit, trigger unit, and feedback unit communicates with each other via an independent high-speed data bus; bidirectional data interaction is performed on the high-speed data bus; both the trigger unit and the feedback unit are connected to the TE board corresponding to each thyristor in the valve group via independent optical fiber channels; The redundancy design employs cross redundancy, and the configuration of a single system and the redundancy configuration can be tuned; The trigger pulse includes a pulse identifier, which includes at least one of the following: a main system identifier, a backup system identifier, and a device maintenance identifier; The CPU unit has the following operating modes: running, standby, maintenance, and testing.

2. The universal valve-based electronic device as described in claim 1, characterized in that, The core of the triggering unit and the return check unit includes: a logic calculation unit; The back-check pulse includes encoding the valve group status according to the valve group position.

3. The universal valve-based electronic device as described in claim 1, characterized in that, When the general-purpose valve-based electronic device is operating normally: one set of CPU units operates in running mode, and the other set of CPU units operates in standby mode, and the operating modes of the one set of CPU units and the other set of CPU units can be switched.

4. The universal valve-based electronic device as described in claim 1, characterized in that, When any CPU unit is in maintenance mode: the CPU unit in maintenance mode sends a blocking logic to any redundant core in the triggering unit and / or any redundant core in the return check unit. When the CPU unit receives any data from a core of a locked trigger unit or a core of a check unit, it performs a masking process.

5. The universal valve-based electronic device as described in claim 1, characterized in that, When any CPU unit is in test mode: the CPU unit only receives maintenance synchronization signals and control commands, and works with VTE to complete a low-voltage trigger test without changing any wiring.

6. The universal valve-based electronic device as claimed in claim 1, characterized in that, The length of both the trigger pulse and the return pulse is one cycle.

7. The universal valve-based electronic device as claimed in claim 1, characterized in that, The CPU unit includes: a control and protection system synchronization signal and control interface and a maintenance synchronization signal and control interface; both the control and protection system synchronization signal and control interface and the maintenance synchronization signal and control interface are hardware interfaces; the maintenance synchronization signal and control interface is connected to the valve group low-pressure triggering fixture.

8. The universal valve-based electronic device as claimed in claim 1, characterized in that, The CPU unit is also used to: record the status of each module, trigger pulse, and return pulse inside the general valve-based electronic device in real time using a pre-recorded waveform method, and generate a waveform file; and then send the waveform file to the monitoring system. The pre-recorded waveform function is triggered either manually or under certain conditions. The waveform recording file is in the standard comtrade format.

9. The universal valve-based electronic device as claimed in claim 1, characterized in that, The CPU unit includes at least four Ethernet interfaces, each configured with a different communication module; the CPU unit communicates with different monitoring systems through the different communication modules.

10. The universal valve-based electronic device as claimed in claim 1, characterized in that, Each phase valve group is equipped with a universal valve base electronic device. The three-phase universal valve base electronic devices at each stage ensure the consistency of the main system / standby system status and control commands through fiber optic verification.

11. The universal valve-based electronic device as claimed in claim 1, characterized in that, The interface between a single general-purpose valve-based electronic device and the TE board shall not be less than 72 pairs; The number of thyristors controlled by the general-purpose valve-based electronic device is set by parameters according to the equipment requirements of different voltage levels.

12. The universal valve-based electronic device as claimed in claim 1, characterized in that, The general-purpose valve-based electronic device also includes dual independently configured power supply modules for supplying power to each unit in the general-purpose valve-based electronic device.

13. The universal valve-based electronic device as claimed in claim 1, characterized in that, The CPU unit is also used to: generate a valve group status matrix in real time based on the valve group status and the set return check command, and realize the real-time judgment criterion for valve margin insufficient protection according to the preset valve margin parameters.

14. The universal valve-based electronic device as claimed in claim 13, characterized in that, The triggering logic is tuned based on the length and meaning of the trigger pulse; the interval, length, triggering logic form, meaning, and associated logic of the trigger pulse are defined by parameters. The return check command is tuned based on its length and meaning, and the range in which the return check command appears is defined by parameters.

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