Apparatus, system and method for address translation

Abstract

The present disclosure relates to address translation. Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address in the memory device that corresponds to a target untranslated address, an index in the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to apparatus and methods related to address translation. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications. Non-volatile memory can be used in, for example, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players and video players, and other electronic devices. Memory cells can be arranged in arrays, which are used in memory devices. Summary of the Invention

[0004] According to one aspect of this disclosure, an apparatus for address translation is provided. The apparatus includes: a first control circuitry system configured to provide a page identifier (PID) and a queue identifier (QID) for a request for a translated address corresponding to a target untranslated address in a memory device 130; a second control circuitry system configured to store a plurality of translated addresses of the memory device in a lookup table (LUT) acting as an address translation cache (ATC); and an interface component coupled to the first and second control circuitry systems and configured to: map the requested PID and QID to an identifier (LUT ID) of the LUT; and provide the LUT ID to the second control circuitry system to identify a specific translated address corresponding to the target untranslated address.

[0005] According to another aspect of this disclosure, a method for address translation is provided. The method includes: storing a plurality of translated addresses of a memory device in a first lookup table (LUT) maintained by a control circuitry system; storing a plurality of untranslated addresses in a second LUT maintained by the control circuitry system; and, in response to a translation request for a specific translated address in the memory device corresponding to a target untranslated address: determining an index in the second LUT associated with the target untranslated address; mapping the index of the second LUT to an index of the first LUT to verify that the specific translated address corresponds to the target untranslated address; and retrieving the specific translated address corresponding to the target untranslated address from the first LUT.

[0006] According to another aspect of this disclosure, a non-transitory medium is provided. The medium stores instructions for address translation, the instructions being executable by a processing device to: receive a translation request comprising an index in a first lookup table (LUT) corresponding to a corresponding target untranslated address; and map the index of the first LUT to an index of a second LUT storing a translated address of a storage memory device, wherein the index of the first LUT is associated with a specific translated address in the memory device corresponding to the target untranslated address.

[0007] According to another aspect of this disclosure, a system for address translation is provided. The system includes: a host system including processing means; and a memory system coupled to the host system and including: a local controller of the memory device configured to maintain a first lookup table (LUT) having corresponding untranslated addresses of the memory device; a memory system controller configured to maintain a second LUT for the untranslated addresses; and an interface component coupled to the memory system controller and the local controller, wherein the interface component is configured to map an index in the second LUT associated with a target untranslated address to an index in the first LUT to translate the target untranslated address into a specific translated address of the memory device, wherein the second LUT is configured to be populated by the host system. Attached Figure Description

[0008] Figure 1 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

[0009] Figure 2 This is a block diagram of a memory system controller and a local controller of a device according to several embodiments of the present disclosure.

[0010] Figure 3This is a block diagram representation of address translation according to several embodiments of the present disclosure.

[0011] Figure 4 Example flowcharts illustrating methods for address translation according to several embodiments of the present disclosure. Detailed Implementation

[0012] This disclosure includes apparatus and methods related to address translation. As used herein, "address translation" refers to determining the physical address (e.g., physical block address, physical media location) of a memory (e.g., memory die, memory bank) corresponding to a logical address (e.g., logical block address (LBA), namespace) of a memory device. Address translation may involve the use of an address translation cache (ATC). Some prior methods of address translation have used content-addressable memory (CAM) (e.g., fully associative cache) as an ATC. However, CAMs may have limited capacity. For example, a CAM may be able to store up to one thousand (1K) entries. The gate count of a CAM may be too high for implementing a CAM as an ATC to be practical. Set-associated caches cannot be used as ATCs because typically only the host device can invalidate entries in an ATC.

[0013] The memory control circuitry of the memory device can conform to the Non-Volatile Memory Fast (NVMe) specification. An NVMe module can have a finite number of queues, each with a finite number of pages. The ATC protocol can be executed at a relatively low frequency. Embodiments of this disclosure address the aforementioned shortcomings and other deficiencies of prior methods by using a lookup table (LUT) to store translated addresses. As used herein, an "untranslated address" refers to the logical address associated with a data value stored in the memory device. As used herein, a "translated address" refers to the physical address of the memory device storing the data value. Therefore, the translated address corresponding to the untranslated address is the physical address corresponding to the logical address.

[0014] Compared to previous methods that use untranslated addresses to look up and retrieve corresponding translated addresses from a CAM, at least one embodiment uses an index of a LUT, hereinafter referred to as a LUT ID, to look up and retrieve the corresponding translated address from the CAM. As described herein, in response to a translation request, a LUT ID can be allocated from a pool of free LUT IDs. The allocated LUT ID can be stored in another LUT. The translation request may contain an index of this other LUT, through which the allocated LUT ID can be obtained. It should be noted that a translation request does not necessarily imply that the untranslated address associated with the translation request has not previously been translated.

[0015] According to this disclosure, the ATC can make translation requests unilaterally on behalf of the NVMe control circuitry. Therefore, the NVMe control circuitry does not need to know about Address Translation Service (ATS) support. The ATC can make translation requests for untranslated addresses of memory pages that have not yet been translated in response to memory requests (e.g., Advanced Extensible Interface (AXI) memory requests).

[0016] For example, the initial memory request for a data page is associated with an untranslated address, which offers no benefit for a Physical Region Page (PRP) memory request, as a PRP memory request occurs only once. Therefore, the NVMe control circuitry performs translation requests before issuing PRP memory requests to hide and / or reduce address translation latency, while the ATC performs translation requests for other types of memory (e.g., 3DXP, NAND) to improve overall system performance, for example.

[0017] According to this disclosure, the ATC can store the translated address in a LUT. When a translation request is made via the ATC, a location in the LUT for storing the translated address is allocated, indicated by a LUTID. Each LUTID is associated with an untranslated address and its corresponding translated address. According to this disclosure, the LUT IDs described herein are ATC-specific. Therefore, the NVMe control circuitry does not need to know the LUT IDs.

[0018] The ATC according to this disclosure can be used in applications other than NVMe control circuitry. At least one embodiment of this disclosure may include an interface component. The interface component may include hardware (e.g., circuitry), firmware, software, and combinations thereof. The interface component may be an NVMe-specific component or a component separate from the NVMe control circuitry, protecting the NVMe control circuitry from the address translation operations of the ATC. The interface component can map untranslated addresses to LUT IDs. Since memory pages conforming to the NVMe specification can be associated with PRP queues or MSI-X queues, another LUT of the interface component does not require a fully associated cache. The index, queue identifier (QID), and page identifier (PID) of the LUT of the interface component can be used to map untranslated addresses to LUT IDs. Subsequently, the LUT IDs can be mapped to the corresponding translated addresses.

[0019] As used herein, unless expressly indicated otherwise, the singular forms “a / an” and “the” include both single and multiple indicators. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., possible, able) rather than in a mandatory sense (i.e., must). The term “comprising” and its derivatives mean “including but not limited to”. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0020] The figures in this document follow a numbering convention, where the first one or more numbers correspond to the figure number, and the remaining numbers identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, element 115 could represent... Figure 1 Component 15, and similar components may be used. Figure 2 The symbol is 215. Hyphens and additional numbers or letters may be used to refer to similar elements within the figures. As will be understood, elements shown in the various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0021] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory system 110, according to some embodiments of the present disclosure. The memory system 110 may include media, such as one or more volatile memory devices 140, one or more non-volatile memory devices 130, or a combination thereof.

[0022] The memory system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module, as well as other types of memory systems. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing device.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory systems 110. In some embodiments, the host system 120 is coupled to different types of memory systems 110. Figure 1 This describes an instance of a host 120 coupled to a memory system 110.

[0025] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect (PCIe) interface controller, a SATA controller). Host system 120 may write data to and / or read data from memory devices 130, 140 of memory system 110.

[0026] Host system 120 can be coupled to memory system 110 via a physical host interface (not shown). Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory system 110. When memory system 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVMe interface to access components. The physical host interface provides an interface for transferring control, address, data, and other signals between memory system 110 and host system 120. Figure 1 The memory system 110 is described as an example. Generally, the host system 120 can access multiple memory systems 110 via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] Non-volatile memory device 130 and volatile memory device 140 may each comprise various combinations of different types of non-volatile memory devices and volatile memory devices. Some examples of volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory include NAND flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in bulk resistance by combining stackable cross-grid data access arrays. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] The non-volatile memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, the non-volatile memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as MLC, TLC, QLC, or PLC portions. The memory cells of the non-volatile memory device 130 may be grouped into pages, which may refer to logical units of a corresponding memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] While non-volatile memory components such as a three-dimensional cross-point array of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) and NAND-type memories are described, non-volatile memory 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory system controller 115 can communicate with memory devices 130 and 140 to perform operations such as reading data, writing data, and / or erasing data stored on non-volatile memory devices 130 and volatile memory devices 140, and other such operations. The memory system controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory system controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory system controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory system 110, including handling communication between the memory system 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although memory system 110 is described as including memory system controller 115, in another embodiment of this disclosure, memory system 110 does not include memory system controller 115 and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory system) to access memory devices 130, 140.

[0034] Generally, the memory system controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform desired access to the non-volatile memory device 130 and / or the volatile memory device 140. The memory system controller 115 may be responsible for other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between untranslated addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the non-volatile memory device 130. The memory system controller 115 may further include host interface circuitry for communication with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system 120 into command instructions to access the non-volatile memory device 130 and / or the volatile memory device 140, and convert responses associated with the non-volatile memory device 130 and / or the volatile memory device 140 into information for the host system 120.

[0035] The memory system 110 may also include additional circuitry or components not described. In some embodiments, the memory system 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory system controller 115 to access non-volatile memory device 130 and / or volatile memory device 140.

[0036] In some embodiments, a memory device (e.g., non-volatile memory device 130) may include a local controller 135 that operates in conjunction with a memory system controller 115 to perform operations on one or more memory cells of the non-volatile memory device 130. An external controller (e.g., memory system controller 115) may externally manage the non-volatile memory device 130 (e.g., perform media management operations on the non-volatile memory device 130). In some embodiments, the non-volatile memory device 130 may be managed memory. Managed memory is raw memory combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] Memory system 110 may include address translation component 113. Although Figure 1Not shown, but address translation component 113 may include circuitry to facilitate address translation. A LUT (Local Underlying Unit) with a translated address of storage memory system 110 may reside on address translation component 113. In some embodiments, address translation component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry, enabling address translation component 113 to receive a LUTID from local memory controller 135 and retrieve, for example, the translated address associated with the LUTID from a LUT. In some embodiments, memory system controller 115 includes at least a portion of address translation component 113. For example, memory system controller 115 may include processor 117 (e.g., processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0038] Memory system 110 may include an interface component 152 coupled to memory system controller 115 and local controller 135 to facilitate address translation. Different LUTs may reside on the interface component 152, which stores LUT IDs of LUTs residing on address translation component 113. In some embodiments, interface component 152 may include a dedicated circuit system in the form of an ASIC, FPGA, state machine, and / or other logic circuitry. The LUTs of interface component 152 may be indexed by a page identifier (PID) and a queue identifier (QID). Interface component 152 may receive a translation request for a target untranslated address from local controller 135. The translation request may include a PID and QID associated with the target untranslated address. Interface component 152 may receive the PID and QID and retrieve the LUT ID from the LUT residing on interface component 152. Interface component 152 may transmit the retrieved LUT ID to address translation component 113. Address translation component 113 can then translate the target untranslated address by retrieving the translated address corresponding to the target untranslated address from the LUT residing on address translation component 113, as described herein.

[0039] Figure 2 This is a block diagram of a memory system controller 215 and a local controller 235 of a device according to several embodiments of the present disclosure. The memory system controller 215 and the local controller 235 may be similar to... Figure 1 The memory system 110 described in association includes a memory system controller 115 and a local controller 135. Figure 2 This describes the circuitry and components of the memory system involved in address translation according to this disclosure. However, Figure 2 This disclosure is not intended to exclude embodiments of the memory system from including other circuit systems and components.

[0040] As by Figure 2The memory system controller 235 may issue a translation request 251. The translation request 251 may contain one or more target untranslated addresses, and a PID and QID associated with each target untranslated address. The value of the QID indicates the type of memory page. The value of the PID indicates a specific (e.g., target) memory page of the type indicated by the QID. The memory system controller 235 may comply with the NVMe specification.

[0041] Interface component 233 may receive a translation request 251 from local memory controller 235. Interface component 252 may maintain a LUT storing LUT IDs of different LUTs maintained by local controller 215. Interface component 252 may map the QID and PID of translation request 251 to LUT IDs. The LUTs maintained by interface component 252 are indexed by QID and PID. Interface component 252 may retrieve the LUT ID from the LUT at the location associated with the PID and QID. Interface component 252 may transmit a translation request 249 to memory system controller 215. Translation request 249 contains the target untranslated address. The response to translation request 249 contains the LUT ID.

[0042] The memory system controller 215 can receive a conversion request 249. As described herein and by Figure 2 The memory system controller 215 can maintain a LUT (Local Unified Address) that acts as an ATC (Automatic Translater) 250. The LUT (ATC 250) stores the translated address indexed by the LUT ID. The memory system controller 215 can retrieve the translated address from the LUT at the location associated with the LUT ID of the translation request 249.

[0043] The translated address can be transmitted from the memory system controller 215 to the host interface 259 and / or the local controller 235. The local memory controller 235 can transmit read and / or write requests from the host. The local memory controller 235 can transmit MSI-X requests from the ATC 250. The host interface 259 may comply with the PCIe specification. Although... Figure 2 The host interface 259 is described as separate from the memory system controller 215, but in some embodiments, the host interface 259 and the memory system controller 215 may be part of a single component.

[0044] The dashed line 256 indicates a cross-clock domain. For example, in... Figure 2As indicated at locations 255 and 257, the local controller 235 and the memory system controller 215 can operate according to their respective different clocks. For example, the frequency of the clock for the local controller 235 (e.g., 500 MHz) may differ from the frequency of the clock for the local controller 215 (e.g., 250 MHz). The interface component 252 facilitates communication between the local controller 235 and the memory system controller 215, despite the different clocks.

[0045] As in Figure 2 As indicated at locations 254 and 258, the local controller 235 and the memory system controller 215 can support correspondingly different bandwidths. For example, the local controller 235 can support 512 megabytes (MB) of bandwidth, while the memory system controller 215 can support 256 MB of bandwidth. Interface component 252 facilitates communication between the local controller 235 and the memory system controller 215, despite the different bandwidths.

[0046] Figure 3 This is a block diagram representation of address translation according to several embodiments of the present disclosure. The host system 320 and interface component 352 may be similar to... Figure 1 The host system 120 and interface component 152 are described in association. Figure 3 A block diagram illustrating the address translation between the host system 320 and the interface component 352, as well as the related operations performed by the memory system controller 315.

[0047] Before ATC transmits the translation request to host system 320, ATC first searches a hash-based search table, where the LUT ID corresponds to the translation request. The hash-based search table includes a header table 371, a linked list 372, and an untranslated address table (…). Figure 3 (Not shown in the table). If the ATC search results in a hit, the corresponding LUT ID is returned to interface component 352. If the ATC search results in a miss, a LUT ID is allocated from the LUT ID free pool 369. The allocated LUT ID is then transmitted to interface component 352 and inserted into the search table.

[0048] The execution of the conversion request function 365 may involve the use of different data structures, such as one or more of the following: a free pool of LUT IDs 369, a hash table 370 consisting of a header table 371 and a linked list 372, an unconverted address table 365 (UNT.A.LUT), and a free pool of requester identifiers (RIDs). Figure 3(Not shown in the image). The RID identifies which memory bank of the memory device the untranslated address or target address corresponds to. Head table 371 records the initial LUTIDs of the list of untranslated addresses. Linked list 372 records additional LUTIDs of the list of untranslated addresses. The length of linked list 372 is variable.

[0049] In some embodiments, the RID may be a RID on the AXI bus. After the ATC transmits a translation request to the host system 320 via the memory system controller 315 (e.g., a PCIe controller), the memory system controller 315 transmits the translated address to the ATC via the AXI bus. The ATC stores the translated address in the translated address table 366. The ATC uses the RID of the AXI bus to index the RID-to-LUT ID table 376 to obtain the LUT ID. The RID is allocated before the ATC transmits the translation request to the host system 320, so that the LUT ID can be stored in the RID-to-LUT ID table 376.

[0050] In some embodiments, the local memory controller ( Figure 3 (Not shown) Supports a multi-function memory system controller. The translation request function 361 may include using an untranslated address (e.g., target untranslated address 363) and a function identifier (FID) to look up a LUT ID 364 associated with the untranslated address in hash table 370. If the lookup in hash table 370 results in a match, then at 373, LUT ID 364 is sent back to interface component 352 as a valid LUT ID. If the lookup in hash table 370 results in a miss, then LUT ID 374 is allocated from the free pool of LUT IDs 369. At 373, the allocated LUT ID 374 is sent to interface component 352. The allocated LUT ID 374 is inserted into hash table 370. The untranslated address and its associated QID, PID, and FID are inserted into untranslated address table 365. Subsequently, at 373, the LUT ID is transmitted to interface component 352 for a translation request, an RID is allocated from the RID free pool, and a translation request message is generated. The translation request message can be sent to the PCIe core of memory system controller 315. Untranslated addresses 364 can be incremented, and the steps described herein can be repeated to translate multiple untranslated addresses.

[0051] The execution of the translation completion function 375 may involve using different data structures, such as one or more of the following: a free pool 369 for LUT IDs, a hash table 370, an untranslated address table 365, a free pool for RIDs, an RID-to-LUTID table 376, and a translated address table 366 (TALUT). Executing the translation completion function 375 may involve using the RID from the RID-to-LUTID table 376 to look up the LUT ID using the RID from the read data bus (e.g., an AXI read data bus). The memory system controller 315 may then release the RID back to the free pool of RIDs. The memory system controller 315 may write the translated address 377 and associated attributes (e.g., untranslated, readable, writable, non-monitored) to the translated address table 366 at the location indexed by the LUT ID 364.

[0052] If a translation completion error occurs (e.g., received from the AXI bus), the memory system controller 315 can remove LUTID 364 from hash table 370 and return LUTID 364 to the LUTID free pool 369. All of this can be written to an entry in the untranslated address table 365 indexed by LUTID 364. The untranslated address 363 and its associated QID can then be transmitted to interface component 352.

[0053] The execution of the invalidation request function 362 may involve using different data structures, such as one or more of the following: a free pool 369 for LUT IDs, a hash table 370, an untranslated address table 365, a free pool for RIDs, an RID-to-LUT ID table 376, and a translated address table 366. Executing the invalidation function 362 may involve looking up the corresponding LUT ID in hash table 370 using an untranslated address (e.g., target untranslated address 368) and the FID of the invalidation request message (received from host system 320). If the lookup in hash table 370 results in a match, the resulting LUT ID 367 is returned to the free pool 369 for LUT IDs, and the entry in translated address table 366 indexed by LUT ID 367 is invalidated. If the lookup in hash table 370 results in a miss, an error condition exists.

[0054] The memory system controller 315 can verify that the QID and PID received from the interface component 352 correspond to the corresponding target untranslated address. At 378, the interface component 352 can transmit the LUTID and LUTID as a valid indication (ID valid) as a sideband signal on the address path to the memory system controller 315. If the ID valid signal is devalidated, then no address table lookup will occur. Otherwise, the LUT ID is used to look up the corresponding translated address from the translated address table 366 and the untranslated address table 365. If the LUT ID is valid, and the untranslated address and FID of the interface component 352 match the untranslated address table 365 (at AND 379), then at the multiplexer 380, the corresponding translated address in the translated address table 366 is used. Otherwise, at the multiplexer 380, the corresponding untranslated address 381 is transmitted to the PCIe core of the memory system controller 315.

[0055] If the LUT ID is invalid, and the untranslated address and FID of interface component 352 match the untranslated address table 365 (at AND 379), then at 382, ​​the untranslated address and associated QID and PID (read from the untranslated address table 365) are transmitted to interface component 352. Interface component 352 can then decide whether to reissue the translation request. If the LUT ID is valid, but the untranslated address and FID of interface component 352 do not match the untranslated address table 365 (at AND 379), then at 382, ​​the untranslated address and associated QID and PID (read from the untranslated address table 365) are transmitted to interface component 352.

[0056] In some embodiments, LUTIDs can be actively deprecated. Only the host system 320 has the authority to invalidate LUT IDs. Therefore, if the host system 320 does not frequently invalidate LUT IDs, then the local memory controller (not controlled by...) Figure 3 (Note: For example, local controller 135) LUT IDs that are no longer needed can still be stored by memory system controller 315. Memory system controller 315 can maintain a record of LUT IDs that have been allocated to memory pages that can benefit from active discarding (e.g., in a first-in, first-out (FIFO) manner). When the number of available LUT IDs in free pool 369 falls below a threshold, the LUT IDs stored in the FIFO can become invalid, as described herein. When a LUT ID has been actively discarded, an invalidation completion message is sent.

[0057] Figure 4Example flowcharts illustrate a method 490 for address translation according to several embodiments of the present disclosure. Method 490 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 490 is performed by... Figure 1 The memory system controller 115 and local controller 135 described in association execute the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0058] At block 491, method 490 may include storing a plurality of translated addresses of a memory device in a first LUT maintained by a control circuitry system. Storing the plurality of translated addresses may include storing the plurality of translated addresses in the first LUT maintained by a first portion of the control circuitry system.

[0059] At block 492, method 490 may include storing a plurality of untranslated addresses in a second LUT maintained by a control circuitry system. Storing the plurality of untranslated addresses may include storing the plurality of untranslated addresses in the second LUT maintained by a second portion of the control circuitry system.

[0060] At block 493, method 490 may include, in response to a translation request for a specific translated address in a memory device corresponding to a target untranslated address, determining at block 494 an index of a second LUT associated with the target untranslated address, mapping the index of the second LUT to an index of a first LUT at block 495, and retrieving at block 496 the specific translated address corresponding to the target untranslated address from the first LUT.

[0061] although Figure 4 Unless otherwise specified, method 490 may include, in association with a translation request, receiving an index of a second LUT from a first portion of the control circuitry system via an interface component of a memory system including memory devices. The interface component may map the index of the second LUT to an index of a first LUT and transmit the index of the first LUT to a second portion of the control circuitry system. Method 490 may include performing operations on data stored at the specific translated address via the second portion of the control circuitry system.

[0062] In some embodiments of this disclosure, the computer system (e.g., with) Figure 1 The associated computing system 100 is a machine within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. A computer system machine includes, is coupled to, or utilizes a memory system (e.g., memory system 110). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, possessing the capabilities of a server or client machine in a client-server network environment.

[0063] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions that will take a specified action by said machine. Furthermore, although a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0064] In some embodiments, a computer system may include a processing device, a main memory (e.g., a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static memory (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system, which communicate with each other via a bus.

[0065] The processing device may be one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. The processing device may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. The processing device may be configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include network interface devices for communication via a network.

[0066] Data storage systems may include machine-readable storage media (also known as computer-readable media) on which one or more sets of instructions or software embodying any one or more of the methods or functions described herein are stored. The instructions may also reside wholly or at least partially in main memory and / or processing apparatus during execution by a computer system, which also constitute machine-readable storage media. The term "machine-readable storage media" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage media" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage media" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0067] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description has been carried out in an illustrative rather than restrictive manner. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents granted by those claims.

[0068] In the foregoing detailed description, various features have been grouped together in a single embodiment for the purpose of simplification. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is an independent embodiment.

Claims

1. A device for address translation, comprising: A first control circuit system (115, 215, 315) is configured to provide a page identifier PID for a request in the memory device (130) for a translated address corresponding to a target untranslated address and a first identifier having a value indicating the type of the memory page; The second control circuit system (135, 235) is configured to store multiple translated addresses of the memory device in a lookup table LUT that acts as an address translation cache (ATC) (250); as well as Interface components (152, 252, 352), coupled to the first control circuit system and the second control circuit system, and configured to: Map the PID and the first identifier of the request to the identifier LUT ID of the LUT; as well as The LUT ID is provided to the second control circuitry system to identify a specific translated address corresponding to the target untranslated address.

2. The device according to claim 1, wherein the second control circuit system (135, 235) is further configured to: Determine whether the LUT ID is stored in the hash-based search table of the second control circuit system; In response to determining that the LUT ID is stored in the hash-based search table, the LUT ID is provided to the interface component (152, 252, 352); as well as In response to determining that the LUT ID is not stored in the hash-based search table, another LUT ID is assigned, the assigned LUT ID is provided to the interface component, and the assigned LUT ID is inserted into the hash-based search table.

3. The device according to claim 1, wherein the first control circuit system (115, 215, 315) includes a memory system control circuit system of a memory system (110), the memory system including the memory device (130), and The second control circuit system (135, 235) includes the local control circuit system of the memory device.

4. The device of claim 1, wherein the second control circuitry (135, 235) is further configured to determine the specific translated address corresponding to the LUT ID to translate the target untranslated address.

5. The device according to claim 1, wherein the first control circuit system (115, 215, 315) operates at a first clock frequency (257), and The second control circuit system (135, 235) operates at a second clock frequency (255) that is different from the first clock frequency.

6. The device according to claim 1, wherein the first control circuit system (115, 215, 315) has a first bandwidth (258), and The second control circuit system (135, 235) has a second bandwidth (254) that is different from the first bandwidth.

7. A method for address translation, comprising: Multiple translated addresses of the memory device (130) are stored (491) in a first lookup table (LUT) maintained by the control circuitry system; Multiple untranslated addresses are stored (492) in a second LUT maintained by the control circuitry system; and In response (493) to a translation request for a specific translated address in the memory device corresponding to the target untranslated address: Determine (494) the index in the second LUT associated with the untranslated address of the target; Map the index of the second LUT (495) to the index of the first LUT to verify that the specific translated address corresponds to the target untranslated address; as well as Retrieve (496) from the first LUT the specific translated address corresponding to the target untranslated address.

8. The method of claim 7, wherein storing (492) the plurality of translated addresses comprises storing the plurality of translated addresses in the first LUT maintained by the first part of the control circuitry system. Storing the plurality of untranslated addresses includes storing the plurality of untranslated addresses in a second LUT maintained by a second part of the control circuit system. The method further includes, in association with the conversion request: The index of the second LUT is received from the first part of the control circuit system via an interface component (152, 252, 352) of a memory system (110) including the memory device (130); The interface component maps the index of the second LUT to the index of the first LUT. as well as The index of the first LUT is transmitted from the interface component to the second part of the control circuit system.

9. The method of claim 8, further comprising performing an operation on data stored at the particular translated address via the second part of the control circuitry system.

10. A non-transitory medium storing instructions for address translation, the instructions being executable by a processing device to: Receive a translation request containing the index in the first lookup table (LUT) corresponding to the corresponding untranslated target address; and The index of the first lookup table LUT is mapped to the index of a second LUT of a translated address in the storage memory device (130), wherein the index of the first lookup table LUT is associated with a specific translated address in the storage device corresponding to the target untranslated address.

11. The medium of claim 10, further storing instructions executable to perform the following operations: The conversion request is received at a first data rate based on a first clock (257) of a memory system (110) including the memory device (130); and Based on the second clock (255) of the memory device, the index identifying the specific translated address in the second LUT is transmitted to the control circuitry (135, 235) of the memory device at a second data rate. The second data rate is different from the first data rate.

12. The medium of claim 10, further storing instructions capable of executing to verify that the received index of the first lookup table (LUT) corresponds to the corresponding target untranslated address.

13. A system for address translation, comprising: The host system (120) includes a processing unit; as well as Memory system (110), coupled to the host system and comprising: The local controller (135, 235) of the memory device (130) is configured to maintain a first lookup table (LUT) for a plurality of translated addresses of the memory device with corresponding untranslated addresses; Memory system controllers (115, 215, 315), configured to maintain a second LUT with untranslated addresses; and Interface components (152, 252, 352) are coupled to the memory system controller and the local controller. The interface component is configured to map the index in the second LUT associated with the target untranslated address to the index in the first lookup table LUT, thereby converting the target untranslated address into a specific translated address of the memory device. The second LUT is configured to be populated by the host system.

14. The system of claim 13, wherein the local controller (135, 235) conforms to the Non-Volatile Memory Fast NVMe specification, and The memory system controllers (115, 215, 315) therein comply with the PCIe specification for peripheral component interconnection.

15. The system of claim 13, wherein the host system (120) is configured to have unique authority to invalidate or modify entries of the second LUT.

16. The system of claim 13, wherein the interface components (152, 252, 352) are further configured to provide the specific translated address to the local controller (135, 235), and The local controller is further configured to perform read, write, or erase operations on the data stored at the specific translated address.

17. The system of claim 13, wherein the host system (120) is configured to issue commands to the memory system (110) to perform read, write, or erase operations on data associated with the target untranslated address, and The memory system is only responsible for converting the target untranslated address to the specific translated address.

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