Data packet transmission method, scheduling management unit, chip and display card

Abstract

The embodiment of the present application provides a data packet transmission method, a scheduling management unit, a chip and a display card. The data packet transmission method comprises the following steps: determining a source node and a target node of a to-be-transmitted data packet; determining at least one intermediate routing node corresponding to the to-be-transmitted data packet according to the source node and the target node of the to-be-transmitted data packet and data transmission states of nodes in an on-chip network; and sending identification information of the at least one intermediate routing node to the source node of the to-be-transmitted data packet, so that the source node of the to-be-transmitted data packet writes the identification information of the at least one intermediate routing node into a head flit of the to-be-transmitted data packet, and the to-be-transmitted data packet reaches the target node of the to-be-transmitted data packet after being transmitted to each intermediate routing node in turn according to an XY routing algorithm. The present scheme can improve the transmission efficiency of data packets.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a data packet transmission method, a scheduling management unit, a chip, and a graphics card. Background Technology

[0002] Network on Chip (NoC) connects multiple nodes on a single chip, enabling reliable communication between them. A node includes a Process Element (PE) and a router. The Process Element includes hardware resources such as a processor, Dynamic Random Access Memory (DRAM), private cache, and network interface. NoC topologies include mesh networks, torus networks, and ring networks. Nodes communicate by transmitting data packets. Data packets are sent from a source node and transmitted from one node to another until they reach the destination node.

[0003] Currently, when nodes transmit data packets through the on-chip network, they transmit data packets based on the XY routing algorithm. After the data packet is sent from the source node, it is first transmitted along the X-dimensional direction to the node in the same column as the target node, and then transmitted along the Y-dimensional direction to the target node.

[0004] However, in on-chip networks, data packets are transmitted between connected nodes in the form of data streams. If multiple data packets need to be transmitted from one node to another connected node, each data packet needs to be transmitted sequentially, which can lead to data congestion and low data packet transmission efficiency. Summary of the Invention

[0005] In view of this, embodiments of this application provide a data packet transmission method, a scheduling management unit, a chip, and a graphics card to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a data packet transmission method applied to a scheduling management unit is provided, comprising: determining a source node and a destination node of a data packet to be transmitted; determining at least one intermediate routing node corresponding to the data packet to be transmitted based on the source node and destination node of the data packet to be transmitted and the data transmission status of each node in the on-chip network; sending the identification information of the at least one intermediate routing node to the source node of the data packet to be transmitted, so that the source node of the data packet to be transmitted writes the identification information of the at least one intermediate routing node into the header micro-chip of the data packet to be transmitted, so that the data packet to be transmitted is transmitted sequentially to each of the intermediate routing nodes according to the XY routing algorithm and then reaches the destination node of the data packet to be transmitted.

[0007] According to a second aspect of the embodiments of this application, a data packet transmission method applied to nodes in an on-chip network is provided, comprising: obtaining a header micro-piece of a data packet to be transmitted, wherein the header micro-piece stores identification information of at least one intermediate routing node, the at least one intermediate routing node being determined based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network; transmitting the data packet to be transmitted to the intermediate routing nodes according to the identification information of each intermediate routing node stored in the header micro-piece, and transmitting the data packet to be transmitted to the intermediate routing nodes according to an XY routing algorithm, so that the data packet to be transmitted passes through each intermediate routing node sequentially and arrives at the destination node.

[0008] According to a third aspect of the embodiments of this application, a scheduling management unit is provided, comprising: a reading subunit, configured to determine the source node and the destination node of a data packet to be transmitted; a planning subunit, configured to determine at least one intermediate routing node corresponding to the data packet to be transmitted based on the source node and the destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network; and an output subunit, configured to send the identification information of the at least one intermediate routing node to the source node of the data packet to be transmitted, so that the source node of the data packet to be transmitted writes the identification information of the at least one intermediate routing node into the header microchip of the data packet to be transmitted, so that the data packet to be transmitted is transmitted sequentially to each of the intermediate routing nodes according to the XY routing algorithm, and then reaches the destination node of the data packet to be transmitted.

[0009] According to a fourth aspect of the embodiments of this application, a node of an on-chip network is provided, comprising: an acquisition subunit, configured to acquire a header micro-piece of a data packet to be transmitted, wherein the header micro-piece stores identification information of at least one intermediate routing node, the at least one intermediate routing node being determined based on the source node and target node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network; and a transmission subunit, configured to transmit the data packet to be transmitted to the intermediate routing nodes according to the identification information of each intermediate routing node stored in the header micro-piece, and according to an XY routing algorithm, such that the data packet to be transmitted passes through each intermediate routing node sequentially before reaching the target node.

[0010] According to a fifth aspect of the embodiments of this application, a chip is provided, including: a scheduling management unit as described in the third aspect above; and a plurality of nodes of an on-chip network as described in the fourth aspect above.

[0011] According to a sixth aspect of the embodiments of this application, a graphics card is provided, comprising: the chip described in the fifth aspect above.

[0012] According to the data packet transmission scheme provided in this application, at least one intermediate routing node corresponding to the data packet to be transmitted is determined based on the source node and target node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network. After the identification information of each intermediate routing node is sent to the source node of the data packet to be transmitted, the source node stores the identification information of each intermediate routing node in the header micro-chip of the data packet to be transmitted. This allows the nodes in the on-chip network to sequentially transmit the data packet to each intermediate routing node according to the XY routing algorithm, and then transmit the data packet to the target node. Since the intermediate routing nodes are determined based on the data transmission status of each node in the on-chip network, the intermediate routing nodes, as nodes through which the data packet to be transmitted passes, can determine a reasonable transmission path for the data packet to be transmitted, avoid nodes with data traffic congestion, and shorten the time spent transmitting the data packet to the target node, thereby improving the efficiency of data packet transmission. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic diagram of a graphics card according to one embodiment of this application;

[0015] Figure 2 This is a schematic diagram of a chip according to one embodiment of this application;

[0016] Figure 3 This is a flowchart of a data packet transmission method according to an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of reinforcement learning according to an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of an embodiment of the on-chip network of this application;

[0019] Figure 6 This is a flowchart of a data packet transmission method according to another embodiment of this application;

[0020] Figure 7 This is a schematic diagram of an on-chip network according to another embodiment of this application;

[0021] Figure 8 This is a schematic diagram of a scheduling management unit according to an embodiment of this application;

[0022] Figure 9This is a schematic diagram of a node in a mesh network according to an embodiment of this application;

[0023] Figure 10 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0024] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0025] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0026] Network on Chip (NoC): Network on Chip (NoC) is a novel communication method for System on Chip (SoC). NoC connects multiple nodes on a chip, enabling reliable communication between them. The topologies that can be formed by the nodes in a NoC include 2D / 3D mesh networks, torus networks, and ring networks.

[0027] Nodes: Nodes are the elements that make up an on-chip network, also known as tiles. A node includes a process element (PE) and a router. Connected nodes communicate by transmitting data packets, which are transmitted from one node's router to another. In a graphics processing unit (GPU), the processing element within a node is a stream processor.

[0028] Flits: When a message is injected into the on-chip network, it is segmented into one or more data packets, and then the data packets are further segmented into flits of fixed length. Flits are flow control units. A flit includes a head flit, a body flit, and a tail flit. The head flit stores the identification information of the source and destination nodes of the data packet, the body flit stores the actual data of the data packet, and the tail flit indicates the end of the data packet.

[0029] Source node: The node that sends data packets in the on-chip network is the source node.

[0030] Destination Node: In an on-chip network, the node to which a data packet needs to reach is the destination node. The destination node can be directly connected to the source node, or indirectly connected through one or more intermediate nodes. When the destination node is directly connected to the source node, the source node directly sends the data packet to the destination node. When the destination node is connected to the source node through an intermediate node, the source node sends the data packet to the intermediate node, which then forwards the data packet to the destination node.

[0031] XY routing algorithm: During the process of a data packet being sent from the source node to the destination node, if routing is required in the X-dimensional direction, it continues to route along the X-dimensional direction until the current node and the destination node are in the same column, and then routes along the Y-dimensional direction to reach the destination node.

[0032] graphics card

[0033] Figure 1 A schematic diagram of a graphics card 100 is shown. A graphics card (video card) is one of the basic components of a computer. It converts the display information required by the computer system to drive the monitor, and provides progressive or interlaced scanning signals to the monitor to control the correct display. It is an important component connecting the monitor and the computer motherboard. Its built-in parallel computing capabilities are also used for operations such as deep learning.

[0034] Graphics cards include integrated graphics, discrete graphics, and integrated graphics. Integrated graphics are located within the motherboard's northbridge chip, sharing system memory or its own internal memory. Discrete graphics cards are integrated graphics chips and related components onto a separate card, serving as specialized hardware for image processing and parallel computing. Integrated graphics are integrated into the CPU, sharing system memory resources.

[0035] Taking a dedicated graphics card as an example, such as Figure 1 As shown, the graphics card 10 may include a printed circuit board (PCB) 11, a graphics processing unit (GPU) 12, video memory 13, a power supply interface 14, an input interface 15, and an output interface 16, etc.

[0036] The printed circuit board 11 provides mechanical support and electrical connections between the image processor 12, video memory 13, power supply interface 14, input interface 15, and output interface 16. Capacitors, inductors, controllers, etc., are mounted on the printed circuit board 11.

[0037] The graphics processing unit (GPU) 12, also known as the display core or display chip, is the core of the graphics card. It handles image and graphics-related calculations, and is also used for deep learning operations. The GPU 12 includes an arithmetic unit, a control unit, and a cache unit.

[0038] The number of video memory 13 can be multiple, used to cache rendering data processed by or about to be extracted by the graphics processor 12.

[0039] The power supply interface 14 is connected to the graphics processor 12, video memory 13, etc. via wires on the printed circuit board 11, and supplies power to the graphics processor 12, video memory 13, etc.

[0040] Input interface 15 is connected to the motherboard to enable data transfer between the CPU and the graphics processor 12. In some embodiments, input interface 15 may be a PCI-E interface.

[0041] Output interface 16 is used to connect to a monitor, and output interface 16 includes one or more of VGA, DVI, HDMI, DP, SUB-C, etc.

[0042] This application focuses on the flow control within the graphics processor 12, and the specific implementation scheme will be described in detail in subsequent embodiments.

[0043] chip

[0044] Figure 2 This is a schematic diagram of chip 20 according to one embodiment of this application. Chip 20 can be the graphics processor 12 in the above embodiment, that is, chip 20 is a GPU, but the embodiments of this application are not limited to this. Chip 20 can be any chip that satisfies the following structure and function, such as chip 20 can be a CPU, basic setup processor (IPU), etc.

[0045] like Figure 2 As shown, chip 20 includes a scheduling and management unit 21 and multiple nodes 22. The multiple nodes 22 constitute an on-chip network. The topology of the on-chip network can be a 2D / 3D mesh network, torus, or ring network, etc. Each node 22 includes a processing element 221 and a router 222. The processing element 221 can be a processor, DRAM, private cache, network interface, or other hardware resources. In one embodiment, when chip 20 is a GPU, the processing element 221 in node 22 can be a stream processor.

[0046] The scheduling management unit 21 is used to schedule and manage each node 22 and control the flow of data packets between each node 22.

[0047] When data packets are transmitted between nodes 22, if the source node and the target node are directly connected in the on-chip network, the source node sends the data packet to the target node through its route. If the source node and the target node are not directly connected in the on-chip network, the source node sends the data packet to the intermediate node through its route, and the data packet is transmitted to the target node through the forwarding of one or more intermediate nodes.

[0048] Since data packets are transmitted between connected nodes 22 in the form of data streams in the on-chip network, if multiple data packets need to be transmitted from one node 22 to another node 22, each data packet needs to queue up and wait for transmission, causing communication congestion in the on-chip network and resulting in low data packet transmission efficiency.

[0049] This application provides a data packet transmission scheme to at least solve or alleviate the problem of low data packet transmission efficiency. The data packet transmission scheme provided in this application will be described in detail below from the perspectives of the scheduling management unit 21 and the node 22, respectively.

[0050] Data packet transmission method applied to scheduling management unit

[0051] Based on the aforementioned chip, this application provides a data packet transmission method, which can be executed by the scheduling management unit 21 in the above embodiments. The data packet transmission method will be described in detail below through several embodiments.

[0052] Figure 3 This is a flowchart of a data packet transmission method according to an embodiment of this application. Figure 3 As shown, the data packet transmission method includes the following steps:

[0053] Step 301: Determine the source node and destination node of the data packet to be transmitted.

[0054] When a data packet needs to be transmitted from one node to another in an on-chip network, the source node and the destination node of the data packet need to be determined first. The source node is the node that sends the data packet, and the destination node is the node to which the data packet needs to be delivered.

[0055] It should be noted that when one node in an on-chip network sends a data packet to another node, it usually does not involve just one data packet, but rather a series of multiple data packets. For example, a message may be split into multiple data packets, and these split data packets need to be transmitted from one node to another. In this case, these split data packets correspond to the same source node and the same destination node. Therefore, in some embodiments, it is not necessary to determine the source node and destination node separately for each individual data packet that needs to be transmitted in the on-chip network. Instead, a unified source node and destination node can be determined for multiple data packets in a batch or within a certain time period.

[0056] Step 302: Based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network, determine at least one intermediate routing node corresponding to the data packet to be transmitted.

[0057] After determining the source and destination nodes of the data packet to be transmitted, at least one intermediate routing node is determined based on the source and destination nodes and the data transmission status of each node in the on-chip network. An intermediate routing node is a node that the data packet must pass through during its transmission from the source node to the destination node. There can be one or more intermediate routing nodes. When there is only one intermediate routing node, it is the destination node. When there are multiple intermediate routing nodes, in addition to the one that is the destination node, the remaining intermediate routing nodes are the nodes that the data packet must pass through from the source node to the destination node.

[0058] The intermediate routing nodes corresponding to the data packets to be transmitted are determined based on the data transmission status of each node in the on-chip network. That is, when determining the intermediate routing nodes corresponding to the data packets based on the source and destination nodes, it is necessary to consider the data transmission status of each node in the on-chip network. The data transmission status of each node in the on-chip network can be the current data transmission status of each node, or it can be the historical data transmission status of each node. For example, the data transmission status of each node in the on-chip network can be periodically obtained, and the intermediate routing nodes corresponding to the data packets to be transmitted can be determined based on the most recently obtained data transmission status of each node in the on-chip network.

[0059] The data transmission status of each node in the on-chip network can indicate the data traffic situation of each node. Based on the data transmission status of each node, nodes experiencing traffic congestion can be identified. Then, when determining the intermediate routing nodes for the data packets to be transmitted, the transmission path of the data packets to be transmitted can be determined through the intermediate routing nodes, so that the transmission path of the data packets to be transmitted bypasses these congested nodes, shortens the time for the data packets to reach the target node from the source node, and improves the efficiency of data packet transmission.

[0060] Step 303: Send the intermediate routing nodes corresponding to the data packets to be transmitted to the source node of the data packets to be transmitted.

[0061] After identifying the intermediate routing nodes corresponding to the data packet to be transmitted, the intermediate routing nodes are sent to the source node of the data packet. The source node stores the identification information of each intermediate routing node in the header fragment of the data packet. During the transmission of the data packet from its source node to the target node, the relevant nodes, based on the identification information of the intermediate routing nodes stored in the header fragment of the data packet, sequentially transmit the data packet to each intermediate routing node according to the XY routing algorithm, thus realizing the transmission of the data packet from the source node to the target node.

[0062] When storing the identification information of intermediate routing nodes in the header fragment of the data packet to be transmitted, the identification information of each intermediate routing node needs to be stored sequentially in the header fragment of the data packet according to the order in which the data packet passes through each intermediate routing node. Then, after receiving the header fragment of the data packet to be transmitted, the node can determine which intermediate routing node to transmit the data packet to according to the order of the identification information of each intermediate routing node in the header fragment.

[0063] For example, if the data packet to be transmitted corresponds to intermediate routing node 1 and intermediate routing node 2, and intermediate routing node 2 is the target node of the data packet, when transmitting the data packet from the source node to the target node, the data packet is first transmitted from the source node to intermediate routing node 1 according to the XY routing algorithm, and then transmitted from intermediate routing node 1 to the target node according to the XY routing algorithm. The header micro-fragment of the data packet stores the identification information of the source node, intermediate routing node 1, and intermediate routing node 2 sequentially. The source node and all nodes located between the source node and intermediate routing node 1 according to the XY routing algorithm transmit the data packet to intermediate routing node 1 according to the identification information stored in the header micro-fragment, and intermediate routing node 1 and all nodes located between intermediate routing node 1 and intermediate routing node 2 according to the XY routing algorithm, transmit the data packet to intermediate routing node 2 according to the identification information stored in the header micro-fragment.

[0064] When transmitting data packets, the on-chip network generates multiple fragments for each packet, including a header fragment, at least one body fragment, and a tail fragment. The header fragment stores the source node and identification information of each intermediate routing node of the data packet. The data in the data packet is split and stored in each body fragment. The tail fragment indicates the end of the data packet transmission. The header, body, and tail fragments have the same data capacity, for example, 64 bytes each. Compared to the amount of data stored in the body fragments, the header fragment stores much less information, so the identification information of multiple intermediate routing nodes can be stored in the header fragment without adjusting its storage structure.

[0065] When data packets are transmitted between connected nodes in an on-chip network, the header fragment of the data packet is transmitted first, followed by the body fragments. After the body fragments are transmitted, the tail fragment is transmitted. The identification information of the intermediate routing node corresponding to the data packet is stored in the header fragment. Therefore, after receiving the header fragment of the data packet, the node can determine which node to transmit the data packet to.

[0066] In this embodiment, based on the source and destination nodes of the data packet to be transmitted and the data transmission status of each node in the on-chip network, at least one intermediate routing node corresponding to the data packet to be transmitted is determined. After the identification information of each intermediate routing node is sent to the source node of the data packet to be transmitted, the source node stores the identification information of each intermediate routing node in the header micro-fragment of the data packet to be transmitted. This allows the nodes in the on-chip network to sequentially transmit the data packet to each intermediate routing node according to the XY routing algorithm, and then transmit the data packet to the destination node. Since the intermediate routing nodes are determined based on the data transmission status of each node in the on-chip network, the intermediate routing nodes, as nodes through which the data packet to be transmitted passes, can determine a reasonable transmission path for the data packet to be transmitted, avoid nodes with data traffic congestion, and shorten the time spent transmitting the data packet to the destination node, thereby improving the efficiency of data packet transmission.

[0067] The process of transmitting data packets from the source node to the intermediate routing node, and from one intermediate routing stage to another, is carried out according to the XY routing algorithm, which can avoid deadlock during the transmission of data packets.

[0068] In one possible implementation, when determining the intermediate routing node corresponding to the data packet to be transmitted, it can be checked whether the intermediate routing table stores at least one alternative routing entry. The source node corresponding to the alternative routing entry is the source node of the data packet to be transmitted, and the destination node corresponding to the alternative routing entry is the destination node of the data packet to be transmitted. The alternative routing entry includes at least one intermediate routing node, and the alternative routing entry is determined based on the data transmission status of each node in the on-chip network. If the intermediate routing table stores an alternative routing entry, then the intermediate routing nodes included in the alternative routing entry with the most recent update time are determined as the intermediate routing nodes corresponding to the data packet to be transmitted.

[0069] An intermediate routing table can store one or more routing entries. These entries are created for historical data packets to be transmitted, recording the transmission path of those packets. Each entry records the corresponding source node and at least one intermediate routing node, one of which is the corresponding destination node. Therefore, a routing entry records the data transmission path from the source node to the destination node. Different routing entries can correspond to the same or different source nodes, and different routing entries can correspond to the same or different destination nodes; therefore, different routing entries can also correspond to the same source node and the same destination node.

[0070] Table 1 below shows an intermediate routing table according to an embodiment of this application, which records three routing entries. Each routing entry records the source node SRC and two intermediate routing nodes IRP1 and IRP2, with intermediate routing node IRP2 being the destination node. The numbers 0, 2, 3, 4, 6, and 8 in Table 1 are the identifiers of the corresponding nodes.

[0071] Table 1

[0072] SRC IRP1 IRP2 0 2 2 0 4 8 3 6 8

[0073] In Table 1 above, the first routing entry includes the same intermediate routing node IRP1 and intermediate routing node IRP2, so the first routing entry records the data transmission path from source node 0 to destination node 2 according to the XY routing algorithm. The second routing entry records the data transmission path from source node 0 through intermediate routing node 4 to destination node 8. The third routing entry records the data transmission path from source node 3 through intermediate routing node 6 to destination node 8.

[0074] The routing entries recorded in the intermediate routing table are determined based on the data transmission status of each node in the on-chip network at that time. Routing entries in the intermediate routing table can be created for packet transmission tasks. A packet transmission task needs to transmit one or more packets from a corresponding source node to a destination node. After creating a routing entry for this packet transmission task, each packet included in the packet transmission task is transmitted from the source node to the destination node sequentially according to the routing entry. After each packet included in the packet transmission task is transmitted to the destination node, the routing entry in the intermediate routing table is deleted or reclaimed.

[0075] There may be multiple route entries in the intermediate routing table that correspond to the same source node and the same destination node, so multiple candidate route entries may be found in the intermediate routing table. If a candidate route entry is found in the intermediate routing table, the intermediate routing nodes included in that candidate route entry are determined as the intermediate routing nodes corresponding to the data packet to be transmitted. If multiple candidate route entries are found in the intermediate routing table, the intermediate routing nodes included in the candidate route entry with the most recent update time are determined as the intermediate routing nodes corresponding to the data packet to be transmitted.

[0076] For a candidate route entry with a more recent update time, the data transmission status of each node in the on-chip network at the time the candidate route entry is determined is close to the data transmission status of each node in the on-chip network at the current time. Therefore, the candidate route entry with the more recent update time is used to transmit the data packet to be transmitted, so that the transmission path of the data packet to be transmitted is more matched with the data transmission status of each node in the on-chip network at the current time, and the time required to transmit the data packet to be transmitted is shortened.

[0077] It should be understood that the routing entries mentioned in the embodiments of this application include intermediate routing nodes, meaning that the routing entries record the identification information of intermediate routing nodes.

[0078] In this embodiment, the intermediate routing table stores routing entries generated for historical data packets to be transmitted. The routing entries define the transmission path of the data packets. Since the transmission time of data packets in the on-chip network is short, and the data transmission status of each node in the on-chip network will not fluctuate significantly in a short period of time, alternative routing entries with the same source node and the same destination node as the data packets to be transmitted can be found in the intermediate routing table. Then, the intermediate routing nodes included in an alternative routing entry are determined as the intermediate routing nodes of the data packets to be transmitted. That is, the data packets to be transmitted are transmitted according to the transmission path defined by an alternative routing entry, without having to re-determine the intermediate routing nodes based on the data transmission status of each node in the on-chip network for each data packet to be transmitted. This saves the time for analyzing the data transmission status of some data packets to be transmitted and can further improve the transmission efficiency of data packets.

[0079] The following describes one implementation method for searching alternative route entries from the intermediate routing table.

[0080] The intermediate routing table has three registers: a selection register, a result register, and a mode register. After determining the source and destination nodes of the data packet to be transmitted, a binary number (01) is written to the mode register to instruct the intermediate routing table to enter search mode. Then, the identification information of the source and destination nodes of the data packet to be transmitted is written to the selection register, indicating the entry to be searched. In search mode, the intermediate routing table first reads the identification information of the source node of the data packet to be transmitted from the selection register, and searches for the route entry whose source node is the same as the source node of the data packet to be transmitted from the stored route entries. Then, it reads the identification information of the destination node of the data packet to be transmitted from the selection register, and searches for the route entry whose source node is the same as the source node of the data packet to be transmitted, and whose destination node is the same as the destination node of the data packet, from the route entries whose source node is the same as the source node of the data packet to be transmitted. This yields candidate route entries whose source node is the same as the source node of the data packet to be transmitted, and whose destination node is the same as the destination node of the data packet to be transmitted. Then, following the Least Recently Used (LRU) principle, the most recently updated candidate route entry is selected from all the found candidate route entries. The source node and all intermediate route nodes recorded in this candidate route entry are written into the result register, and the binary number 11 is written into the mode register to indicate that the intermediate routing table has exited the search mode. After the intermediate routing table has written the source node and all intermediate route nodes recorded in a candidate route entry into the result register, it can read the intermediate route nodes from the result register as the intermediate route nodes for the data packets to be transmitted.

[0081] In one possible implementation, if no alternative route entry is stored in the intermediate routing table, the delay information of each node in the on-chip network is obtained. The delay information can indicate the delay of each node in the on-chip network in transmitting data packets. Then, the delay information, the attribute information of the data packet to be transmitted, and the identification information of the source node and the destination node of the data packet to be transmitted are input into a pre-trained traffic-aware model to obtain a new route entry output by the traffic-aware model. The new route entry includes at least one intermediate routing node, the source node corresponding to the new route entry is the source node of the data packet to be transmitted, and the destination node corresponding to the new route entry is the destination node of the data packet to be transmitted.

[0082] After obtaining a new route entry, it is determined whether the data transmission path corresponding to the new route entry constitutes a deadlock or livelock with the data transmission paths corresponding to each route entry in the intermediate routing table. If no deadlock or livelock occurs, the new route entry is stored in the intermediate routing table, and then each intermediate routing node included in the new route entry is determined as the intermediate routing node corresponding to the data packet to be transmitted. If a deadlock or livelock occurs, the new route entry is regenerated through the traffic-aware model.

[0083] A pre-trained traffic-aware model can plan the data transmission path from the source node to the target node based on the latency information of each node in the on-chip network, avoiding nodes with traffic congestion and shortening the time to transmit data packets from the source node to the target node. Traffic-aware models can be trained using reinforcement learning (RL), and the network structure can be Q-learning, deep quality networks (DeepQ Network, DQN), etc. Traffic-aware models can also be trained using other types of neural networks, such as convolutional neural networks (CNNs).

[0084] The on-chip network includes a delay collector in the routing of the nodes. The delay collector can collect the delay when the nodes transmit data packets and calculate the average delay over N clock cycles. Then, after M clock cycles, it sends one or more average delays to the scheduling and management unit, where M is greater than N. The scheduling and management unit can input the received average delay, the attribute information of the data packets to be transmitted, and the identification information of the source and destination nodes of the data packets to be transmitted into the traffic-aware model to obtain new routing entries.

[0085] The attribute information of the data packet to be transmitted includes the packet location, packet size, etc.

[0086] In this embodiment, if no alternative route entry is stored in the intermediate routing table, the latency information of each node in the on-chip network is obtained. The obtained latency information, the attribute information of the data packet to be transmitted, and the identification information of the source and destination nodes of the data packet are input into the traffic-aware model to obtain a newly created route entry output by the traffic-aware model. The intermediate routing nodes included in the newly created route entry are then determined as the intermediate routing nodes for the data packet to be transmitted. The traffic-aware model can plan a data transmission path with lower latency based on the latency information of each node in the on-chip network. The intermediate routing nodes in the newly created routing table output by the traffic-aware model define this data transmission path, thereby determining the intermediate routing nodes in the newly created routing table as the intermediate routing nodes for the data packet to be transmitted. This allows the data packet to be transmitted sequentially to each intermediate routing node according to the XY routing algorithm, avoiding nodes experiencing traffic congestion, shortening the time spent transmitting the data packet to the target node, and improving data packet transmission efficiency.

[0087] The newly created route entries output by the traffic-aware model are stored in the intermediate routing table. In the short term, newly generated data packets with the same source node and destination node as the newly created route entry can directly read the newly created route entry from the intermediate routing table to obtain the intermediate routing node, without having to perform inference through the traffic-aware model again, thus shortening the transmission time of subsequent data packets.

[0088] The following section uses reinforcement learning as an example to illustrate the training process of a traffic-aware model. The training process of a traffic-aware model may include the following steps:

[0089] S1. Generate the initial training dataset using a simulator with hardware cycle precision.

[0090] An emulator is a software-implemented chip that can simulate the chip's data processing capabilities, such as simulating the transmission of data packets between nodes forming an on-chip network. Emulators with hardware cycle precision include Bookim and Garnet.

[0091] The initial training dataset includes multiple training samples, which contain the following information:

[0092] (i) The source and destination nodes of the data packet, i.e., from which node the data packet needs to be transmitted to which node;

[0093] (ii) The data transmission status of each node in the on-chip network, such as the delay in transmitting data packets to each node;

[0094] (iii) The transmission path of the data packet from the source node to the target node.

[0095] It should be noted that, in addition to using a simulator with hardware cycle precision to generate the initial training dataset, an event-driven simulator can also be used to generate the initial training dataset.

[0096] S2. Train the initial traffic awareness model using the initial training dataset.

[0097] The initial traffic-aware model is obtained by training the training samples in the initial training dataset. This enables the traffic-aware model to generate intermediate routing nodes corresponding to data packets based on the source and destination nodes of the data packets and the data transmission status of each node in the on-chip network. The generated intermediate routing nodes can define the transmission path of the data packets.

[0098] It should be understood that the initial traffic-aware model only has the ability to generate intermediate routing nodes, but the accuracy of the generated intermediate routing nodes is low.

[0099] S3. Collect real-time training datasets using a simulator.

[0100] After obtaining the initial traffic-aware model, it is combined with the simulator. The initial traffic-aware model is used to determine the intermediate routing nodes for the data packets to be transmitted in the simulator. The simulator transmits the data packets according to the intermediate routing nodes determined by the initial traffic-aware model, and the transmission delay of each node for the data packets to be transmitted is obtained. The simulator transmits data packets in the manner described in the previous embodiment, that is, it transmits the data packets to be transmitted sequentially to each intermediate routing node according to the XY routing algorithm.

[0101] A delay collector is set within the routing table of a node. The delay collector can collect the delay when the node transmits data packets and calculate the average delay over N clock cycles.

[0102] Real-time training data includes multiple training samples, which contain information such as the average latency of the corresponding nodes.

[0103] S4. Based on reinforcement learning, the initial traffic awareness model is trained using a real-time training dataset to obtain the traffic awareness model.

[0104] Reinforcement learning-based training systems can include Q-learning, DQN, etc.

[0105] Figure 4 This is a schematic diagram of reinforcement learning according to one embodiment of this application. Figure 4 As shown, based on the environment, state, operation, and reward of reinforcement learning, the initial traffic awareness model is trained to obtain the traffic awareness model. Wherein, state S... t State S corresponds to the state of the t-th data packet. t+1For the state corresponding to the t-th data packet, the reward R is... t The reward R is the reward corresponding to the (t+1)th data packet. t+1 This is the reward corresponding to the (t+1)th data packet, where t is a positive integer.

[0106] The reinforcement learning environment is a simulation environment of on-chip network, and the topology and routing strategy of the simulation environment are consistent with those of the chip.

[0107] The state of reinforcement learning is the real-time traffic state of each node in the on-chip network, including packet location, packet size, packet delay, and the intermediate routing node corresponding to the packet.

[0108] The reinforcement learning operation is the intermediate routing node corresponding to the next data packet transmission task.

[0109] The reward for reinforcement learning is equal to the difference between the design latency and the packet latency. The design latency equals the number of nodes on the packet transmission path multiplied by the node latency plus a specific latency. The node latency is determined by the routing latency during packet transmission and the latency of transmission over the wires between nodes; for example, the routing latency is 5 clock cycles, and the latency of transmission over the wires between nodes is 1 clock cycle. The specific latency is determined by the structure of the on-chip network and the number of nodes included; for example, the specific latency of a 3×3 on-chip network can be set to 5 clock cycles. If a deadlock or livelock occurs in the packet transmission path determined by the intermediate routing nodes output by the initial traffic-aware model, the reward value is set to a large negative number. The packet latency can be obtained from training samples in the real-time training dataset.

[0110] The following example will be used to explain in detail how to store newly created route entries in the intermediate routing table.

[0111] The intermediate routing table has three registers: a selection register, a result register, and a mode register. After acquiring a new route entry that includes at least one intermediate routing node, a binary number 00 is written to the mode register, indicating that the intermediate routing table is entering insertion mode. Then, the identification information of the source node and each intermediate routing node included in the new route entry are written to the result register, indicating the content to be inserted into the new route entry. The intermediate routing table then reads the contents stored in the result register and either writes the read content into an empty entry or replaces an existing route entry.

[0112] When writing content to the result register, if there is an empty entry in the intermediate routing table, the read content is stored in the empty entry to form a routing entry. If there is no empty entry in the intermediate routing table, the content of the routing entry with the earlier update time is replaced according to the LRU principle.

[0113] In one possible implementation, if the data transmission path corresponding to the newly created route entry forms a deadlock or livelock with the data transmission path corresponding to the route entry in the intermediate routing table, a negative incentive is generated, and the delay information, attribute information of the data packet to be transmitted, identification information of the source node and target node of the data packet to be transmitted, and the negative incentive are sent to the server so that the server can train the traffic awareness model through reinforcement learning.

[0114] Since nodes in the on-chip network can transmit data packets simultaneously according to multiple data transmission paths defined by each routing entry in the intermediate routing table, the data transmission path corresponding to the newly created routing entry output by the traffic-aware model may cause deadlock or livelock with the data transmission paths corresponding to each routing entry in the intermediate routing table, affecting the normal operation of the on-chip network. Therefore, before storing the newly created routing entry in the intermediate routing table, it is necessary to check whether the newly created routing table will cause deadlock or livelock.

[0115] After sending latency information, attribute information of the data packets to be transmitted, identification information of the source and destination nodes of the data packets, and negative incentives to the server, the server can train the traffic-aware model based on reinforcement learning using this information. This reduces the probability of deadlock or livelock caused by the traffic-aware model's output routing entries. The server will then distribute the trained traffic-aware model, allowing the scheduling and management unit to subsequently generate new routing entries using the updated traffic-aware model.

[0116] In this embodiment, if creating a new routing table would lead to deadlock or livelock, a negative incentive is generated for the new routing entry and sent to the server. The server can then train the traffic-aware model based on the negative incentive, reducing the probability that the routing entries output by the traffic-aware model will cause deadlock or livelock. Subsequently, the updated traffic-aware model is used to generate new routing entries, reducing the number of deadlock or livelock occurrences and improving the stability and reliability of the on-chip network operation.

[0117] In one possible implementation, each node in the on-chip network (NIC) has a latency collector configured in its routing. This latency collector collects the latency of data packets transmitted by the nodes and calculates the average latency over N clock cycles. Each node in the NIC can then send the latency information calculated by the latency collector to the scheduling management unit. The scheduling management unit periodically sends this latency information to the server. The server can then use reinforcement learning to train the traffic-aware model based on the received latency information, continuously optimizing the model. The server can then distribute the trained traffic-aware model to the scheduling management unit via an update driver. The scheduling management unit subsequently uses the trained traffic-aware model to generate new routing entries, making the data transmission paths defined by these new routing entries more rational and efficient, thereby improving the data transmission performance of the NIC.

[0118] In one possible implementation, the data packet to be transmitted can correspond to one or more intermediate routing nodes. If the data packet to be transmitted corresponds to one intermediate routing node, then that intermediate routing node is the target node of the data packet to be transmitted. Therefore, when transmitting the data packet, the XY routing algorithm is used to transmit the data packet from the source node to the target node. If the data packet to be transmitted corresponds to n intermediate routing nodes, where n is a positive integer greater than or equal to 2, then the nth intermediate routing node among the n intermediate routing nodes is the target node of the data packet to be transmitted. When transmitting the data packet, the XY routing algorithm is used to transmit the data packet from the source node to the first intermediate routing node, and then from the ith intermediate routing node to the (i+1)th intermediate routing node, where i is a positive integer less than n.

[0119] Figure 5 This is a schematic diagram of an embodiment of the on-chip network of this application. Figure 5 As shown, the on-chip network includes 9 nodes, from Tile00 to Tile08. Each node includes a route, and the routes included by nodes Tile00 to Tile08 are routes R000 to R008, respectively. Routes R000 to R008 form a mesh network. Route R000 is connected to routes R001 and R003. Route R001 is connected to routes R000, R002, and R004. Route R002 is connected to routes R001 and R005. Route R003 is connected to routes R000, R004, and R006. Route R004 is connected to routes R001, R003, R005, and R007. Route R005 is connected to routes R002, R004, and R008. Route R006 is connected to routes R003 and R007. Route R007 is connected to routes R004, R006, and R008. Route R008 is connected to routes R005 and R007.

[0120] The source node of the data packet A to be transmitted is node Tile00, and the destination node is node Tile02. The intermediate routing node for determining the data packet A to be transmitted is node Tile002. When transmitting the data packet A to be transmitted, according to the XY routing algorithm, node Tile00 transmits the data packet A to be transmitted to route R001 through route R000, route R001 transmits the data packet A to be transmitted to route R002, and node Tile02 obtains the data packet A to be transmitted from route R002.

[0121] The source node of the data packet B to be transmitted is node Tile00, and the destination node is node Tile08. The intermediate routing nodes for the data packet B to be transmitted are nodes Tile04 and Tile08. When transmitting the data packet B, according to the XY routing algorithm, node Tile00 transmits the data packet B to route R001 through route R000, route R001 transmits the data packet B to route R004, route R004 transmits the data packet B to route R005, route R005 transmits the data packet B to route R008, and node Tile08 obtains the data packet B from route R008.

[0122] The source node of the data packet C to be transmitted is node Tile03, and the destination node is node Tile08. The intermediate routing nodes for the data packet C to be transmitted are nodes Tile06 and Tile08. When transmitting the data packet C, according to the XY routing algorithm, node Tile03 transmits the data packet C to route R006 through route R003, route R006 transmits the data packet C to route R007, route R007 transmits the data packet C to route R008, and node Tile08 obtains the data packet C from route R008.

[0123] It should be noted that, in order to facilitate the management of intermediate routing nodes, different data packets can be assigned to the same number of intermediate routing nodes, such as each data packet being assigned to 2 intermediate routing nodes. In this case, if the intermediate routing node corresponding to the data packet to be transmitted is determined to be its target node, that is, the data packet to be transmitted is directly transmitted from the source node to the target node according to the XY routing algorithm, then the 2 intermediate routing nodes corresponding to the data packet to be transmitted are both the target nodes of the data packet to be transmitted.

[0124] In this embodiment, the intermediate routing nodes for the data packet to be transmitted can be one or more. When there is only one intermediate routing node, the data packet is transmitted from the source node to the target node according to the XY routing algorithm. When there are multiple intermediate routing nodes, the data packet is transmitted sequentially to each intermediate routing node according to the XY routing algorithm, and the last intermediate routing node becomes the target node. Therefore, since it is not limited by the number of intermediate routing nodes, a more reasonable data transmission path can be determined based on the data transmission status of each node in the on-chip network, ensuring the efficiency of data packet transmission.

[0125] It should be noted that the data packet transmission method in this application embodiment can be implemented based on a kernel-mode driver.

[0126] Data packet transmission method applied to nodes

[0127] Based on the aforementioned chip, this application provides a data packet transmission method, which can be executed by node 22 in the above embodiments. The following describes this data packet transmission method in detail through several embodiments.

[0128] Figure 6 This is a flowchart of a data packet transmission method according to an embodiment of this application. Figure 6 As shown, the data packet transmission method includes the following steps:

[0129] Step 601: Obtain the header fragment of the data packet to be transmitted.

[0130] When a node in an on-chip network needs to send a data packet to another connected node, that node can obtain the header fragment of the data packet. If a node is the source node of the data packet, it can directly obtain the header fragment after splitting the data packet into header, body, and tail fragments. If a node is not the source node of the data packet, it can receive data packets sent by other nodes, and when receiving data packets, it will first receive the header fragment of the data packet.

[0131] The header micro-chip of the data packet to be transmitted stores the identification information of at least one intermediate routing node. Each intermediate routing node is determined based on the source node and destination node of the data packet to be transmitted, as well as the data transmission status of each node in the on-chip network. Among the intermediate routing nodes corresponding to the data packet to be transmitted, one of the intermediate routing nodes is the destination node of the data packet to be transmitted.

[0132] It should be noted that the process of determining the intermediate routing nodes corresponding to the data packets to be transmitted can be found in the description of the aforementioned data packet transmission method embodiment applied to the scheduling management unit, and will not be repeated here.

[0133] Step 602: Based on the identification information of each intermediate routing node stored in the header micro-chip, transmit the data packet to be transmitted to the intermediate routing nodes according to the XY routing algorithm, so that the data packet to be transmitted passes through each intermediate routing node in sequence and arrives at the target node.

[0134] After obtaining the header fragment of the data packet to be transmitted, the node determines the next intermediate routing node to which the data packet needs to be transmitted based on the identification information of each intermediate routing node stored in the header fragment. Then, it transmits the data packet to be transmitted to the determined next intermediate routing node according to the XY routing algorithm, so that the data packet to be transmitted is transmitted to the target node after passing through each intermediate routing node in sequence.

[0135] In this embodiment, the intermediate routing nodes corresponding to the data packets to be transmitted are determined based on the data transmission status of each node in the on-chip network. As the nodes that the data packets to be transmitted need to pass through during the transmission to the target node, the data packets to be transmitted are transmitted according to the XY routing algorithm when they are transmitted between the source node and the intermediate routing nodes, and between the intermediate routing nodes. Therefore, the intermediate routing nodes can determine the reasonable transmission path of the data packets to be transmitted, avoid the nodes with traffic congestion in the on-chip network, shorten the time spent transmitting the data packets to the target node, and thus improve the efficiency of data packet transmission in the on-chip network.

[0136] In one possible implementation, if the current node is the source node of the data packet to be transmitted, when obtaining the header fragment of the data packet, it receives identification information from at least one intermediate routing node from the scheduling management unit, writes the received identification information into the header fragment of the data packet to be transmitted, and obtains a header fragment storing the identification information of the intermediate routing nodes. If the current node is not the source node of the data packet to be transmitted, it receives the header fragment of the data packet to be transmitted from the upstream node through the XY routing algorithm.

[0137] If the current node is the source node of the data packet to be transmitted, the data packet is sent from this node. The node will split the data packet into a header fragment, a body fragment, and a tail fragment. After receiving the identification information of at least one intermediate routing node corresponding to the data packet to be transmitted from the scheduling management unit, the node will store the identification information of each intermediate routing node corresponding to the data packet into the header fragment of the data packet. Then, the node will send the data packet to the first intermediate routing node that the data packet needs to reach according to the identification information of each intermediate routing node stored in the header fragment of the data packet.

[0138] If the current node is not the source node of the data packet to be transmitted, then the node receives the data packet to be transmitted sent by its upstream node according to the XY routing algorithm. The data packet to be transmitted is transmitted to the node in the order of header fragment, body fragment and tail fragment, thereby obtaining the header fragment of the data packet to be transmitted.

[0139] like Figure 5 As shown, if the current node is Tile00 and the data packet to be transmitted is data packet A, then node Tile00 receives the identification information of node Tile02 sent by the scheduling management unit, and then stores the identification information of node Tile02 in the header fragment of data packet A. If the current node is Tile04 and the data packet to be transmitted is data packet B, then node Tile04 receives the header fragment sent by node Tile01. This header fragment stores the identification information of each intermediate routing node corresponding to data packet B, that is, it stores the identification information of nodes Tile04 and Tile08. If the current node is Tile07 and the data packet to be transmitted is data packet C, then node Tile07 receives the header fragment sent by node Tile06. This header fragment stores the identification information of each intermediate routing node corresponding to data packet C, that is, it stores the identification information of nodes Tile06 and Tile08.

[0140] In this embodiment, the source node of the data packet to be transmitted receives the identification information of the intermediate routing node from the scheduling management unit and stores the received identification information in the header micro-piece of the data packet to be transmitted. Other nodes that are not the source node of the data packet to be transmitted will first receive the header micro-piece of the data packet to be transmitted when receiving the data packet to be transmitted. Then, each node on the transmission path of the data packet to be transmitted can transmit the data packet to the next intermediate routing node according to the identification information of the intermediate routing node stored in the header micro-piece and the XY routing algorithm. This improves the data packet transmission efficiency and avoids deadlock or livelock problems, ensuring the reliability of the on-chip network operation.

[0141] In one possible implementation, if the current node is the source node of the data packet to be transmitted, after receiving the identification information of at least one intermediate routing node from the scheduling management unit, the current node can sequentially write the identification information of each intermediate routing node into the header micro-fragment of the data packet to be transmitted according to the order requirements of the data packet to be transmitted arriving at each intermediate routing node, so that the header micro-fragment of the data packet to be transmitted sequentially stores the identification information of the source node of the data packet to be transmitted and the identification information of each intermediate routing node.

[0142] The header micro-element stores the identification information of the source node and each intermediate routing node of the data packet to be transmitted, and the identification information of the source node and each intermediate routing node is stored sequentially in the header micro-element. If there are multiple intermediate routing nodes, the identification information of each intermediate routing node is stored after the identification information of the source node, according to the order in which the data packet to be transmitted arrives at each intermediate routing node. The identification information of the intermediate routing node that arrives first for the data packet to be transmitted is placed before the identification information of the intermediate routing node that arrives later for the data packet to be transmitted.

[0143] For example, the intermediate routing nodes of the data packet to be transmitted include intermediate routing node 1, intermediate routing node 2 and intermediate routing node 3. When the data packet to be transmitted is transmitted from the source node to the target node, it needs to pass through intermediate routing node 1, intermediate routing node 2 and intermediate routing node 3 in sequence. Then, the header micro-fragment of the data packet to be transmitted stores the identification information of the source node, the identification information of intermediate routing node 1, the identification information of intermediate routing node 2 and the identification information of intermediate routing node 3 in sequence.

[0144] If the current node is not the source node of the data packet to be transmitted, after the current node receives the header fragment transmitted by the upstream node through the XY routing algorithm, the current node can parse the header fragment of the data packet to be transmitted to obtain the identification information of the source node of the data packet to be transmitted and the identification information of each intermediate routing node of the data packet to be transmitted. Then, based on the storage order of the identification information of each intermediate routing node, the current node can determine the order requirement of the data packet to be transmitted to reach each intermediate routing node.

[0145] If there are multiple intermediate routing nodes for the data packet to be transmitted, after parsing the header fragment of the data packet, the identification information of the source node and the identification information of each intermediate routing node can be obtained. The identification information of each intermediate routing node is stored sequentially after the identification information of the source node according to the order in which the data packet arrives at each intermediate routing node. Therefore, after parsing the identification information of each intermediate routing node, the order in which the data packet arrives at each intermediate routing node can be determined according to the storage order of the identification information of each intermediate routing node, and thus the node to which the data packet needs to be sent can be determined.

[0146] For example, by parsing the header fragment of the data packet to be transmitted and obtaining the identification information of the source node, the identification information of intermediate routing node 4, and the identification information of intermediate routing node 5, it can be determined that the data packet to be transmitted needs to reach intermediate routing node 4 first, and then reach intermediate routing node 5.

[0147] In this embodiment, the header micro-chip stores the identification information of the source node of the data packet to be transmitted and the identification information of each intermediate routing node. Moreover, the identification information of each intermediate routing node is stored sequentially after the identification information of the source node according to the order in which the data packet to be transmitted arrives at the intermediate routing nodes. By parsing the header micro-chip, the identification information of each intermediate routing node can be obtained. Then, according to the storage order of the identification information of each intermediate routing node, the order in which the data packet to be transmitted arrives at each intermediate routing node can be determined, ensuring that the data packet to be transmitted can be transmitted to each intermediate routing node sequentially according to the XY routing algorithm.

[0148] In one possible implementation, when a node transmits a data packet to be transmitted based on the identification information stored in the header micro-piece, it can determine whether the current node is an intermediate routing node of the data packet to be transmitted based on the identification information of each intermediate routing node stored in the header micro-piece. If the current node is an intermediate routing node of the data packet to be transmitted and the current node is not the target node of the data packet to be transmitted, then the micro-pieces included in the received data packet to be transmitted are stored in a buffer. After storing all the micro-pieces included in the data packet to be transmitted in the buffer, the micro-pieces of the data packet to be transmitted stored in the buffer are transmitted to the next intermediate routing node according to the XY routing algorithm.

[0149] Since the header fragment stores the identification information of the source node and each intermediate routing node of the data packet to be transmitted, and each intermediate routing node includes the destination node of the data packet, a node, upon receiving the header fragment of the data packet, can determine whether it is an intermediate routing node of the data packet and whether it is the destination node of the data packet based on the identification information stored in the header fragment. If the current node is the destination node of the data packet, it stops transmitting the data packet after receiving each fragment of the data packet. If the current node is not the destination node of the data packet, it needs to continue transmitting the data packet based on the identification information stored in the header fragment.

[0150] If the current node is an intermediate routing node for the data packet to be transmitted, and the current node is not the destination node of the data packet, then the current node receives the header, body, and tail fragments of the data packet in sequence, and stores all the received header, body, and tail fragments in a buffer. After storing the header, body, and tail fragments of the data packet in the buffer, the current node then sends the header, body, and tail fragments in the buffer to the next intermediate routing node according to the XY routing algorithm. When the current node transmits the header, body, and tail fragments of the data packet to the next intermediate routing node, it still transmits the fragments in the order of header, body, and tail fragments.

[0151] The header fragment of the data packet to be transmitted stores the data volume information of the data packet to be transmitted. Based on the data volume information, it can be determined whether each fragment of the data packet to be transmitted has been stored in the buffer.

[0152] Each node's routing is equipped with a buffer. The buffer's capacity is greater than the maximum data size of the data packets transmitted in the on-chip network, meaning that any data packet transmitted in the on-chip network can be stored in the buffer.

[0153] like Figure 5 As shown, after receiving the header fragment of the data packet B to be transmitted, node Tile04 determines that it is an intermediate routing node of the data packet B to be transmitted, but not the target node of the data packet B, based on the identification information of the intermediate routing node stored in the header fragment. Then, node Tile04 stores each fragment of the subsequently received data packet B to be transmitted into the buffer of route R004. After storing each fragment of the data packet B to be transmitted into the buffer of route R004, it sends the fragments in the buffer of route R004 to node Tile08 according to the identification information of the intermediate routing node stored in the header fragment, that is, it sends the fragments in the buffer of route R004 to node Tile05.

[0154] In this embodiment, a buffer is set in the routing of the node. When a node acts as an intermediate routing node for a data packet to be transmitted, and the node is not the target node of the data packet, after receiving the micro-fragments of the data packet to be transmitted, the node stores the received micro-fragments in the buffer. After storing all the micro-fragments of the data packet to be transmitted in the buffer, the node sends the micro-fragments in the buffer to the next intermediate routing node according to the XY routing algorithm. This ensures that the data transmission path between the source node and the first intermediate routing node, as well as the data transmission path between two adjacent intermediate routing nodes, both satisfy the XY routing algorithm. The data transmission path between the source node and the target node that does not satisfy the XY routing algorithm is split into multiple sub-paths that satisfy the XY routing algorithm, avoiding deadlock or livelock problems during data packet transmission. This improves the data packet transmission efficiency while ensuring the reliability of data packet transmission on the on-chip network.

[0155] In one possible implementation, if the current node is not the intermediate routing node corresponding to the data packet to be transmitted, the received data packet fragments are transmitted to the next intermediate routing node according to the XY routing algorithm.

[0156] If the current node is not an intermediate routing node of the data packet to be transmitted, then the node is a node on the data transmission path between the source node and the first intermediate routing node, or a node on the transmission path between two adjacent intermediate routing nodes. After receiving the micro-fragments of the data packet to be transmitted, the node transmits the received micro-fragments to the next intermediate routing node in the form of a data stream according to the XY routing algorithm, without having to store all the micro-fragments of the data packet to be transmitted in a buffer before sending the micro-fragments of the data packet to the next intermediate routing node.

[0157] like Figure 5 As shown, after receiving the header fragment of the data packet A to be transmitted, node Tile01 determines that it is not an intermediate routing node of the data packet A to be transmitted based on the identification information of the intermediate routing node stored in the header fragment. Then, node Tile01 sends the received fragment of the data packet A to node Tile04 in the form of a data stream.

[0158] In this embodiment, if a node is not an intermediate routing node for the data packet to be transmitted, the node satisfies the XY routing algorithm when transmitting the data packet, and will not cause deadlock or livelock. Therefore, it is not necessary to store all the micro-pieces of the data packet to be transmitted into the buffer and then transmit each micro-piece in the buffer to the next intermediate routing node according to the XY routing algorithm, which saves the time of storing each micro-piece in the buffer and ensures the efficiency of data packet transmission in the on-chip network.

[0159] In one possible implementation, if the current node is an intermediate routing node for the data packet to be transmitted, after storing the header fragment of the data packet in the buffer, the current node adds an invalid flag to the identification information of the current node stored in the header fragment. Correspondingly, when the node transmits the data packet to the intermediate routing node according to the XY routing algorithm, it can determine the next tag information without an invalid flag as the target tag information according to the order of the identification information stored in the header fragment, and then transmit the data packet to the intermediate routing node identified by the target tag information according to the XY routing algorithm.

[0160] like Figure 5As shown, the header fragments of the data packet B to be transmitted sequentially store identification information Tile00, Tile04, and Tile08. Tile00 is the identification information of the source node, while Tile04 and Tile08 are the identification information of two intermediate routing nodes. After receiving the header fragment of the data packet B, node Tile04 determines itself as an intermediate routing node based on the identification information stored in the header fragment. After storing the header fragment of the data packet B in a buffer, node Tile04 adds an invalid flag to the identification information Tile04 in the header fragment. After storing all fragments of the data packet B in the buffer, node Tile04, based on the identification information stored in the header fragments, and since the identification information Tile04 of the first intermediate routing node has been invalidated, then transmits the fragments stored in the buffer to node Tile08 according to the XY routing algorithm. After receiving the header fragment of the data packet B to be transmitted, node Tile06, based on the identification information stored in the header fragment, and since the identification information of the first intermediate routing node Tile04 has been marked with an invalid flag, transmits the received fragment to node Tile08 in the form of a data stream according to the XY routing algorithm.

[0161] In this embodiment, the header micro-chip stores the identification information of each intermediate routing node in sequence. After the header micro-chip is transmitted to an intermediate routing node, the intermediate routing node adds invalid information to the identification information stored in the header micro-chip, so that the current intermediate routing node and subsequent nodes can determine the next intermediate routing node, ensuring the correctness of data packet transmission.

[0162] Figure 7 This is a schematic diagram of an on-chip network according to another embodiment of this application. (See diagram below.) Figure 7 As shown, the on-chip network includes 25 nodes, from Tile00 to Tile24. Each node contains routes, and the routes included in nodes Tile00 to Tile24 are routes R000 to R024, respectively. The connected routes R000 to R024 form a 5×5 mesh network.

[0163] Data packets D, E, and F are transmitted simultaneously in the on-chip network. The source node for data packet D is node Tile02, and the destination node is Tile11. The source node for data packet E is node Tile03, and the destination node is Tile16. The source node for data packet F is node Tile04, and the destination node is Tile21.

[0164] If the traditional XY routing algorithm is used to transmit data packets D, E, and F, the transmission path of data packet D is Tile02→Tile01→Tile06→Tile11 (as shown in D′ in the figure), the transmission path of data packet E is Tile03→Tile02→Tile01→Tile06→Tile11→Tile16 (as shown in E′ in the figure), and the transmission path of data packet F is Tile04→Tile03→Tile02→Tile01→Tile06→Tile11→Tile16→Tile21 (as shown in F in the figure). Because data packets E and D are congested at node Tile02, and data packets F and E are congested at node Tile03, they are queuing and waiting. The delay for transmitting data packet D is 521 clock cycles, the delay for transmitting data packet E is 1039 clock cycles, and the delay for transmitting data packet F is 1557 clock cycles.

[0165] If the data packet transmission method of this embodiment is used to transmit the data packet D, the data packet E, and the data packet F to be transmitted, the transmission path of the data packet D is Tile02→Tile07→Tile12→Tile11 (as shown in Figure D), the transmission path of the data packet E is Tile03→Tile06→Tile13→Tile18→Tile17→Tile16 (as shown in Figure E), and the transmission path of the data packet F is Tile04→Tile03→Tile02→Tile01→Tile06→Tile11→Tile16→Tile21 (as shown in Figure F). The data transmission paths of data packets D, E, and F do not overlap, so there will be no traffic congestion. The delay for transmitting data packet D is 521 clock cycles, the delay for transmitting data packet E is 527 clock cycles, and the delay for transmitting data packet F is 533 clock cycles. Since data packets D, E, and F are transmitted simultaneously, the total delay is 533 clock cycles.

[0166] Without considering other factors, the transmission of data packets D, E, and F in this embodiment reduces latency by (1557-533) / 1557 = 65.77% compared to the transmission of data packets D, E, and F using the traditional XY routing algorithm, which can significantly improve the efficiency of on-chip network data packet transmission.

[0167] Dispatch Management Unit

[0168] Corresponding to the above-described embodiment of the data packet transmission method applied to the scheduling management unit, Figure 8 A schematic diagram of a scheduling management unit according to an embodiment of this application is shown. Figure 8 As shown, the scheduling management unit 21 includes:

[0169] Read subunit 211 is used to determine the source node and destination node of the data packet to be transmitted;

[0170] Planning subunit 212 is used to determine at least one intermediate routing node corresponding to the data packet to be transmitted based on the source node and destination node of the data packet to be transmitted and the data transmission status of each node in the on-chip network.

[0171] The output subunit 213 is used to send the identification information of at least one intermediate routing node to the source node of the data packet to be transmitted, so that the source node of the data packet to be transmitted writes the identification information of at least one intermediate routing node into the header micro-chip of the data packet to be transmitted, so that the data packet to be transmitted is transmitted to each intermediate routing node in sequence according to the XY routing algorithm and then reaches the target node of the data packet to be transmitted.

[0172] In this embodiment, the planning subunit 212 determines at least one intermediate routing node corresponding to the data packet to be transmitted based on the source and destination nodes of the data packet to be transmitted and the data transmission status of each node in the on-chip network. After the output subunit 213 sends the identification information of each intermediate routing node to the source node of the data packet to be transmitted, the source node stores the identification information of each intermediate routing node in the header micro-chip of the data packet to be transmitted. This allows the nodes in the on-chip network to sequentially transmit the data packet to each intermediate routing node according to the XY routing algorithm, and then transmit the data packet to the destination node. Since the intermediate routing nodes are determined based on the data transmission status of each node in the on-chip network, the intermediate routing nodes, as nodes through which the data packet to be transmitted passes, can determine a reasonable transmission path for the data packet to be transmitted, avoid nodes with data traffic congestion, and shorten the time spent transmitting the data packet to the destination node, thereby improving the efficiency of data packet transmission.

[0173] It should be noted that the scheduling management unit in this embodiment is used to implement the data packet transmission method applied to the scheduling management unit in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0174] On-chip network nodes

[0175] Corresponding to the above-described embodiment of the data packet transmission method applied to nodes, Figure 9 A schematic diagram of a node in an embodiment of the on-chip network of this application is shown. Figure 8 As shown, node 22 includes:

[0176] Acquisition subunit 223 is used to acquire the header micro-piece of the data packet to be transmitted, wherein the header micro-piece stores the identification information of at least one intermediate routing node, and the at least one intermediate routing node is determined based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network.

[0177] The transmission subunit 224 is used to transmit the data packet to be transmitted to the intermediate routing nodes according to the identification information of each intermediate routing node stored in the header microchip and the XY routing algorithm, so that the data packet to be transmitted passes through each intermediate routing node in sequence and arrives at the target node.

[0178] In this embodiment, the intermediate routing nodes corresponding to the data packets to be transmitted are determined based on the data transmission status of each node in the on-chip network. As the nodes that the data packets to be transmitted need to pass through during the transmission to the target node, the data packets to be transmitted are transmitted according to the XY routing algorithm when they are transmitted between the source node and the intermediate routing nodes, and between the intermediate routing nodes. Therefore, the intermediate routing nodes can determine the reasonable transmission path of the data packets to be transmitted, avoid the nodes with traffic congestion in the on-chip network, shorten the time spent transmitting the data packets to the target node, and thus improve the efficiency of data packet transmission in the on-chip network.

[0179] It should be noted that the node in this embodiment is used to implement the data packet transmission method applied to the node in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0180] electronic devices

[0181] Figure 10 This is a schematic block diagram of an electronic device provided in an embodiment of this application. Specific embodiments of this application do not limit the specific implementation of the electronic device. Figure 10 As shown, the electronic device may include: a processor 1002, a communications interface 1004, a memory 1006, and a communication bus 1008. Wherein:

[0182] The processor 1002, communication interface 1004, and memory 1006 communicate with each other via communication bus 1008.

[0183] Communication interface 1004 is used to communicate with other electronic devices or servers.

[0184] The processor 1002 is used to execute program 1010, which can specifically execute the relevant steps in any of the aforementioned data packet transmission method embodiments.

[0185] Specifically, program 1010 may include program code that includes computer operation instructions.

[0186] The processor 1002 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0187] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects of microcontrollers and FPGA chips, specifically in areas such as IoT security, industrial control, mobile phones, and personal computers. Because its design considers small size, speed, and low power consumption, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of AIoT (Artificial Intelligence of Things), the RISC-V instruction set architecture is receiving increasing attention and support and is expected to become the next generation of widely used CPU architecture.

[0188] The computer operation instructions in this application embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 1002 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this application embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the data packet transmission method in the above embodiment.

[0189] Memory 1006 is used to store program 1010. Memory 1006 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0190] Specifically, program 1010 can be used to cause processor 1002 to execute the data packet transmission method in any of the foregoing embodiments.

[0191] The specific implementation of each step in program 1010 can be found in the corresponding steps and units described in any of the foregoing data packet transmission method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0192] The electronic device of this application determines at least one intermediate routing node corresponding to the data packet to be transmitted based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network. After sending the identification information of each intermediate routing node to the source node of the data packet to be transmitted, the source node stores the identification information of each intermediate routing node in the header microchip of the data packet to be transmitted. This allows the nodes in the on-chip network to sequentially transmit the data packet to each intermediate routing node according to the XY routing algorithm, and then transmit the data packet to the destination node. Since the intermediate routing nodes are determined based on the data transmission status of each node in the on-chip network, the intermediate routing nodes, as nodes through which the data packet to be transmitted passes, can determine a reasonable transmission path for the data packet to be transmitted, avoid nodes with data traffic congestion, and shorten the time spent transmitting the data packet to the destination node, thereby improving the efficiency of data packet transmission.

[0193] Computer storage media

[0194] This application also provides a computer-readable storage medium storing instructions for causing a machine to perform the data packet transmission method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0195] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of this application.

[0196] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0197] Computer program products

[0198] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0199] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0200] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0201] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0202] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0203] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A data packet transmission method, comprising: Determine the source and destination nodes of the data packets to be transmitted; Based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network, at least one intermediate routing node corresponding to the data packet to be transmitted is determined. The identification information of the at least one intermediate routing node is sent to the source node of the data packet to be transmitted, so that the source node of the data packet to be transmitted writes the identification information of the at least one intermediate routing node into the header micro-part of the data packet to be transmitted, so that the data packet to be transmitted is transmitted to each of the intermediate routing nodes in sequence according to the XY routing algorithm and then reaches the target node of the data packet to be transmitted. Based on the source and destination nodes of the data packet to be transmitted, and the data transmission status of each node in the on-chip network, at least one intermediate routing node corresponding to the data packet to be transmitted is determined, including: Based on the candidate route entries stored in the intermediate routing table, at least one intermediate route node corresponding to the data packet to be transmitted is determined; the source node corresponding to the candidate route entry is the source node of the data packet to be transmitted, and the target node corresponding to the candidate route entry is the target node of the data packet to be transmitted. The candidate route entry includes at least one intermediate route node, and the candidate route entry is determined based on the data transmission status of each node in the on-chip network. The candidate route entry includes a pre-trained traffic-aware model, which obtains a new route entry based on the latency information of each node in the on-chip network, the attribute information of the data packet to be transmitted, and the identification information of the source node and the target node of the data packet to be transmitted. Wherein, the latency information is used to indicate the latency of data packet transmission by each node in the on-chip network, the new route entry includes at least one intermediate route node, the source node corresponding to the new route entry is the source node of the data packet to be transmitted, and the target node corresponding to the new route entry is the target node of the data packet to be transmitted.

2. The method according to claim 1, wherein, The step of determining at least one intermediate routing node corresponding to the data packet to be transmitted based on the candidate route entries stored in the intermediate routing table includes: Check if the intermediate routing table stores at least one alternative route entry; If the intermediate routing table stores at least one of the candidate route entries, then each intermediate route node included in the candidate route entry with the newest update time is determined as at least one intermediate route node corresponding to the data packet to be transmitted.

3. The method according to claim 2, further comprising: If the alternative route entry is not stored in the intermediate routing table, then the latency information of each node in the on-chip network is obtained; The delay information, the attribute information of the data packet to be transmitted, and the identification information of the source node and the destination node of the data packet to be transmitted are input into a pre-trained traffic awareness model to obtain the new route entry output by the traffic awareness model. If the data transmission path corresponding to the newly created route entry does not form a deadlock or livelock with the data transmission path corresponding to the route entry stored in the intermediate routing table, then the newly created route entry is stored in the intermediate routing table. Each intermediate routing node included in the newly created routing entry is identified as at least one intermediate routing node corresponding to the data packet to be transmitted.

4. The method according to claim 3, further comprising: If the data transmission path corresponding to the newly created route entry forms a deadlock or livelock with the data transmission path corresponding to the route entry in the intermediate routing table, a negative stimulus is generated. The delay information, the attribute information of the data packet to be transmitted, the identification information of the source node and the target node of the data packet to be transmitted, and the negative incentive are sent to the server so that the server can train the traffic awareness model through reinforcement learning.

5. The method according to claim 4, further comprising: Receive delay information sent by each node in the on-chip network; The delay information is sent to the server so that the server can train the traffic awareness model through reinforcement learning.

6. The method according to any one of claims 1-5, wherein, If the data packet to be transmitted corresponds to an intermediate routing node, then the intermediate routing node is the target node of the data packet to be transmitted, and the data packet to be transmitted is transmitted from the source node of the data packet to the target node of the data packet according to the XY routing algorithm; If the data packet to be transmitted corresponds to n intermediate routing nodes, where n is a positive integer greater than or equal to 2, then the nth intermediate routing node among the n intermediate routing nodes is the target node of the data packet to be transmitted. The data packet to be transmitted is transmitted from the source node of the data packet to the 1st intermediate routing node among the n intermediate routing nodes according to the XY routing algorithm, and is transmitted from the 1st intermediate routing node among the n intermediate routing nodes to the (i+1)th intermediate routing node among the n intermediate routing nodes according to the XY routing algorithm, where i is a positive integer less than n.

7. A data packet transmission method, comprising: Obtain the header fragment of the data packet to be transmitted, wherein the header fragment stores identification information of at least one intermediate routing node; the at least one intermediate routing node is determined based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network, including intermediate routing nodes determined based on candidate route entries stored in the intermediate routing table, wherein the source node corresponding to the candidate route entry is the source node of the data packet to be transmitted, and the destination node corresponding to the candidate route entry is the destination node of the data packet to be transmitted, and the candidate route entry includes at least one intermediate routing node, the candidate route entry being based on the on-chip network... The data transmission status of each node in the network is determined; the alternative routing entries include a pre-trained traffic-aware model, which obtains new routing entries based on the latency information of each node in the on-chip network, the attribute information of the data packet to be transmitted, and the identification information of the source node and the destination node of the data packet to be transmitted; wherein, the latency information is used to indicate the latency of data packet transmission by each node in the on-chip network, the new routing entry includes at least one intermediate routing node, the source node corresponding to the new routing entry is the source node of the data packet to be transmitted, and the destination node corresponding to the new routing entry is the destination node of the data packet to be transmitted; Based on the identification information of each intermediate routing node stored in the header microchip, the data packet to be transmitted is transmitted to the intermediate routing nodes according to the XY routing algorithm, so that the data packet to be transmitted passes through each intermediate routing node in sequence and arrives at the target node.

8. The method according to claim 7, wherein, The process of obtaining the header fragment of the data packet to be transmitted includes: If the current node is the source node of the data packet to be transmitted, then the identification information of the at least one intermediate routing node from the scheduling management unit is received, and the identification information of the at least one intermediate routing node is written into the header micro-part of the data packet to be transmitted. If the current node is not the source node of the data packet to be transmitted, then the header fragment of the data packet to be transmitted by the upstream node through the XY routing algorithm is received.

9. The method according to claim 8, wherein, The step of writing the identification information of the at least one intermediate routing node into the header micro-fragment of the data packet to be transmitted includes: According to the order requirements of the data packet to be transmitted arriving at each intermediate routing node, the identification information of at least one intermediate routing node is sequentially written into the header micro-part of the data packet to be transmitted, so that the header micro-part of the data packet to be transmitted sequentially stores the identification information of the source node of the data packet to be transmitted and the identification information of at least one intermediate routing node. After receiving the header fragment of the data packet to be transmitted from the upstream node via the XY routing algorithm, the method further includes: The header fragment of the data packet to be transmitted is parsed to obtain the identification information of the source node of the data packet to be transmitted and the identification information of at least one intermediate routing node. Based on the storage order of the identification information of the at least one intermediate routing node, the order requirement for the data packet to be transmitted to arrive at each intermediate routing node is determined.

10. The method according to claim 7, wherein, The step of transmitting the data packet to be transmitted to the intermediate routing nodes according to the XY routing algorithm based on the identification information of each intermediate routing node stored in the header micro-chip includes: Based on the identification information of each intermediate routing node stored in the header micro-chip, determine whether the current node is an intermediate routing node; If the current node is the intermediate routing node and the current node is not the target node of the data packet to be transmitted, then the micro-pieces included in the received data packet to be transmitted are stored in the buffer. After storing each micro-piece of the data packet to be transmitted in the buffer, the micro-pieces of the data packet to be transmitted stored in the buffer are transmitted to the next intermediate routing node according to the XY routing algorithm.

11. The method according to claim 10, further comprising: If the current node is not the intermediate routing node, then the received data packet to be transmitted, including the micro-pieces, is transmitted to the next intermediate routing node according to the XY routing algorithm.

12. The method according to claim 10, further comprising: If the current node is the intermediate routing node, then an invalid identifier is added to the identifier information of the current node stored in the header micro-piece in the buffer. The step of transmitting the data packet to be transmitted to the intermediate routing node according to the XY routing algorithm includes: Based on the order of the identification information stored in the head micro-chip, the next identification information that has not been added with an invalid identifier is determined as the target identification information; According to the XY routing algorithm, the data packet to be transmitted is transmitted to the intermediate routing node identified by the target identification information.

13. A scheduling management unit, comprising: The read sub-unit is used to determine the source and destination nodes of the data packet to be transmitted; The planning subunit is used to determine at least one intermediate routing node corresponding to the data packet to be transmitted based on the source node and destination node of the data packet to be transmitted and the data transmission status of each node in the on-chip network. The output subunit is used to send the identification information of the at least one intermediate routing node to the source node of the data packet to be transmitted, so that the source node of the data packet to be transmitted writes the identification information of the at least one intermediate routing node into the header micro-part of the data packet to be transmitted, so that the data packet to be transmitted is transmitted to each of the intermediate routing nodes in sequence according to the XY routing algorithm and then reaches the target node of the data packet to be transmitted. The planning subunit is further configured to determine at least one intermediate routing node corresponding to the data packet to be transmitted based on the candidate routing entries stored in the intermediate routing table; the source node corresponding to the candidate routing entry is the source node of the data packet to be transmitted, and the target node corresponding to the candidate routing entry is the target node of the data packet to be transmitted; the candidate routing entry includes at least one intermediate routing node, and the candidate routing entry is determined based on the data transmission status of each node in the on-chip network; the candidate routing entry includes a pre-trained traffic-aware model, which obtains a new routing entry based on the delay information of each node in the on-chip network, the attribute information of the data packet to be transmitted, and the identification information of the source node and the target node of the data packet to be transmitted; wherein, the delay information is used to indicate the delay of data packet transmission by each node in the on-chip network, the new routing entry includes at least one intermediate routing node, the source node corresponding to the new routing entry is the source node of the data packet to be transmitted, and the target node corresponding to the new routing entry is the target node of the data packet to be transmitted.

14. A node of an on-chip network, comprising: An acquisition subunit is used to acquire the header micro-piece of a data packet to be transmitted, wherein the header micro-piece stores identification information of at least one intermediate routing node; the at least one intermediate routing node is determined based on the source node and destination node of the data packet to be transmitted, and the data transmission status of each node in the on-chip network, including intermediate routing nodes determined based on candidate routing entries stored in an intermediate routing table, wherein the source node corresponding to the candidate routing entry is the source node of the data packet to be transmitted, and the destination node corresponding to the candidate routing entry is the destination node of the data packet to be transmitted, and the candidate routing entry includes at least one intermediate routing node, the candidate routing entry being based on The data transmission status of each node in the on-chip network is determined; the alternative routing entries include a pre-trained traffic-aware model, which obtains new routing entries based on the latency information of each node in the on-chip network, the attribute information of the data packet to be transmitted, and the identification information of the source node and the destination node of the data packet to be transmitted; wherein, the latency information is used to indicate the latency of data packet transmission by each node in the on-chip network, the new routing entry includes at least one intermediate routing node, the source node corresponding to the new routing entry is the source node of the data packet to be transmitted, and the destination node corresponding to the new routing entry is the destination node of the data packet to be transmitted; The transmission subunit is used to transmit the data packet to be transmitted to the intermediate routing nodes according to the identification information of each intermediate routing node stored in the header microchip, and according to the XY routing algorithm, so that the data packet to be transmitted passes through each intermediate routing node in sequence and arrives at the target node.

15. A chip, comprising: The scheduling management unit according to claim 13; Multiple nodes of the on-chip network according to claim 14.

16. A graphics card, comprising: The chip according to claim 15.

Images