Circuit board and wiring method for circuit board

Abstract

The present disclosure provides a circuit board and a wiring method of the circuit board. The wiring method comprises: obtaining a circuit board model, the circuit board model comprising a plurality of groups of traces, each group of traces comprising at least one first transmission line, the plurality of groups of traces being used to transmit a group of signals and each group of traces being used to transmit one signal in the group of signals; and adjusting a length of the at least one first transmission line to obtain a target circuit board model, a wiring manner in the target circuit board model making a difference between a total transmission delay of any one signal in the group of signals on a corresponding group of traces and a reference time less than or equal to a threshold value. The method can make a plurality of first transmission lines arranged on different layers of the circuit board, making the wiring space and the wiring manner of the traces in the circuit board more flexible, and is particularly suitable for a circuit board with a small number of layers.

Description

Technical Field

[0001] This disclosure relates to the design and manufacture of circuit boards, and more particularly to a circuit board and a wiring method for the circuit board, an electronic device, a means for wiring a circuit board, a computing device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Printed Circuit Boards (PCBs) are crucial components in communication equipment, serving as the support for electronic components and providing electrical connections. High-speed signal transmission on multilayer PCBs typically employs a layer-swapping design, where traces on different layers are connected vias to form an interconnected communication network. Because the lamination structures of each PCB layer are not necessarily identical, and the delays caused by vias of varying effective lengths also differ, signal transmission delays vary across traces and vias on different layers. This is extremely disadvantageous for signal groups with strict delay requirements. Summary of the Invention

[0003] In view of the above, this disclosure provides a circuit board and a wiring method for the circuit board, an electronic device, a means for wiring a circuit board, a computing device, a computer-readable storage medium, and a computer program product that can alleviate, reduce, or even eliminate the above-mentioned problems.

[0004] According to a first aspect of this disclosure, a circuit board is provided, the circuit board including multiple layers and multiple sets of traces, the multiple sets of traces being configured to transmit a set of signals and each set of traces being configured to transmit one signal in the set of signals, wherein the difference between the total transmission delay of any signal in the set of signals on the corresponding set of traces and a reference time is less than or equal to a threshold, the threshold being the delay difference required by the timing rule corresponding to the set of signals. The multiple sets of traces satisfy either of the following two routing methods: each set of traces includes at least one first transmission line, the first transmission lines of at least two sets of traces are located on different layers of the circuit board, and the transmission rate of the signal on the first transmission lines located on at least two different layers of the circuit board is different; or, each set of traces includes N first transmission lines, where N is a positive integer greater than or equal to 2, the N first transmission lines of each set of traces are connected sequentially, and each specific layer of the multiple layers of the circuit board is provided with one of the N first transmission lines of each set of traces, the specific layer being the layer where the N first transmission lines are located, but the routing order of the N first transmission lines of at least one set of traces is different from the routing order of the N first transmission lines of the other sets of traces, and the length of at least one of the N first transmission lines of the at least one set of traces is different from the length of the first transmission lines of the other sets of traces located on the same layer as the at least one first transmission line.

[0005] In some embodiments, the multiple layers of the circuit board include multiple inner layers, the multiple inner layers being the specific layer.

[0006] In some embodiments, each group of traces includes N first transmission lines connected in sequence, and the N first transmission lines are located in different layers of the plurality of inner layers.

[0007] In some embodiments, the circuit board further includes a surface layer among its multiple layers. The first transmission line includes a second transmission line located on the surface layer and a third transmission line located on the inner layer. The second transmission line includes a first fan-out trace and a second fan-out trace. The circuit board also includes multiple vias penetrating the multiple layers. Each set of traces includes a signal input terminal and a signal output terminal. The signal input terminal is connected to the first fan-out trace. The first fan-out trace is connected to one of the multiple vias, which is connected to the third transmission line. The third transmission line is connected to another of the multiple vias, which is connected to the second fan-out trace. The second fan-out trace is connected to the signal output terminal.

[0008] In some embodiments, each set of traces includes a signal input terminal, a signal output terminal, and a first transmission line, wherein the signal input terminal is connected to the signal output terminal via the first transmission line.

[0009] According to a second aspect of this disclosure, an electronic device is provided that includes a circuit board as described in any of the preceding embodiments.

[0010] According to a third aspect of this disclosure, a wiring method for a circuit board is provided, the wiring method comprising: obtaining a circuit board model, the circuit board model including multiple sets of traces, each set of traces including at least one first transmission line; adjusting the length of at least one of the multiple first transmission lines of the multiple sets of traces in the circuit board model to obtain a target circuit board model, wherein the target circuit board model corresponds to the circuit board described in any of the preceding embodiments.

[0011] In some embodiments, adjusting the length of at least one of the multiple first transmission lines in the multiple sets of traces in the circuit board model includes: adjusting the first initial length of the first transmission line corresponding to the target signal based on the transmission delay of the target signal in the set of signals per unit length of the corresponding first transmission line.

[0012] In some embodiments, adjusting the first initial length of the first transmission line corresponding to the target signal based on the transmission delay of the target signal in the set of signals per unit length of the corresponding first transmission line includes: obtaining the initial total transmission delay of each signal in the set of signals on the corresponding set of traces; determining the amount of delay that needs to be adjusted for the initial total transmission delay of each target signal in the set of signals based on multiple initial total transmission delays of the set of signals; obtaining the length value that the first transmission line needs to be adjusted based on the ratio of the amount of delay that needs to be adjusted to the transmission delay of each target signal per unit length of the corresponding first transmission line; and adjusting the first initial length of the first transmission line corresponding to the target signal based on the length value that needs to be adjusted.

[0013] In some embodiments, determining the amount of delay that needs to be adjusted for the initial total transmission delay of each target signal in the set of signals based on a plurality of initial total transmission delays of the set of signals includes: using one of the plurality of initial total transmission delays as the reference time; in response to the initial total transmission delay of the target signal being greater than the reference time and the absolute value of the difference between the two being greater than the threshold, subtracting the reference time and the threshold from the initial total transmission delay to obtain a time difference, and determining the time difference as the amount of delay that needs to be adjusted; in response to the initial total transmission delay of the target signal being less than the reference time and the absolute value of the difference between the two being greater than the threshold, subtracting the initial total transmission delay and the threshold from the reference time to obtain a time difference, and determining the time difference as the amount of delay that needs to be adjusted.

[0014] In some embodiments, obtaining the initial total transmission delay of each signal in the set of signals on the corresponding set of traces includes: obtaining a first transmission delay of each signal in the set of signals on a first transmission line of the corresponding set of traces, and a second transmission delay on a plurality of vias associated with the corresponding set of traces; and obtaining the initial total transmission delay of each signal in the set of signals on the corresponding set of traces based on the sum of the first transmission delay and the second transmission delay.

[0015] In some embodiments, obtaining the first transmission delay of each signal in the set of signals on the first transmission line of the corresponding set of traces includes: determining the transmission delay of each signal in the set of signals on the first transmission line of the corresponding set of traces per unit length; and obtaining the first transmission delay of each signal on the first transmission line of the corresponding set of traces based on the product of the length of the first transmission line of the corresponding set of traces and the transmission delay per unit length of the first transmission line.

[0016] In some embodiments, each group of traces includes a signal input terminal and a signal output terminal, and each group of traces includes a first transmission line. Obtaining the first transmission delay of each signal in the group of traces on the first transmission line of the corresponding group of traces includes: obtaining the initial time required for the signal to travel from the signal input terminal to the signal output terminal based on the first initial length of the first transmission line of each group of traces; obtaining the changed first length of the first transmission line of each group of traces; obtaining the changed first time required for the signal to travel from the signal input terminal to the signal output terminal based on the changed first length; obtaining the transmission delay per unit length of the first transmission line of the group of traces based on the ratio of the difference between the changed first time and the initial time and the difference between the changed first length and the first initial length; and obtaining the first transmission delay of each signal on the first transmission line of the corresponding group of traces based on the product of the length of the first transmission line of the group of traces and the transmission delay per unit length of the first transmission line.

[0017] In some embodiments, each group of traces includes a signal input terminal and a signal output terminal, and each group of traces includes N first transmission lines, which are connected sequentially and located on different layers of the circuit board. The step of obtaining the first transmission delay of each signal in the group of signals on the first transmission line of the corresponding group of traces includes: obtaining the initial time required for the signal to travel from the signal input terminal to the signal output terminal based on the first initial length of the first transmission line of each group of traces; obtaining the modified first length of a target first transmission line among the N first transmission lines of each group of traces; obtaining the modified first time required for the signal to travel from the signal input terminal to the signal output terminal based on the modified first length; and obtaining the modified first time required for the signal to travel from the signal input terminal to the signal output terminal based on the modified first length; and obtaining the modified first time required for the signal to travel from the signal input terminal to the signal output terminal based on the modified first length. The transmission delay of the signal per unit length on the target first transmission line is obtained by comparing the difference between the time and the initial time with the difference between the changed first length and the first initial length; the changed first length is restored to the first initial length; in response to restoring the changed first length of the last target first transmission line in the N first transmission lines of the group of traces to the first initial length, the transmission delay of the signal per unit length on each of the N first transmission lines of the group of traces is obtained; the product of the transmission delay per unit length on each of the N first transmission lines and the length of the first transmission line is summed to obtain the first transmission delay of each signal on the N first transmission lines of the corresponding group of traces.

[0018] In some embodiments, the circuit board includes a surface layer and multiple inner layers. The first transmission line includes a second transmission line located on the surface layer and a third transmission line located on the inner layers. The second transmission line includes a first fan-out trace and a second fan-out trace. The circuit board also includes multiple vias penetrating the multiple layers. Each set of traces includes a signal input terminal and a signal output terminal. The signal input terminal is connected to the first fan-out trace. The first fan-out trace is connected to one of the multiple vias. This via is connected to the third transmission line. The third transmission line is connected to another of the multiple vias. The other via is connected to the second fan-out trace. The second fan-out trace is connected to the signal output terminal.

[0019] In some embodiments, the circuit board includes a surface layer, and each set of traces includes a signal input terminal, a signal output terminal, and a first transmission line located on the surface layer, wherein the signal input terminal is connected to the signal output terminal via the first transmission line.

[0020] According to a fourth aspect of this disclosure, an apparatus for routing circuit boards is provided, the apparatus comprising: an acquisition module configured to acquire a circuit board model, the circuit board model including multiple sets of traces, each set of traces including at least one first transmission line; and a control module configured to adjust the length of at least one of the multiple first transmission lines of the multiple sets of traces in the circuit board model to obtain a target circuit board model, the target circuit board model corresponding to a circuit board described in any of the preceding embodiments.

[0021] According to a fifth aspect of this disclosure, a computing device is provided, comprising: a memory configured to store computer-executable instructions; and a processor configured to perform the wiring method described in any of the preceding embodiments when the computer-executable instructions are executed by the processor.

[0022] According to a sixth aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed, perform the wiring method described in any of the preceding embodiments.

[0023] According to a seventh aspect of this disclosure, a computer program product is provided, including computer-executable instructions that, when executed by a processor, implement the wiring method described in any of the preceding embodiments.

[0024] In the circuit board provided in this disclosure, multiple first transmission lines of multiple sets of traces do not necessarily have to be arranged on the same layer of the circuit board, as in related technologies. Instead, they can be arranged on different layers of the circuit board, while ensuring that the difference between the total transmission delay of each signal in a set of signals and the reference time is less than or equal to a threshold. This is because, although the dielectrics of different layers of the circuit board have different effective dielectric constants, and these different effective dielectric constants result in different transmission delays per unit length on the first transmission lines of different layers, by controlling the length of certain first transmission lines, the signals can have substantially the same total transmission delay in each set of traces, thereby ensuring that the difference between the total transmission delay of each signal in a set of signals and the reference time is less than or equal to a threshold. The circuit board provided in this disclosure can effectively optimize wiring space, making the wiring space and wiring method on the circuit board more flexible.

[0025] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0026] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 The parameters of each layer of a printed circuit board in the related art are shown;

[0028] Figure 2 A schematic diagram of the via structure of a printed circuit board in the related art is shown;

[0029] Figure 3 A flowchart illustrating a circuit board wiring method according to an embodiment of the present disclosure is shown;

[0030] Figure 4 A flowchart illustrating a wiring method for a circuit board according to another embodiment of the present disclosure is shown;

[0031] Figure 5 A wiring structure for a set of traces on a circuit board according to an embodiment of the present disclosure is shown;

[0032] Figure 6 A wiring structure for a set of traces on a circuit board according to an embodiment of the present disclosure is shown;

[0033] Figure 7 The wiring structure of two sets of traces in a circuit board according to an embodiment of the present disclosure is shown;

[0034] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0035] Figure 9 A block diagram of an apparatus for wiring a circuit board according to an embodiment of the present disclosure is shown; and

[0036] Figure 10 A block diagram of a computing device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0037] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] Before detailing the embodiments of this disclosure, some terms used in this application will be explained.

[0039] "Circuit board" can refer to any appropriate circuit board, such as a printed circuit board.

[0040] "Multiple sets of traces" refers to multiple sets of traces used to transmit a set of signals. "Each set of traces" refers to one or more traces used to transmit one signal in a set of signals. Here, "a set of signals" refers to a set of signals with strict delay requirements, such as address signals and clock signals, data signals and data sampling signals, etc.

[0041] "Total transmission delay of a signal on a set of traces" refers to the time it takes for a signal to travel from the signal input terminal to the signal output terminal of that set of traces.

[0042] A "threshold" refers to the delay difference required by timing rules for a set of signals. The specific content of the timing rules depends on the selected chip model. The specific value of the threshold is determined by the clock cycle; for example, the threshold can be on the order of picoseconds or nanoseconds.

[0043] For parallel buses such as DDR (Double Data Rate) and GDDR (Graphics Double Data Rate), there are strict timing requirements for the traces on the printed circuit board. For example, address signals and clock signals are a set of signals, and the total transmission delay difference between them needs to be strictly controlled; similarly, data signals and data sampling signals are a set of signals, and the total transmission delay difference between them also needs to be strictly controlled. Using traces arranged on different layers of the printed circuit board to transmit a set of signals, if certain influencing factors cannot be overcome, will usually result in significant differences in the total transmission delay of each signal in that set. These influencing factors mainly include the following two aspects:

[0044] (1) The structure of each layer of a printed circuit board with multiple stacked layers is usually different. Therefore, the DK value of different layers (DK is the equivalent dielectric constant of the medium wrapped above and below the trace in the printed circuit board. The DK value is related to the thickness and dielectric constant of the medium wrapped above / below the trace) is also different. This will result in different transmission delays of signals per unit length of traces in different layers, or in other words, different transmission rates of signals on traces in different layers. Figure 1 This diagram illustrates some parameters of the various dielectric layers of a printed circuit board with an 8-layer stack-up structure. For example... Figure 1 As shown, when the trace is placed on the top layer of the printed circuit board (the top layer refers to the TOP layer or the 8th layer in the table), the thickness of the dielectric solder mask covering the trace is 1.4 mil, and DK = 3.4; when the trace is placed on the 2nd layer of the printed circuit board, the thickness of the dielectric PP1080 RC63% between the TOP layer and the 2nd layer is 2.72 mil, and DK = 4.09; when the trace is placed on the 3rd layer of the printed circuit board, the thickness of the dielectric CORE 2113×2 between the 2nd and 3rd layers is 8 mil, and DK = 4.27; when the trace is placed on the 4th layer of the printed circuit board, the thickness of the dielectric PP1080 RC67% between the 3rd and 4th layers is 2.8 mil, and DK = 3.98; when the trace is placed on the 5th, 6th, and 7th layers of the printed circuit board, the corresponding dielectric thickness and DK values ​​are as follows. Figure 1 As shown, details will not be described further. The formula for the signal transmission rate on the trace is: (Where C refers to the speed of light in a vacuum, and DK refers to the equivalent dielectric constant of the medium covering the trace above and below, as mentioned above). As mentioned above, different layers of medium have different DK values. Therefore, the transmission rate of signals on traces on different layers is different. For example, the transmission rate of a signal on a trace located on the TOP layer is different from the transmission rate on a trace located on the 3rd layer.

[0045] (2) The signal transmission rate differs within a via (or layer-change via), resulting in varying signal transmission delays. The main factors affecting the transmission delay of a via are as follows:

[0046] I. For the same reason as (1), since vias penetrate multiple layers of a printed circuit board, the DK value of the dielectric surrounding different sections of the via is different along its length, resulting in different signal transmission rates in vias on different layers. For example... Figure 2 As shown, the transmission rate of the signal at different locations in the vias from the TOP layer to the 3rd layer and from the TOP layer to the 5th layer is different because the medium covering the effective area is different.

[0047] II. The effective length of a via is related to the location of the inner layer trace and the thickness of the dielectric. (Combined) Figure 1 From the perspective of the thickness of the medium material Figure 2 The effective length of a via from the top layer to the third layer is much shorter than that from the top layer to the fifth layer. Different effective lengths of vias will also affect the signal transmission rate in the via.

[0048] Related technologies cannot accurately determine the transmission delay per unit length of a signal trace and the transmission delay within a via. To ensure that a set of signals meets the delay difference requirements, all traces used to transmit that set of signals must be placed on the same layer of the printed circuit board to guarantee that the signals have the same transmission rate on the traces and the same transmission delay within the vias. Since the only factor causing the difference in the total transmission delay of different signals is the trace length, ensuring that all traces have the same length is sufficient to meet timing requirements.

[0049] While the above solution can meet the timing requirements of the signals, the cost is that all traces used to transmit a set of signals must be arranged on the same layer of the printed circuit board. This severely reduces the flexibility of the routing method and is especially unsuitable for printed circuit boards with fewer layers (such as 4-layer or 6-layer printed circuit boards), because such low-layer printed circuit boards cannot provide enough routing space to ensure that all traces are arranged on the same layer.

[0050] In order to overcome the above-mentioned defects and some other possible defects in the related technologies, embodiments of this disclosure provide a circuit board wiring method and a circuit board.

[0051] Figure 3 A flowchart of a circuit board wiring method 100 according to an embodiment of the present disclosure is shown. The wiring method 100 includes the following steps:

[0052] 101: Obtain the circuit board model.

[0053] A circuit board model may include at least two layers and at least two sets of traces. Each set of traces includes at least one first transmission line. Multiple sets of traces are used to transmit a set of signals, and each set of traces is used to transmit one signal from that set of signals. The specific method of obtaining the circuit board model is not limited. For example, an appropriate circuit board model can be created based on the physical path of the signal on the circuit board, the layer stack-up, the thickness of each layer, and the actual DK value. The specific representation form of the circuit board model is also not limited; it can be represented in pure data form, pure graphical form, or a combination of data and graphics.

[0054] 102: Adjust the length of at least one of the first transmission lines in the multiple sets of traces in the circuit board model to obtain the target circuit board model. The difference between the total transmission delay of any signal in a set of signals in the target circuit board model and the reference time in the corresponding set of traces is less than or equal to a threshold value, which is the delay difference value required by the timing rules corresponding to the set of signals. The multiple sets of traces in the target circuit board model satisfy any one of the following two routing methods:

[0055] (1) Each group of traces in the multiple groups includes at least one first transmission line, the first transmission lines of at least two groups of traces are located on different layers of the circuit board, and the transmission rates of the signals on the first transmission lines located on at least two different layers of the circuit board are different; or

[0056] (2) Each group of multiple traces includes N first transmission lines, where N is a positive integer greater than or equal to 2. The N first transmission lines of each group of traces are connected sequentially. Each specific layer of the multiple layers of the circuit board is provided with one of the N first transmission lines of each group of traces. The specific layer is the layer where the N first transmission lines are located. However, the routing order of the N first transmission lines of at least one group of traces is different from the routing order of the N first transmission lines of the other groups of traces. Furthermore, the length of at least one of the N first transmission lines of the at least one group of traces is different from the length of the first transmission lines of the other groups of traces that are located on the same layer as the at least one first transmission line.

[0057] Specifically, by adjusting the initial length of the first transmission line in each group of traces, the transmission delay of each group of traces in the circuit board model meets the aforementioned threshold-related requirements. Specifically, this embodiment does not limit how the initial length is adjusted. In one feasible implementation, the transmission delay of the target signal in the group of signals per unit length of the corresponding first transmission line can be determined, and the length of the first transmission line is adjusted based on this transmission delay per unit length. The transmission delay per unit length can be obtained initially or in advance; details will be described later.

[0058] In some embodiments, the routing method for multiple sets of traces in the target circuit board model can be as follows: Figure 5 As shown, Figure 5 The wiring method shown belongs to wiring method (1) above. For the sake of simplicity, Figure 5 Only one set of traces from multiple sets of traces on circuit board 300 is shown. For example... Figure 5As shown, the circuit board 300 has a multi-layer structure, such as a 4-layer, 6-layer, or 8-layer board. The multiple layers of the circuit board 300 include a top layer and multiple inner layers. The top layer refers to the top or bottom layer of the circuit board 300, and the inner layers refer to all layers of the circuit board 300 except the top layer. Each set of traces includes a first transmission line, which includes a transmission line 101. The transmission line 101 can be located on any layer of the circuit board 300, such as any top or inner layer. In the circuit board 300, there are at least two sets of traces whose transmission lines 101 are located on different layers of the circuit board 300, and the signal transmission rates on the transmission lines 101 located on at least two different layers of the circuit board 300 are different. For example, in multiple sets of traces, some sets of transmission lines 101 are located on the k-th layer of the circuit board 300, and other sets of transmission lines 101 are located on the j-th layer of the circuit board 300, where k is not equal to j. Therefore, the signal transmission rate on the transmission line 101 located on the k-th layer is different from the signal transmission rate on the transmission line 101 located on the j-th layer. It should be noted that if the surface materials of the circuit board 300 are the same, a special case can be excluded: that is, the k-th and j-th layers refer to the top and bottom layers of the circuit board 300, respectively (e.g., the k-th layer is the top layer and the j-th layer is the bottom layer, or vice versa). In this case, although k is not equal to j, since the top and bottom layers are made of the same material, the DK value is the same. Therefore, the signal transmission rate on the transmission line 101 located on the top layer is the same as the signal transmission rate on the transmission line 101 located on the bottom layer. The transmission delay of a signal on transmission line 101 is equal to the transmission rate of the signal on transmission line 101 multiplied by the length of transmission line 101. Although the transmission rate of the signal on transmission lines 101 in different layers is different, by adjusting the length of certain transmission lines 101, it can be ensured that the difference between the total transmission delay of the signal on each set of traces and the reference time is less than or equal to the threshold.

[0059] In some embodiments, the routing method for multiple sets of traces in the target circuit board model can be as follows: Figure 6 As shown, Figure 6 The wiring method shown belongs to the wiring method (1) above. For the sake of simplicity, Figure 6 Only one set of traces from multiple sets of traces on circuit board 400 is shown. For example... Figure 6As shown, each group of traces includes a first transmission line, which includes three transmission lines 2011, 2012, and 2013 connected in sequence. Transmission line 2011 can be located on the x-th layer of the circuit board 400, transmission line 2012 can be located on the y-th layer of the circuit board 400, and transmission line 2013 can be located on the z-th layer of the circuit board 400. The values ​​of x, y, and z can be completely different or only partially the same. In the multiple sets of traces on the circuit board 400, at least two sets of traces have their first transmission lines located on different layers of the circuit board 400. Here, "different layers" can include the following situations: the layer where the transmission line 2011 of one set of traces is located is different from the layer where the transmission line 2011 of another set of traces is located, and the layer where the transmission line 2012 of one set of traces is located is different from the layer where the transmission line 2012 of another set of traces is located, and the layer where the transmission line 2013 of one set of traces is located is different from the layer where the transmission line 2013 of another set of traces is located; or, at least one of the three transmission lines 2011, 2012, and 2013 of one set of traces is located is different from the layers where all three transmission lines 2011, 2012, and 2013 of another set of traces are located. The signal transmission delay on the three transmission lines is equal to the signal transmission rate on transmission line 2011 × the length of transmission line 2011 + the signal transmission rate on transmission line 2012 × the length of transmission line 2012 + the signal transmission rate on transmission line 2013 × the length of transmission line 2013. Although the signal transmission rate is different on transmission lines in different layers, by adjusting the length of certain transmission lines, it can be ensured that the difference between the total transmission delay of the signal on each set of lines and the reference time is less than or equal to the threshold.

[0060] In some embodiments, the routing method for multiple sets of traces in the target circuit board model can be as follows: Figure 7 As shown, Figure 7 The wiring method shown belongs to wiring method (2) above. For the sake of brevity, Figure 7 Only two sets of traces from multiple sets of traces on the circuit board are shown. These two sets are trace set A (referred to as group A traces) and trace set B (referred to as group B traces). Figure 7As shown, each group of traces includes a first transmission line, which comprises three sequentially connected transmission lines 2011, 2012, and 2013. The x-th layer of the circuit board contains one of the three transmission lines from each of the multiple groups of traces. For example, the x-th layer of the circuit board contains transmission lines 2011 from group A and 2012 from group B. The y-th layer of the circuit board contains one of the three transmission lines from each of the multiple groups of traces. For example, the y-th layer of the circuit board contains transmission lines 2012 from group A and 2011 from group B. The z-th layer of the circuit board contains one of the three transmission lines from each of the multiple groups of traces. For example, the z-th layer of the circuit board contains transmission lines 2013 from group A and 2013 from group B. It can be seen that although the three transmission lines of group A and group B are respectively arranged on layers x, y, and z, the routing order of the three transmission lines of group A is different from that of group B. This different routing order will result in a difference in the effective via length between group A and group B, i.e., (L via3 +L via4 +L via5 +L via6 )≠(L via3 '+L via4 '+L via5 '+L via6 This can cause the interlayer transmission delay of group A traces to differ from that of group B traces. To prevent the potentially large delay difference caused by these different interlayer transmission delays, the lengths of certain transmission lines can be adjusted so that the length of at least one of the three transmission lines in group A traces is different from the length of the transmission line in group B traces that is located on the same layer as the at least one transmission line. For example, the length L of transmission line 2011 in group A traces located on layer x can be adjusted. x The length L of transmission line 2012 located on layer x, which is connected to group B, is... x 'Different, and / or, the length L of transmission line 2012 located on layer y of group A's routing. y The length L of transmission line 2011 located on layer y, which is connected to group B, is... y 'Different, and / or, the length L of transmission line 2013 located on layer z in group A.' z The length L of transmission line 2013 located on layer z, which is connected to group B, is... z The difference ultimately makes the difference between the total transmission delay of the signal on each set of traces and the reference time less than or equal to the threshold.

[0061] In method 100, by adjusting the length of at least one of the multiple first transmission lines in multiple sets of traces in the circuit board model, the difference between the total transmission delay of any signal in a set of signals on the corresponding set of traces and the reference time is less than or equal to a threshold. This method 100 provides greater flexibility in the routing of the first transmission lines; multiple first transmission lines in multiple sets of traces can be arranged on different layers of the circuit board, instead of having to be arranged on the same layer as in related technologies. This method 100 is particularly advantageous for circuit boards with a limited number of layers (e.g., 4 or 6 layers) because the routing space on such low-layer circuit boards is limited, and the routing space cannot guarantee that all first transmission lines used to transmit a set of signals are arranged on the same layer.

[0062] Figure 4 A flowchart of wiring method 200 is shown. Below, refer to... Figure 4-6 This section will further describe in detail how to route the circuit board so that the difference between the total transmission delay of each signal group and the reference time is less than or equal to a threshold. It should be noted that this article only uses... Figure 5 300 or Figure 6 The circuit board 400 is used to illustrate the various steps of the wiring method 200, but it does not limit the wiring method 200 to only the structure of the circuit board 300 or 400. Based on the embodiments provided in this disclosure, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this disclosure.

[0063] Wiring method 200 includes the following steps.

[0064] 201: Obtain the circuit board model.

[0065] For example, an appropriate model of the circuit board can be established based on the physical path of the signal on the circuit board, the stack-up, the thickness of each layer of the circuit board, and the actual DK value.

[0066] like Figure 5As shown, each group of traces on the circuit board 300 includes a first transmission line, which includes transmission line 101. Transmission line 101 can be located on any layer of the circuit board 300. In some embodiments, the first transmission line may also include a second transmission line located on the surface layer of the circuit board 300, which includes a first fan-out trace 102 and a second fan-out trace 103. When transmission line 101 is located on the same surface layer as the first fan-out trace 102 and the second fan-out trace 103, the first fan-out trace 102, transmission line 101, and second fan-out trace 103 can be directly connected in sequence to form a continuous trace. When transmission line 101 is located on an inner layer of the circuit board 300, transmission line 101 can be referred to as a third transmission line. In this case, the first fan-out trace 102, transmission line 101, and second fan-out trace 103 can be connected sequentially via vias 106 and 107. When transmitting signals, the signal is sequentially transmitted from the signal input terminal of this group of traces through the first fan-out trace 102, via 106, transmission line 101, via 107, and the second fan-out trace 103 to the signal output terminal. The solder ball 104 of the first device can be connected to the signal input terminal, and the solder ball 105 of the second device can be connected to the signal output terminal.

[0067] like Figure 6 As shown, each group of traces on the circuit board 400 includes a first transmission line, which includes a transmission line 2011 located on the x-th layer, a transmission line 2012 located on the y-th layer, and a transmission line 2013 located on the z-th layer. The values ​​of x, y, and z can be completely different or only partially the same. x, y, and z can be any layer of the circuit board 400. In some embodiments, the first transmission line may further include a second transmission line located on the surface layer, which includes a first fan-out trace 202 and a second fan-out trace 203. When transmission lines 2011, 2012, and 2013 are all located on the inner layers of the circuit board 400, transmission lines 2011, 2012, and 2013 can be referred to as a third transmission line. The first fan-out trace 202, transmission lines 2011, 2012, 2013, and second fan-out trace 203 can be connected sequentially via vias 206 to 209. When transmitting signals, the signal is sequentially transmitted from the signal input terminal of this group of traces through the first fan-out trace 202, via 206, transmission line 2011, via 208, transmission line 2012, via 209, transmission line 2013, via 207, and the second fan-out trace 203 to the signal output terminal. The solder ball 204 of the first device can be connected to the signal input terminal, and the solder ball 205 of the second device can be connected to the signal output terminal.

[0068] For example, when the circuit board model is Figure 5 When the circuit board is 300, the effective path of the entire link is: the length L of the first fan-out trace 102. fanout1 +Length L of the second outgoing cable 103 fanout2+Effective length L of via 106 via1 +Effective length L of via 107 via2 +Length L of transmission line 101 k It should be noted that, assuming transmission line 101 is located on layer k of circuit board 300, and the signal changes layer from layer 1 to layer k of circuit board 300 via via 106, then the effective length L of via 106 is... via1 This refers to the length of the segment of via 106 located from layer 1 to layer k. The signal transitions from layer k to layer 1 of the circuit board 300 via via 107; therefore, the effective length L of via 107 is... via2 This refers to the length of the section of via 107 located between layer k and layer 1.

[0069] For example, when the circuit board model is Figure 6 When the circuit board is 400, the effective path of the entire link is: the length L of the first fan-out trace 202. fanout1 +Length L of the second outgoing cable 203 fanout2 +Effective length L of via 206 via3 +Effective length L of via 208 via4 +Effective length L of via 209 via5 +Effective length L of via 207 via6 +Length L of transmission line 2011 x +Length L of transmission line 2012 y +Length L of transmission line 2013 z The effective length L of via 206 via3 The effective length L of via 208 refers to the length of the segment of via 206 located from layer 1 to layer x. via4 This refers to the length of the segment of via 208 located from layer x to layer y, and the effective length L of via 209. via5 The effective length L of via 207 refers to the length of the segment of via 209 located from layer z to layer y. via6 This refers to the length of the segment of via 207 located from layer 1 to layer z. As mentioned earlier, x, y, and z can be any layer of the circuit board 400, either the same layer or completely different layers. If it is the same layer, the corresponding effective via length can be considered as 0. If there are more layer changes, the effective via length and inner layer trace length can be increased accordingly.

[0070] 202: Based on the first initial length of the first transmission line of each group of traces, obtain the initial time T required for the signal to be transmitted from the signal input end to the signal output end.

[0071] In one implementation, the initial time required for a signal to travel from the signal input to the signal output can be simulated using 2.5D or 3D electromagnetic field analysis tools.

[0072] For example, if targeting Figure 5 When the circuit board 300 shown is simulated, the first initial length of the first transmission line is equal to the length L of the first fan-out trace 102. fanout1 +Length L of the second outgoing cable 103 fanout2 The initial length Lk of the transmission line 101 and the initial time T required for the signal to be transmitted from the solder ball 104 of the first device to the solder ball 105 of the second device are given.

[0073] For example, if targeting Figure 6 When the circuit board 400 shown is simulated, the first initial length of the first transmission line is equal to the length L of the first fan-out trace 202. fanout1 +Length L of the second outgoing cable 203 fanout2 + Initial length Lx of transmission line 2011 + Initial length L of transmission line 2012 y + Initial length L of transmission line 2013 z The initial time required for the signal to be transmitted from the solder ball 204 of the first device to the solder ball 205 of the second device is T.

[0074] 203: Obtain the transmission delay of the signal per unit length on each first transmission line.

[0075] Accordingly, in one feasible implementation, the propagation delay per unit length of each first transmission line can be obtained using, for example, 2.5D or 3D electromagnetic field analysis tools. If for... Figure 5 If the circuit board 300 shown is simulated, then step 203 may include the following sub-steps:

[0076] In the model, the length of transmission line 101 is changed to obtain the changed length L of transmission line 101. k ′;

[0077] Based on the changed length L k ′, to obtain the altered first time T1 required for the signal to be transmitted from the solder ball 104 of the first device to the solder ball 105 of the second device;

[0078] Based on the difference between the changed first time T1 and the initial time T, and the changed length L k ′ and initial length L k The ratio of the differences is used to obtain the signal propagation delay T per unit length on the transmission line 101. k-unit That is, T k-unit =(T1-T) / (L) k ′-L k );

[0079] Restore the length of transmission line 101 to its initial length L.k .

[0080] By performing the above steps on each transmission line 101 of the multiple sets of traces, the transmission delay of the signal per unit length of each transmission line 101 can be obtained. As mentioned earlier, the dielectrics on different layers of the circuit board have different DK values, and different DK values ​​will cause the signal to have different transmission rates on the traces on different layers. Therefore, if the transmission lines 101 of the multiple sets of traces are located on different layers of the circuit board 300, the transmission delay T of the signal per unit length of each transmission line 101 will be... k-unit They may be different.

[0081] For example, if targeting Figure 6 If the circuit board 400 shown is simulated, then step 203 may include the following sub-steps:

[0082] In the model, the length of transmission line 2011 is changed to obtain the changed length L of transmission line 2011. x ;

[0083] Based on the changed length L x ′, to acquire the altered first time T required for the signal to be transmitted from solder ball 204 of the first device to solder ball 205 of the second device. 1x ;

[0084] Based on the changed first time T 1x The difference from the initial time T and the changed length L x ′ and initial length L x The ratio of the differences is used to obtain the transmission delay T of the signal per unit length on transmission line 2011. x-unit That is, T x-unit =(T 1x -T) / (L x ′-L x );

[0085] Restore the length of transmission line 2011 to its initial length L. x ;

[0086] In the model, change the length of transmission line 2012 to obtain the changed length L of transmission line 2012. y ′;

[0087] Based on the changed length L y ′, to acquire the altered first time T required for the signal to be transmitted from solder ball 204 of the first device to solder ball 205 of the second device. 1y ;

[0088] Based on the changed first time T 1y The difference from the initial time T and the changed length Ly ′ and initial length L y The ratio of the differences is used to obtain the transmission delay T of the signal per unit length on transmission line 2012. y-unit That is, T y-unit =(T 1y -T) / (L y ′-L y );

[0089] Restore the length of transmission line 2012 to its initial length L. y ;

[0090] In the model, the length of transmission line 2013 is changed to obtain the changed length L of transmission line 2013. z ′;

[0091] Based on the changed length L z ′, to acquire the altered first time T required for the signal to be transmitted from solder ball 204 of the first device to solder ball 205 of the second device. 1z ;

[0092] Based on the changed first time T 1z The difference from the initial time T and the changed length L z ′ and initial length L z The ratio of the differences is used to obtain the transmission delay T of the signal per unit length on transmission line 2013. z-unit That is, T z-unit =(T 1z -T) / (L z ′-L z );

[0093] Restore the length of transmission line 2013 to its initial length L. z .

[0094] By performing the above steps on transmission lines 2011-2013 of each of the multiple sets of traces, the transmission delay per unit length of each transmission line in each set of traces can be obtained. As mentioned earlier, the dielectrics on different layers of the circuit board have different DK values, and different DK values ​​will cause the signal to have different transmission rates on the traces on different layers. Therefore, if transmission lines 2011-2013 are located on different layers of the circuit board 400, then T x-unit Ty- unit T z-unit The values ​​may be different from each other.

[0095] If there is more Figure 6 If the model is layered multiple times, the above sub-steps can be repeated until the transmission delay of the signal per unit length of each transmission line is calculated.

[0096] As mentioned above, the first transmission line may further include a second transmission line located on the surface, namely the first sector outgoing line and the second sector outgoing line. Step 203, acquiring the signal transmission delay per unit length on each of the first transmission lines, may also include acquiring the signal transmission delay per unit length on each of the second transmission lines. Acquiring the signal transmission delay per unit length on each of the second transmission lines may include the following sub-steps, which are applicable to… Figure 5 Circuit board 300 and Figure 4 Circuit board 400:

[0097] In the model, the length of the second transmission line is changed to obtain the changed length (L) of the second transmission line. fanout1 +L fanout2 )';

[0098] Based on the changed length (L) fanout1 +L fanout2 )', to obtain the altered second time T2 required for the signal to be transmitted from the solder ball of the first device to the solder ball of the second device;

[0099] Based on the difference between the changed second time T2 and the initial time T and the changed length (L) fanout1 +L fanout2 )' and initial length (L) fanout1 +L fanout2 The ratio of the differences is used to obtain the transmission delay T of the signal per unit length on the second transmission line. outer-unit That is, T outer-unit =(T2-T) / {(L fanout1 +L fanout2 )'-(L fanout1 +L fanout2 )}.

[0100] By performing the above steps on the second transmission line of each of the multiple sets of traces, the transmission delay of the signal per unit length on the second transmission line of each set of traces can be obtained.

[0101] As mentioned earlier, the second transmission line can be either a top-layer or bottom-layer trace on the circuit board. Since the dielectric material and board thickness are the same on both the top and bottom layers, the transmission delay per unit length is the same for both top-layer and bottom-layer traces. Furthermore, since the second transmission line includes both a first-fan outgoing trace and a second-fan outgoing trace, the signal transmission delay T per unit length on the second transmission line is the same. outer-unit It is equal to the transmission delay of the signal per unit length on the first outgoing line, and also equal to the transmission delay of the signal per unit length on the second outgoing line.

[0102] Step 203 allows for precise determination of the signal propagation delay per unit length on each first transmission line. Since different layers of the medium have different DK values, and these different DK values ​​result in different transmission rates on the traces of different layers, the signal propagation delay per unit length on the first transmission lines of different layers may vary. Because the first transmission line is a component of each group of traces, and each group of traces is used to transmit one signal from a group of signals with strict delay requirements, precisely controlling the signal propagation delay per unit length on each first transmission line is beneficial for precisely controlling the total signal propagation delay on each group of traces.

[0103] It should be noted that the transmission delay per unit length at each layer obtained through the above method can be stored after calculation. Correspondingly, the DK value or unique identifier (e.g., medium representation) of the corresponding layer can be stored. This allows for direct retrieval of the stored transmission delay when the DK value or unique identifier of a particular layer is identified during subsequent use, avoiding redundant calculations. Furthermore, it should be noted that the above method for calculating transmission delay is only one feasible implementation, and the calculation method for transmission delay is not limited to the above approach.

[0104] 204: Obtain the signal propagation delay on the multiple vias associated with each group of traces.

[0105] For example, if targeting Figure 5 If the circuit board 300 shown is simulated, then step 204 may include the following sub-steps:

[0106] Based on the length L of transmission line 101 k The transmission delay T of the signal per unit length on the transmission line 101 k-unit The product of L and L is used to obtain the first transmission delay of the signal on transmission line 101, that is, the first transmission delay is equal to L. k ×T k-unit ;

[0107] Based on the length L of the first outgoing line 102 fanout1 The length L of the second outgoing cable 103 fanout2 The sum of these values ​​and the transmission delay T per unit length of the signal on the first outgoing line 102 and the second outgoing line 103 are given. outer-unit The product of L and L is used to obtain the third transmission delay of the signal on the first outgoing line 102 and the second outgoing line 103, that is, the third transmission delay is equal to (L). fanout1 +L fanout2 )×T outer-unit ;as well as

[0108] Subtract the first propagation delay and the third propagation delay from the initial time T required for the signal to travel from the solder ball 104 of the first device to the solder ball 105 of the second device, thereby obtaining the second propagation delay T of the signal on the vias 106 and 107 associated with this set of traces. via-300 =TL k ×T k-unit -(L fanout1 +L fanout2 )×T outer-unit In terms of the total transmission delay of the entire physical link, the transmission delay of the vias associated with each group of traces can be considered as a whole.

[0109] By performing the above steps on the vias involved in each of the multiple sets of traces, the second transmission delay of the signal on the multiple vias associated with each set of traces can be obtained.

[0110] For example, if targeting Figure 6 If the circuit board 400 shown is simulated, then step 204 may include the following sub-steps:

[0111] Based on the length L of transmission line 2011 x The transmission delay T of the signal per unit length on the transmission line 2011 x-unit The product of the two, the length L of the transmission line 2012 y The transmission delay T of the signal per unit length on the transmission line 2012 y-unit The product of, and the length L of transmission line 2013 z The transmission delay T of the signal per unit length on the transmission line 2013 z-unit The sum of the products of the three factors is used to obtain the first transmission delay of the signal on transmission lines 2011-2013, that is, the first transmission delay is equal to L. x ×T x-unit +L y ×T y- u nit +L z ×T z-unit ;

[0112] Based on the length L of the first outgoing line 202 fanout1 The length L of the second outgoing cable 203 fanout2 The sum of these two values ​​is the transmission delay T per unit length of the signal on the first outgoing line 202 and the second outgoing line 203. outer-unit The product of L and L is used to obtain the third transmission delay of the signal on the first outgoing line 202 and the second outgoing line 203, that is, the third transmission delay is equal to (L). fanout1 +L fanout2 )×T outer-unit ;as well as

[0113] Subtract the first propagation delay and the third propagation delay from the initial time T required for the signal to travel from the solder ball 204 of the first device to the solder ball 205 of the second device, thereby obtaining the second propagation delay of the signal on the vias 206-209 associated with this set of traces, i.e., T. via-400 =T-(L x ×T x-unit +L y ×T y-unit +L z ×T z-unit )-(L fanout1 +L fanout2 )×T outer-unit .

[0114] By performing the above steps on the vias involved in each of the multiple sets of traces, the second transmission delay of the signal on the multiple vias associated with each set of traces can be obtained.

[0115] As mentioned earlier, the main causes of signal transmission delay include two parts: the transmission delay of the signal on different layers and the transmission delay of the signal on vias. The transmission delay on different layers is related to the DK value of the dielectric, while the transmission delay on vias is related to the DK value of the dielectric surrounding the via and the effective length of the via. Step 203 accurately obtains the transmission delay per unit length of each first transmission line; step 204 accurately obtains the transmission delay of the signal on several vias involved in the physical transmission path. Precise control of the transmission delay per unit length of each first transmission line and the transmission delay on several vias facilitates accurate determination of the total transmission delay of the signal on each set of traces.

[0116] 205: Obtain the initial total transmission delay for each signal in a set of signals.

[0117] Having obtained the first transmission delay, second transmission delay, and third transmission delay of the signal through step 204, the initial total transmission delay T of each signal in the group of signals is then determined. x = First transmission delay + Second transmission delay + Third transmission delay. Due to factors such as the different number of routing layers, dielectric constants of the dielectric materials, and effective lengths of vias for each signal's corresponding set of traces, the first, second, and third transmission delays of each signal may differ from each other or at least partially differ, resulting in an initial total transmission delay T for each signal in a set of signals. x There may be some differences between them.

[0118] Through steps 201-205 above, the delay of any signal in the set of signals whose timing needs to be controlled, as well as the total transmission delay, is accurately obtained at each part of the physical path. Then, the circuit board wiring structure can be adjusted through steps 206-208 below, so that signals not routed on the same layer can still accurately meet the transmission delay difference requirements.

[0119] 206: Identify the target signals whose initial total transmission delay differs from the reference time by a threshold value and the amount of delay Δt that needs to be adjusted for the initial total transmission delay of each target signal.

[0120] Step 205 has calculated the initial total transmission delay for each signal in the set of signals. In some embodiments, the initial total transmission delay of a signal in the set of signals can be determined as the reference time target. Ideally, the absolute value of the difference between the initial total transmission delay of each other signal in the set and the target should be less than or equal to a threshold y. The units of target and y can be, for example, picoseconds or nanoseconds, and the specific value of y can be determined according to the actual situation. However, as mentioned earlier, the routing of different layers will cause the signal to transmit at different rates on the routing. Therefore, there will always be one or more target signals in the set of signals whose absolute value of the difference between the initial total transmission delay and the reference time target is greater than the threshold y. The initial total transmission delay T of the target signal... 目标 When the time is greater than the baseline time target and the absolute value of the difference between the two is greater than the threshold y, i.e., T 目标 -target>y, from the initial total transmission delay T 目标 Subtract the reference time target and the threshold y to obtain the time difference, and determine the amount of delay Δt that needs to be adjusted for the initial total transmission delay of each target signal. Alternatively, in the initial total transmission delay T of the target signal... 目标 When the target time is small and the absolute value of the difference between the two is greater than the threshold y, i.e., target-T 目标 >y, subtract the initial total transmission delay T from the reference time target. 目标 The time difference is obtained by using a threshold y, and this time difference is determined as the amount of delay Δt that needs to be adjusted for the initial total transmission delay of each target signal.

[0121] In an alternative embodiment, the reference time target may not be the initial total transmission delay of any one of the signals in a set of signals, but may be a pre-set or selected reference value as the reference time target.

[0122] 207: Based on the required adjustment of the delay Δt and the transmission delay T of each target signal per unit length on the corresponding first transmission line. j-unitThe ratio of ΔL and T is used to obtain the length value ΔL that the first transmission line needs to be adjusted. j-unit This refers to the transmission delay per unit length of the first transmission line located on the j-th layer of the circuit board.

[0123] Δt=ΔL×T j-unit Since Δt is a known quantity, and T j-unit As learned in the previous step 203, ΔL can be calculated using this formula. ΔL refers to the length of the first transmission line corresponding to any target signal in a set of signals that does not meet the delay difference requirement.

[0124] 208: Based on the length value that needs to be adjusted, adjust the first initial length of the first transmission line corresponding to those target signals.

[0125] Based on ΔL obtained in step 207, the lengths of the first transmission lines corresponding to target signals that do not meet the delay difference requirements are adjusted so that the difference between the total transmission delay of each signal and the reference time target is less than or equal to the threshold y. In other words, to allow multiple sets of first transmission lines to be arranged on different layers of the circuit board, the lengths of some first transmission lines need to be adjusted to compensate for the differences in delay caused by the different layer positions. This allows for flexible routing of the first transmission lines on the circuit board while ensuring that the total transmission delay of each signal in a set of signals meets the requirements.

[0126] Steps 206-208 above can be described using an example. In this example, the multiple sets of traces used to transmit a set of signals with strict delay requirements can be divided into two categories. In the first category, the transmission lines of each set of traces are arranged on the inner layer of the circuit board (e.g., layer j), and the physical path involved in the signal transmitted by this set of traces includes the second transmission line on the surface layer, vias, and the transmission line on the inner layer. In the second category, the first transmission line of each set of traces is arranged on the top layer of the circuit board, and the physical path involved in the signal transmitted by this set of traces only includes the first transmission line on the top layer. Simulating a set of traces in the first category, the transmission delay T per unit length of the transmission line of this set of traces can be obtained according to step 203. j-unit And the signal propagation delay T per unit length on the second transmission line on the surface of this group of traces. outer-unit According to step 204, the signal propagation delay T on the via associated with the group of traces can be obtained. via-j .

[0127] The lengths of each trace in each group can be obtained through measurement. For example, for the first type of trace group, the measured length of the second transmission line on the surface layer is denoted as L1, and the measured length of the transmission line on the j-th layer is denoted as L... jTherefore, according to the method in step 205 above, the initial total transmission delay T of the signal on each group of traces in the first type of trace group is... x =L1×T outer-unit +T via-j +L j ×T j-unit Because of the L1 and L2 groups of the first type of wiring group... j They may differ from each other, therefore the initial total propagation delay T of the signals corresponding to each group of traces is different. x They may also differ from each other. For the second type of trace group, the measured length of the first transmission line located on the top layer is denoted as L. top Since the transmission delay per unit length of the first transmission line at the top layer is equal to the transmission delay per unit length of the second transmission line at the surface layer, according to the method in step 205 above, the initial total transmission delay T of the signal on each group of traces in the second type of trace group is... x =L top ×T outer-unit The L-shaped traces in each group of the second type of trace group. top They may differ from each other, therefore the initial total propagation delay T of the signals corresponding to each group of traces is different. x They may also be different from each other.

[0128] Through the above steps, the initial total transmission delay of each signal in the group can be obtained. Taking the initial total transmission delay of any signal in the group as the target, the difference between the initial total transmission delay of the remaining signals in the group and the target is required to be less than or equal to y. Identify those target signals that do not meet this range, and obtain Δt according to step 206. For signals corresponding to the first type of trace group, Δt should satisfy Δt = ΔL × T. j-unit Due to Δt and T j-unit Since everything is known, the required length ΔL for the transmission line at layer j can be calculated. Then, based on this ΔL, the length of the transmission line in each group of traces is adjusted so that the difference between the total transmission delay of the signal transmitted in each group of traces and the reference time target is less than or equal to the threshold y. For signals corresponding to the second type of trace group, Δt = ΔL × T should be satisfied. outer-unit Due to Δt and T outer-unit Since everything is known, the length ΔL that the first transmission line at the top layer needs to be increased or decreased can be calculated. Then, based on this ΔL, the length of the first transmission line of each group of traces is adjusted so that the difference between the total transmission delay of the signal transmitted by each group of traces and the reference time target is less than or equal to the threshold y.

[0129] In the method 200 provided in this disclosure, factors such as the influence of dielectrics with different dielectric constants and thicknesses on the signal transmission rate on the traces, and the influence of vias with different effective lengths on the signal transmission rate are taken into account. The transmission delay per unit length of the signal on the first transmission line on different layers and the transmission delay of the signal on multiple vias associated with each group of traces are accurately calculated. Based on these parameters, the total transmission delay of each signal in a group of signals can be accurately obtained. By comparing the total transmission delay of each signal and adjusting the length of the first transmission line corresponding to those target signals that do not meet the delay difference requirement, the total transmission delay of each signal can be precisely controlled so that the difference between each signal and the reference time target is less than or equal to a threshold y. Therefore, this method 200 not only ensures that the total transmission delay of each signal meets the requirements, but also allows the first transmission lines to be arranged on different layers of the circuit board, achieving flexibility in routing methods and routing space.

[0130] It should be noted that although this application uses a circuit board including layer-changing vias as an example, the circuit board structure described in this application and the method for controlling the signal transmission delay difference of the circuit board are also applicable to circuit boards with HDI (High Density Interconnector) designs. In HDI circuit boards, trace layer changing is achieved through microvias and / or buried vias. Similar to layer-changing vias, the signal transmission rate in microvias and / or buried vias on different layers is also different.

[0131] Embodiments of this disclosure provide a circuit board including multiple layers and multiple sets of traces. The multiple sets of traces are used to transmit a set of signals, and each set of traces is used to transmit one signal from the set of signals. The difference between the total transmission delay of any signal in the set of signals on the corresponding set of traces and a reference time is less than or equal to a threshold value, which is the delay difference value required by the timing rules corresponding to the set of signals. The multiple sets of traces satisfy any one of the following two routing methods:

[0132] (1) Each group of traces in the multiple groups includes at least one first transmission line, the first transmission lines of at least two groups of traces are located on different layers of the circuit board, and the transmission rates of the signals on the first transmission lines located on at least two different layers of the circuit board are different; or

[0133] (2) Each group of multiple traces includes N first transmission lines, where N is a positive integer greater than or equal to 2. The N first transmission lines of each group of traces are connected sequentially. Each specific layer of the multiple layers of the circuit board is provided with one of the N first transmission lines of each group of traces. The specific layer is the layer where the N first transmission lines are located. However, the routing order of the N first transmission lines of at least one group of traces is different from the routing order of the N first transmission lines of the other groups of traces. Furthermore, the length of at least one of the N first transmission lines of the at least one group of traces is different from the length of the first transmission lines of the other groups of traces that are located on the same layer as the at least one first transmission line.

[0134] Figure 5 A partial structural schematic diagram of circuit board 300 is shown. In this example, each group of traces includes a first transmission line. Circuit board 300 has a multi-layer structure, such as a 4-layer board, a 6-layer board, an 8-layer board, etc. Figure 5 As shown, the first transmission line includes transmission line 101. The first transmission line may also include a second transmission line located on the surface layer. The second transmission line includes a first outgoing trace 102 and a second outgoing trace 103. Transmission line 101 is located on any of the inner layers of the circuit board 300 other than the surface layer. "Surface layer" can refer to the top or bottom layer of the circuit board 300. Figure 5 Taking the second transmission line located on the top layer of circuit board 300 as an example, in an alternative embodiment, the second transmission line may also be located on the bottom layer of circuit board 300. Since the top and bottom layers of the circuit board have the same dielectric, the second transmission line located on the top or bottom layer of circuit board 300 has the same equivalent dielectric constant.

[0135] like Figure 5 As shown, each set of traces is equipped with two vias 106 and 107. The solder ball 104 of the first device is connected to the first fan-out trace 102 via the signal input terminal. The first fan-out trace 102 is connected to the via 106, which is connected to the transmission line 101. The transmission line 101 is connected to the via 107, which is connected to the second fan-out trace 103. The second fan-out trace 103 is connected to the solder ball 105 of the second device via the signal output terminal, thus forming a complete physical path for signal transmission. When transmitting a signal, the signal starts from the solder ball 104, passes sequentially through the first fan-out trace 102, via 106, transmission line 101, via 107, and the second fan-out trace 103, and finally reaches the solder ball 105, thereby realizing the transmission of the signal from the solder ball 104 of the first device to the solder ball 105 of the second device.

[0136] In some embodiments, the connection between the solder ball 104 of the first device and the first fan-out trace 102 may include the following: the solder ball 104 of the first device is connected to a first pad of the circuit board 300, and the first pad is connected to the first fan-out trace 102. In some embodiments, the connection between the second fan-out trace 103 and the solder ball 105 of the second device may include the following: the second fan-out trace 103 is connected to a second pad of the circuit board 300, and the second pad is connected to the solder ball 105 of the second device.

[0137] In some alternative embodiments, the first transmission line of each group of traces includes only one surface trace and no inner traces, and no vias are required. In such an embodiment, the solder ball 104 of the first device is connected to the surface trace, which is connected to the solder ball 105 of the second device, thereby enabling signal transmission from the solder ball of the first device to the solder ball of the second device.

[0138] In one embodiment, multiple sets of traces are divided into two categories. One category of first transmission lines is arranged on the surface layer (e.g., the top layer) of the circuit board 300, while the other category is arranged on the third layer of the circuit board 300. This allows the first transmission lines to be arranged on different layers of the circuit board 300, thereby achieving flexibility in the routing method. This is particularly advantageous when the circuit board 300 has a small number of layers (e.g., 4 or 6 layers), because the routing space of such a low-layer circuit board 300 is limited, making it impossible to guarantee that the traces used to transmit a set of signals are arranged on the same layer. By arranging each first transmission line in at least two different layers of the circuit board 300, the routing space is greatly optimized, making the routing space and routing method of the traces in the circuit board 300 more flexible, while ensuring that the difference between the total transmission delay of each signal in a set of signals and the reference time is less than or equal to a threshold.

[0139] Figure 6 A partial structural schematic diagram of circuit board 400 is shown. In this example, circuit board 400 has a multi-layer structure, such as a 4-layer board, a 6-layer board, an 8-layer board, etc. Figure 6 As shown, each group of traces includes a first transmission line, which includes three transmission lines 2011, 2012, and 2013. In some embodiments, the first transmission line may also include a second transmission line located on the surface of the circuit board 400, which includes a first outgoing trace 202 and a second outgoing trace 203.

[0140] Transmission line 2011 may be located on layer x of circuit board 400, transmission line 2012 may be located on layer y of circuit board 400, and transmission line 2013 may be located on layer z of circuit board 400. Layer x, layer y, and layer z may be any one of multiple layers of circuit board 400. In some embodiments, x, y, and z may be completely different values. For example, transmission line 2011 may be located on layer 4 of circuit board 400, transmission line 2012 may be located on layer 2 of circuit board 400, and transmission line 2013 may be located on layer 3 of circuit board 400. In alternative embodiments, the values ​​of x, y, and z may be partially the same. For example, transmission line 2011 may be located on layer 3 of circuit board 400, transmission line 2012 may be located on layer 2 of circuit board 400, and transmission line 2013 may be located on layer 3 of circuit board 400. In another alternative embodiment, the values ​​of x, y, and z may be completely the same. For example, transmission lines 2011, 2012, and 2013 may all be located on layer 3 of circuit board 400.

[0141] like Figure 6 As shown, each group of traces is equipped with four vias. The solder ball 204 of the first device is connected to the first pad 210 via the signal input terminal. The first pad 210 is connected to the first fan-out trace 202. The first fan-out trace 202 is connected to the via 206. The via 206 is connected to the transmission line 2011 located on the x-th layer. The transmission line 2011 is connected to the via 208. The via 208 is connected to the transmission line 2012 located on the y-th layer. The transmission line 2012 is connected to the via 209. The via 209 is connected to the transmission line 2013 located on the z-th layer. The transmission line 2013 is connected to the via 207. The via 207 is connected to the second fan-out trace 203. The second fan-out trace 203 is connected to the second pad 211. The second pad 211 is connected to the solder ball 205 of the second device via the signal output terminal, thus forming a complete physical path for signal transmission. When transmitting signals, the signal starts from solder ball 204, passes through several traces and vias in sequence, and is finally transmitted to solder ball 205, thereby realizing the transmission of the signal from solder ball 204 of the first device to solder ball 205 of the second device.

[0142] In circuit board 400, transmission lines 2011-2013 and second transmission lines 202-203 can be arranged on at least two different layers of circuit board 400, without having to arrange all traces on the same layer of the circuit board to control delay differences, as is the case in related technologies. This greatly optimizes the routing space, making the routing space and routing method of traces in circuit board 400 more flexible, while ensuring that the difference between the total transmission delay of each signal in a set of signals and the reference time is less than or equal to a threshold. This is particularly advantageous for lower-layer circuit boards with extremely limited routing space.

[0143] Figure 7The diagram shows a partial structure of another circuit board. For simplicity, only two sets of traces from the multiple sets of traces on the board are shown: one set of traces A (referred to as set A traces) and another set of traces B (referred to as set B traces). Figure 7 As shown, each group of traces includes a first transmission line, which includes three sequentially connected transmission lines 2011, 2012, and 2013. In some embodiments, the first transmission line may further include a second transmission line located on the surface layer of the circuit board, which includes a first outgoing trace 202 and a second outgoing trace 203. The x-th layer of the circuit board is arranged with one of the three transmission lines from each of the multiple groups of traces; for example, the x-th layer of the circuit board has transmission lines 2011 from group A and 2012 from group B. The y-th layer of the circuit board is arranged with one of the three transmission lines from each of the multiple groups of traces; for example, the y-th layer of the circuit board has transmission lines 2012 from group A and 2011 from group B. The z-th layer of the circuit board is arranged with one of the three transmission lines from each of the multiple groups of traces; for example, the z-th layer of the circuit board has transmission lines 2013 from group A and 2013 from group B. It can be seen that although the three transmission lines of both group A and group B are arranged on layers x, y, and z respectively, the routing order of the three transmission lines in group A is different from that in group B. This different routing order will result in a difference in the effective via length between group A and group B, i.e., (L... via3 +L via4 +L via5 +L via6 )≠(L via3 '+L via4 '+L via5 '+L via6 This causes the interlayer transmission delay of group A traces to differ from that of group B traces. To prevent the potentially large delay difference caused by these different interlayer transmission delays, the length of at least one of the three transmission lines in group A traces is different from the length of the transmission line in group B traces that is located on the same layer as the at least one transmission line. For example, the length L of transmission line 2011 in group A traces located on layer x is different. x The length L of transmission line 2012 located on layer x, which is connected to group B, is... x 'Different, and / or, the length L of transmission line 2012 located on layer y of group A's routing. y The length L of transmission line 2011 located on layer y, which is connected to group B, is... y 'Different, and / or, the length L of transmission line 2013 located on layer z in group A.' z The length L of transmission line 2013 located on layer z, which is connected to group B, is... z'Different.' Through this wiring method, the difference between the total transmission delay of the signal on each set of traces and the reference time can be less than or equal to a threshold.

[0144] Figure 8 Example block diagrams of electronic devices 500 according to some embodiments of the present disclosure are shown. Electronic device 500 includes a circuit board described in any of the preceding embodiments. The electronic device 500 can be any suitable type of electronic device, such as a consumer electronics product including integrated circuits, a motherboard of a household appliance, industrial equipment, etc.

[0145] The electronic device 500 can have essentially the same technical effects as the circuit board described in the previous embodiments. For the sake of brevity, the technical effects of the electronic device 500 will not be described again here.

[0146] Figure 9 An apparatus 600 for routing a circuit board is shown. The apparatus 600 includes: an acquisition module 602 configured to acquire a model of a circuit board, the circuit board including multiple layers and multiple sets of traces, each set of traces including at least one first transmission line; and a control module 604 configured to adjust the length of at least one of the multiple first transmission lines of the multiple sets of traces in the circuit board model to obtain a target circuit board model, the target circuit board model corresponding to the circuit board described in any of the preceding embodiments, such as circuit board 300 or 400.

[0147] It should be noted that the various modules described above can be implemented in software, hardware, or a combination of both. Multiple different modules can be implemented within the same software or hardware architecture, or a single module can be implemented by multiple different software or hardware architectures.

[0148] The technical effects of device 600 can be referred to the technical effects of method 200, and will not be repeated here for the sake of brevity.

[0149] Figure 10 A schematic block diagram of a computing device 700 according to an embodiment of the present disclosure is shown.

[0150] like Figure 10 As shown, computing device 700 includes a processing system 702 communicatively coupled to each other, one or more computer-readable media 708, and one or more I / O interfaces 706. Although not shown, computing device 700 may also include a system bus or other data and command transfer system that couples the various components to each other. The system bus may include any or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of a variety of bus architectures, or may include control and data lines.

[0151] Processing system 702 represents the functionality of performing one or more operations using hardware. Therefore, processing system 702 is illustrated as including hardware elements 704 that can be configured as processors, function blocks, etc. This may include application-specific integrated circuits (ASICs) or other logic devices formed using one or more semiconductors implemented in the hardware. Hardware element 704 is not limited by its forming material or the processing mechanism employed therein. For example, a processor may consist of semiconductors and / or transistors (e.g., integrated circuits (ICs)). In such a context, processor-executable instructions may be electronically executable instructions.

[0152] Computer-readable medium 708 is illustrated as including memory 710. Memory 710 represents a memory associated with one or more computer-readable media. Memory 710 may include volatile storage media (such as random access memory (RAM)) and / or non-volatile storage media (such as read-only memory (ROM), flash memory, optical disk, magnetic disk, etc.). Memory 710 may include fixed media (e.g., RAM, ROM, fixed hard disk drive, etc.) and removable media (e.g., flash memory, removable hard disk drive, optical disk, etc.). Computer-readable medium 708 may be configured in various other ways as further described below.

[0153] One or more input / output interfaces 706 represent the functionality that allows a user to type commands and information into a computing device 700 and also allows information to be presented to the user and / or sent to other components or devices using various input / output devices. Examples of input devices include keyboards, cursor control devices (e.g., mice), microphones (e.g., for voice input), scanners, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), cameras (e.g., capable of detecting non-touch-related movements as gestures using visible or invisible wavelengths (such as infrared frequencies), network interface cards (NICs), receivers, and so on). Examples of output devices include display devices (e.g., monitors or projectors), speakers, printers, haptic-responsive devices, network interface cards (NICs), transmitters, and so on.

[0154] The computing device 700 also includes an application 712. The application 712 can be stored as computing program instructions in the memory 710. The application 712, together with the processing system 702, can implement the various steps of method 100 or 200. (Refer to the above...) Figure 9 The described apparatus 600 may take the form of a computing device 700. Alternatively, the apparatus 600 may be implemented as a computer program as an application 712, i.e., the application 712 may be a software instance of the apparatus 600 and implement the techniques described herein in combination with other elements in the computing device 700.

[0155] This document describes various technologies in the general context of software, hardware, components, or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. The terms "module," "function," etc., as used herein generally refer to software, firmware, hardware, or a combination thereof. The technologies described herein are platform-independent, meaning that these technologies can be implemented on a variety of computing platforms with various processors.

[0156] Implementations of the described modules and technologies may be stored on or transmitted across some form of computer-readable medium. The computer-readable medium may include a variety of media accessible by the computing device 700. By way of example and not limitation, the computer-readable medium may include "computer-readable storage media" and "computer-readable signal media".

[0157] In contrast to simple signal transmission, carrier waves, or signals themselves, a "computer-readable storage medium" refers to a medium and / or device capable of persistently storing information, and / or a tangible storage device. Therefore, a computer-readable storage medium refers to a non-signal-bearing medium. Computer-readable storage media include hardware such as volatile and non-volatile, removable and non-removable media and / or storage devices implemented using methods or techniques suitable for storing information (such as computer-executable instructions, data structures, program modules, logic elements / circuits, or other data). Examples of computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD or other optical storage devices, hard disks, magnetic tape cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or other storage devices, tangible media, or articles of art suitable for storing desired information and accessible by a computer.

[0158] "Computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions, such as via a network, to computing device 700. Signal media typically embody computer-executable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves, data signals, or other transmission mechanisms. Signal media also includes any information transmission medium. By way of example and not limitation, signal media includes wired media such as wired networks or direct connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0159] As previously described, hardware element 704 and computer-readable medium 708 represent instructions, modules, programmable device logic, and / or fixed device logic implemented in hardware, which in some embodiments can be used to implement at least some aspects of the techniques described herein. Hardware elements may include components of integrated circuits or systems-on-a-chip, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations or other hardware devices in silicon. In this context, hardware elements can serve as processing devices for executing program tasks defined by instructions, modules, and / or logic embodied by the hardware element, and as hardware devices for storing instructions for execution, such as the previously described computer-readable storage medium.

[0160] The foregoing combinations can also be used to implement the various techniques and modules described herein. Therefore, software, hardware, or program modules and other program modules can be implemented as one or more instructions and / or logic embodied on some form of computer-readable storage medium and / or by one or more hardware elements 704. The computing device 700 can be configured to implement specific instructions and / or functions corresponding to the software and / or hardware modules. Thus, modules can be implemented at least partially in hardware as modules executable as software by the computing device 700, for example, by using the computer-readable storage medium and / or hardware elements 704 of a processing system. Instructions and / or functions can be executed / operated by, for example, one or more computing devices 700 and / or processing system 702 to implement the techniques, modules, and examples described herein.

[0161] The techniques described herein can be supported by these various configurations of computing device 700, and are not limited to specific examples of the techniques described herein.

[0162] It should be understood that, for clarity, embodiments of this disclosure have been described with reference to different functional units. However, it will be apparent that, without departing from this disclosure, the functionality of each functional unit may be implemented in a single unit, in multiple units, or as part of other functional units. For example, functionality described as being performed by a single unit may be performed by multiple different units. Therefore, references to a particular functional unit are considered merely as references to the appropriate unit used to provide the described functionality, and not as indicating a strict logical or physical structure or organization. Thus, this disclosure may be implemented in a single unit, or may be physically and functionally distributed among different units and circuits.

[0163] This disclosure provides a computer-readable storage medium storing computer-executable instructions thereon, which, when executed, implement the circuit board wiring methods provided in the various embodiments described above.

[0164] This disclosure provides a computer program product or computer program including computer-executable instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the computing device to perform the circuit board wiring methods provided in the various embodiments described above.

[0165] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0166] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the foregoing terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples, without contradiction.

[0167] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0168] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A circuit board comprising multiple layers and multiple sets of traces, characterized in that, The multiple sets of traces are configured to transmit a set of signals, and each set of traces is configured to transmit one signal from the set of signals. The difference between the total transmission delay of any signal in the set of signals and the reference time on the corresponding set of traces is less than or equal to a threshold value, where the threshold value is the delay difference value required by the timing rules corresponding to the set of signals. The multiple layers include a surface layer and multiple inner layers. The surface layer refers to the top or bottom layer of the circuit board, and the inner layers refer to all layers other than the surface layer. The wiring method for the multiple sets of cables is as follows: Each of the multiple sets of traces includes N first transmission lines connected in sequence, where N is a positive integer greater than or equal to 2. The multiple inner layers are specific layers, and each of the specific layers has one of the N first transmission lines from each set of traces. The N first transmission lines are located in different layers of the multiple inner layers, but the routing order of the N first transmission lines in at least one set of traces is different from the routing order of the N first transmission lines in the other sets of traces, and the length of at least one of the N first transmission lines in the at least one set of traces is different from the length of the first transmission lines in the other sets of traces that are located on the same layer as the at least one first transmission line.

2. The circuit board according to claim 1, characterized in that, The circuit board also includes a second transmission line located on the surface layer, the second transmission line including a first outgoing trace and a second outgoing trace. The circuit board also includes multiple vias penetrating the multiple layers. Each set of traces includes a signal input terminal and a signal output terminal. The signal input terminal is connected to the first fan-out trace. The first fan-out trace is connected to one of the multiple vias. The via is connected to the first transmission line. The first transmission line is connected to another of the multiple vias. The other via is connected to the second fan-out trace. The second fan-out trace is connected to the signal output terminal.

3. An electronic device, characterized in that, The electronic device includes the circuit board according to claim 1 or 2.

4. A wiring method for a circuit board, characterized in that, The wiring method includes: Obtain a circuit board model, which includes multiple sets of traces, each set of traces including N first transmission lines, where N is a positive integer greater than or equal to 2; Adjust the length of at least one of the multiple first transmission lines in the multiple sets of traces in the circuit board model to obtain the target circuit board model, wherein the target circuit board model corresponds to the circuit board as described in claim 1 or 2.

5. The wiring method according to claim 4, characterized in that, Adjusting the length of at least one of the multiple first transmission lines in the multiple sets of traces in the circuit board model includes: Based on the transmission delay of the target signal in the set of signals per unit length of the corresponding first transmission line, the first initial length of the first transmission line corresponding to the target signal is adjusted.

6. The wiring method according to claim 5, characterized in that, The step of adjusting the first initial length of the first transmission line corresponding to the target signal based on the transmission delay of the target signal in the set of signals per unit length of the corresponding first transmission line includes: Obtain the initial total propagation delay of each signal in the set of signals on the corresponding set of traces; Based on the multiple initial total transmission delays of the set of signals, determine the amount of delay that needs to be adjusted for the initial total transmission delay of each target signal in the set of signals; The length value of the first transmission line that needs to be adjusted is obtained based on the ratio of the delay amount that needs to be adjusted to the transmission delay of each target signal per unit length of the corresponding first transmission line. Based on the length value that needs to be adjusted, the first initial length of the first transmission line corresponding to the target signal is adjusted.

7. The wiring method according to claim 6, characterized in that, The determination of the amount of delay that needs to be adjusted for the initial total transmission delay of each target signal in the set of signals, based on multiple initial total transmission delays of the set of signals, includes: One of the multiple initial total transmission delays is used as the reference time; In response to the initial total transmission delay of the target signal being greater than the reference time and the absolute value of the difference between the two being greater than the threshold, the reference time and the threshold are subtracted from the initial total transmission delay to obtain the time difference, and the time difference is determined as the amount of delay to be adjusted. In response to the initial total transmission delay of the target signal being less than the reference time and the absolute value of the difference between the two being greater than the threshold, the initial total transmission delay and the threshold are subtracted from the reference time to obtain the time difference, and the time difference is determined as the delay amount to be adjusted.

8. The wiring method according to claim 6, characterized in that, The step of obtaining the initial total transmission delay of each signal in the set of signals on the corresponding set of traces includes: The first transmission delay of each signal in the set of signals on the first transmission line of the corresponding set of traces, and the second transmission delay on the plurality of vias associated with the corresponding set of traces are obtained. Based on the sum of the first transmission delay and the second transmission delay, the initial total transmission delay of each signal in the set of signals on the corresponding set of traces is obtained.

9. The wiring method according to claim 8, characterized in that, The step of obtaining the first transmission delay of each signal in the set of signals on the first transmission line of the corresponding set of traces includes: Determine the propagation delay of each signal in the set of signals per unit length on the first transmission line corresponding to the set of traces; The first transmission delay of each signal on the first transmission line of the corresponding set of traces is obtained by multiplying the length of the first transmission line of the corresponding set of traces by the transmission delay per unit length of the first transmission line.

10. The wiring method according to claim 9, characterized in that, Each set of traces includes a signal input terminal and a signal output terminal. The step of obtaining the first transmission delay of each signal in the set of signals on the first transmission line of the corresponding set of traces includes: Based on the first initial length of the first transmission line of each group of traces, the initial time required for the signal to be transmitted from the signal input terminal to the signal output terminal is obtained; Obtain the modified first length of one of the N first transmission lines in each group of traces; Based on the modified first length, obtain the modified first time required for the signal to be transmitted from the signal input terminal to the signal output terminal; Based on the ratio of the difference between the changed first time and the initial time and the difference between the changed first length and the first initial length, the transmission delay of the signal per unit length of the target first transmission line is obtained; Restore the modified first length to the first initial length; In response to restoring the changed first length of the last target first transmission line in the N first transmission lines of the group of traces to the first initial length, the transmission delay of the signal per unit length of each of the N first transmission lines in the group of traces is obtained. Summing the product of the transmission delay per unit length of each of the N first transmission lines and the length of that first transmission line, we obtain the first transmission delay of each signal on the N first transmission lines corresponding to the same set of traces.

11. The wiring method according to any one of claims 4-10, characterized in that, The circuit board also includes a second transmission line located on the surface layer, the second transmission line including a first outgoing trace and a second outgoing trace. The circuit board also includes multiple vias penetrating the multiple layers. Each set of traces includes a signal input terminal and a signal output terminal. The signal input terminal is connected to the first fan-out trace. The first fan-out trace is connected to one of the multiple vias. The via is connected to the first transmission line. The first transmission line is connected to another of the multiple vias. The other via is connected to the second fan-out trace. The second fan-out trace is connected to the signal output terminal.

12. An apparatus for wiring a circuit board, characterized in that, The device includes: The acquisition module is configured to acquire a circuit board model, which includes multiple sets of traces, each set of traces including N first transmission lines, where N is a positive integer greater than or equal to 2; The control module is configured to adjust the length of at least one of the multiple first transmission lines in the multiple sets of traces in the circuit board model to obtain a target circuit board model, wherein the target circuit board model corresponds to the circuit board as described in claim 1 or 2.

13. A computing device, comprising: Memory, configured to store computer-executable instructions; A processor configured to execute the wiring method according to any one of claims 4-11 when the computer-executable instructions are executed by the processor.

14. A computer-readable storage medium storing computer-executable instructions that, when executed, perform the wiring method according to any one of claims 4-11.

15. A computer program product comprising computer-executable instructions that, when executed by a processor, implement the wiring method as described in any one of claims 4-11.

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