Memory device and method of operation thereof

Abstract

The present disclosure relates to a memory device. In one aspect, the memory device includes a memory cell, a pre-charge circuit, a reset voltage control circuit, and a logic control circuit. In one aspect, the pre-charge circuit is configured to set a voltage of a bit line to a first voltage level. In one aspect, the reset voltage control circuit includes a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level. The transistor can be arranged or operated as a diode. In one aspect, the logic control circuit is configured to cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase, and to cause the pre-charge circuit to set the voltage of the bit line to the first voltage level during a pre-charge phase after the reset phase. Embodiments of the present application also relate to a method of operating a memory device.

Description

Technical Field

[0001] The embodiments of this application relate to storage devices and methods of operation thereof. Background Technology

[0002] The development of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices has driven increased demand for storage devices. Storage devices can typically be either volatile or non-volatile. Volatile storage devices can store data while powered on, but may lose this data when power is off. Unlike volatile storage devices, non-volatile storage devices retain data even after power is turned off, but may be slower than volatile storage devices. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a storage device is provided, comprising: a memory cell; a precharge circuit coupled to the memory cell via a bit line, the precharge circuit setting the voltage of the bit line to a first voltage level; a reset voltage control circuit including a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level, the transistor operating as a diode; and a logic control circuit coupled to the precharge circuit and the reset voltage control circuit, the logic control circuit being configured to: cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase, and cause the precharge circuit to set the voltage of the bit line to the first voltage level during a precharge phase following the reset phase.

[0004] According to another aspect of the embodiments of this application, a storage device is provided, including: a memory cell; a bit line coupled to the memory cell; and a controller configured to: set the voltage of the bit line to a first voltage level during a reset phase if the operating mode of the storage device is a first mode, and set the voltage of the bit line to a second voltage level during a reset phase if the operating mode of the storage device is a second mode.

[0005] According to another aspect of the embodiments of this application, a method for operating a storage device is provided, comprising: determining an operating mode of the storage device by a controller, the storage device including memory cells coupled to bit lines; determining a time period of a pre-charging phase by the controller based on the operating mode of the storage device; during the pre-charging phase of the time period, setting the voltage of the bit lines to a first voltage level by the controller; discharging the bit lines by the controller in a sensing phase following the pre-charging phase based on data stored in the memory cells; and determining, by the controller, the data stored in the memory cells during the sensing phase based on the voltage of the discharged bit lines in the sensing phase. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic block diagram of an example storage device according to some embodiments is shown.

[0008] Figure 2 A schematic block diagram of an example bitline controller according to some embodiments is shown.

[0009] Figure 3 A plan view of a storage device according to some embodiments is shown.

[0010] Figure 4A A schematic diagram of a set of memory cells, a precharge circuit, and a reset voltage control circuit according to some embodiments is shown.

[0011] Figure 4B A schematic diagram of a set of memory cells, a precharge circuit, and a reset voltage control circuit according to some embodiments is shown.

[0012] Figure 5A A timing diagram of signals for performing a read operation in a first operating mode is shown according to some embodiments.

[0013] Figure 5B A timing diagram of signals for performing a read operation in a second operating mode is shown according to some embodiments.

[0014] Figure 6 This is a flowchart illustrating a method for operating a storage device according to an operating mode of the storage device, based on some embodiments.

[0015] Figure 7 This is an example block diagram of a computing system according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relation terms such as "below," "under," "lower," "above," "upper," "top," and "top" may be used herein to describe the relationship between one element or component and another, as shown in the figure. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figure. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0018] This document discloses a memory device with reset voltage control. In one aspect, the memory device includes a memory cell, a precharge circuit, a reset voltage control circuit, and a logic control circuit. In one aspect, the precharge circuit is configured to set the voltage of the bit line to a first voltage level.

[0019] In one aspect, the reset voltage control circuit includes a transistor coupled to a bit line to set the voltage of the bit line to a second voltage level. The second voltage level may be less than a first voltage level. For example, the first voltage level may be a power supply voltage level VDD or 1V, and the second voltage level may be the difference between the power supply voltage level VDD and the threshold voltage Vth of the transistor or diode (e.g., VDD–Vth). The transistor may be arranged or operated as a diode. In one aspect, a logic control circuit is configured to cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase, and to cause a pre-charge circuit to set the voltage of the bit line to the first voltage level during a pre-charge phase following the reset phase. After the pre-charge phase, the logic control circuit may discharge the bit line during a sensing phase based on the data stored in the memory cell. Here, bit line discharge refers to removing charge at the bit line to reduce or decrease the voltage of the bit line. The logic control circuit may determine the data stored in the memory cell during the sensing phase based on the voltage of the bit line discharged during the sensing phase.

[0020] Advantageously, memory devices can operate faster by setting the bit line voltage to a second voltage level (e.g., VDD-Vth (threshold voltage) of the transistor). In one embodiment, during the reset phase, the bit line can be discharged or set to, for example, a ground voltage level (e.g., 0V or GND). During the pre-charge phase following the reset phase, the bit line voltage can be set to a first voltage level (e.g., VDD or 1V). Then, during the sensing phase, the bit line voltage can be discharged according to the data stored in the memory cell, and the data stored in the memory cell can be determined based on the discharged bit line voltage. However, charging the bit line or setting the bit line voltage from the ground voltage level (e.g., 0V or GND) to the first voltage level can take a long time and may limit or reduce the speed of the memory device. By setting the bit line voltage to a second voltage level between the first voltage level (e.g., VDD or 1V) and the ground voltage level during the reset phase, charging the bit line or setting the bit line voltage to the first voltage level can be performed faster. Therefore, by setting the bit line voltage to a second voltage level during the reset phase, the operating speed of the memory device can be improved because the time to charge the bit line voltage to the first voltage level during the pre-charge phase can be reduced.

[0021] In one aspect, memory devices can be adaptively configured or operated in a selected mode by enabling or disabling the reset voltage control circuit. For example, in a first operating mode (or normal operating mode), the reset voltage control circuit can be disabled during the reset phase, allowing the bit line voltage to be discharged to ground. By setting the bit line voltage to ground during the reset phase, leakage current during the reset phase can be reduced. For example, in a second operating mode (or turbo operating mode), the reset voltage control circuit can be enabled during the reset phase, thereby setting the bit line voltage to a second voltage level (e.g., VDD-Vth (threshold voltage) of the transistor). By setting the bit line voltage to the second voltage level (e.g., VDD-Vth) during the reset phase, the time required to charge the bit line voltage to the first voltage level during the pre-charge phase can be reduced, allowing the memory device in the second operating mode to perform read operations faster than in the first operating mode.

[0022] In some embodiments, one or more components may be implemented as one or more transistors. Transistors in this disclosure are shown as having a specific type (N-type or P-type), but embodiments are not limited thereto. A transistor can be any suitable type of transistor, including but not limited to metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. Furthermore, one or more transistors shown or described herein may be implemented as two or more transistors connected in parallel.

[0023] Figure 1 This is a diagram of a memory device 100 according to one embodiment. In some embodiments, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of memory circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to a corresponding word line WL and a corresponding bit line BL. The memory controller 105 may write data to or read data from the memory array according to electrical signals through the word line WL and the bit line BL. In other embodiments, the memory device 100 includes a... Figure 1 Show more, fewer, or different components.

[0024] Memory array 120 is a hardware component for storing data. In one aspect, memory array 120 is implemented as a semiconductor memory device. Memory array 120 includes a plurality of memory circuits or memory cells 125. Memory array 120 includes word lines WL0, WL1...WLJ, each extending in a first direction (e.g., the X direction), and bit lines BL0, BL1...BLK, each extending in a second direction (e.g., the Y direction). Word lines WL and bit lines BL can be conductive metal or conductive rails. In one configuration, each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and can operate according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB coupled to one or more memory cells 125 in a group of memory cells 125 arranged along a second direction (e.g., the Y direction). Bit lines BL, BLB can receive and / or provide differential signals. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is implemented as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0025] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line controller 112, word line controller 114, and timing controller 110. Bit line controller 112, word line controller 114, and timing controller 110 may be implemented as logic circuitry, analog circuitry, or a combination thereof. In one configuration, word line controller 114 is circuitry that provides voltage or current through one or more word lines WL of memory array 120, and bit line controller 112 is circuitry that provides or senses voltage or current through one or more bit lines BL of memory array 120. In one configuration, timing controller 110 is circuitry that provides control signals or clock signals to synchronize the operation of bit line controller 112 and word line controller 114. In some embodiments, timing controller 110 is implemented as or includes a processor and non-transitory computer-readable medium containing storage instructions that, when executed by the processor, cause the processor to perform one or more functions of timing controller 110 or memory controller 105 described herein. Bit line controller 112 can be coupled to bit line BL of memory array 120, and word line controller 114 can be coupled to word line WL of memory array 120. In some embodiments, memory controller 105 includes... Figure 1 The components shown may be more, fewer, or different than the components shown.

[0026] In one example, timing controller 110 may generate control signals to coordinate the operation of bit line controller 112 and word line controller 114. In one method, to write data to memory cell 125, timing controller 110 may cause word line controller 114 to apply voltage or current to memory cell 125 via word line WL coupled to memory cell 125, and cause bit line controller 112 to apply voltage or current corresponding to the data to be stored to memory cell 125 via bit line BL coupled to memory cell 125. In another method, to read data from memory cell 125, timing controller 110 may cause word line controller 114 to apply voltage or current to memory cell 125 via word line WL coupled to memory cell 125, and cause bit line controller 112 to sense voltage or current corresponding to the data stored in memory cell 125 via bit line BL coupled to memory cell 125.

[0027] Figure 2A schematic block diagram of an example bit line controller 112 according to some embodiments is shown. In some embodiments, the bit line controller 112 includes a precharge circuit 220, a reset voltage control circuit 230, a sense amplifier 240, and a logic control circuit 250. These components can operate together to determine the data stored in the memory cell 125. For example, the reset voltage control circuit 230 can set the voltage of the bit line BL to a reset voltage level during a reset phase, and the precharge circuit 220 can set the voltage of the bit line BL to a precharge voltage level or a power supply voltage level during a precharge phase. During a sensing phase, the bit line BL can discharge according to the data stored in the memory cell. The sense amplifier 240 can sense the voltage or current of the bit line during the sensing phase to determine the data stored in the memory cell 125. In some embodiments, the bit line controller 112 includes a... Figure 2 Show more, fewer, or different components.

[0028] In some embodiments, the precharge circuit 220 is a circuit that sets or precharges the voltage of bit line BL to a supply voltage level (e.g., VDD or 1V). In some embodiments, the precharge circuit 220 may be replaced by different circuits or components capable of performing the functions of the precharge circuit 220 described herein. In one configuration, the precharge circuit 220 includes a transistor or switch that can selectively couple a power rail or metal rail having a supply voltage level (e.g., VDD or 1V) to bit line BL according to a control signal. For example, in response to a control signal having a supply voltage level (e.g., 1V), the precharge circuit 220 can be disabled to electrically decouple bit line BL from the power rail or metal rail, such that the voltage of bit line BL may not be set to the supply voltage level. For example, in response to a control signal having a ground voltage level (e.g., 0V), the precharge circuit 220 can be enabled to electrically couple bit line BL to the power rail or metal rail, such that the voltage of bit line BL may be set to the supply voltage level (e.g., VDD or 1V).

[0029] In some embodiments, the reset voltage control circuit 230 is a circuit that sets or precharges the voltage of bit line BL to a reset voltage level. The reset voltage level can be lower than the supply voltage level (e.g., VDD or 1V) and higher than the ground voltage level (e.g., GND or 0V). In some embodiments, the reset voltage control circuit 230 can be replaced by different circuits or components capable of performing the functions of the reset voltage control circuit 230 described herein. In one configuration, the reset voltage control circuit 230 includes a diode-connected transistor or a diode coupled to bit line BL. Here, a diode-connected transistor refers to a transistor whose drain and gate are coupled to each other or have the same voltage. The reset voltage control circuit 230 can selectively set the voltage of bit line BL to the reset voltage level according to a control signal. When the diode or diode-connected transistor is enabled, the voltage of bit line BL can decrease from the supply voltage level to the threshold voltage of the diode or transistor. For example, in response to a control signal having a ground voltage level (e.g., GND or 0V), the reset voltage control circuit 230 can be disabled to electrically decouple the bit line BL from the power rail or metal rail that provides the power supply voltage, such that the voltage of the bit line BL is not set to the reset voltage level. Alternatively, in response to a control signal having a power supply voltage level (e.g., VDD or 1V), the reset voltage control circuit 230 can be enabled to electrically couple the bit line BL to the power rail or metal rail via a diode or a diode-connected transistor, such that the voltage of the bit line BL is set to the reset voltage level (e.g., VDD-Vth of the transistor).

[0030] In some embodiments, the sense amplifier 240 is a component that amplifies the voltage of bit line BL. In some embodiments, the sense amplifier 240 may be replaced by different circuitry or different components that can perform the functions of the sense amplifier 240 described herein. In one configuration, the sense amplifier 240 may be implemented as a comparator that compares the voltage of bit line BL with a reference voltage or the voltage of the corresponding bit line BLB and generates a digitally represented signal or voltage corresponding to the comparison. For example, if the sensed voltage of bit line BL is lower than the reference voltage or the voltage of bit line BLB, the sense amplifier 240 may generate an output voltage corresponding to logic state '0'. For example, if the sensed voltage of bit line BL is higher than the reference voltage or the voltage of bit line BLB, the sense amplifier 240 may generate an output voltage corresponding to logic state '1'.

[0031] In some embodiments, logic control circuitry 250 is a component that generates one or more control signals to control the operation of precharge circuitry 220, reset voltage control circuitry 230, and sense amplifier 240. In some embodiments, logic control circuitry 250 may be replaced by different circuits or components capable of performing the functions of logic control circuitry 250 described herein. In some embodiments, logic control circuitry 250 is implemented as a field-programmable gate array (FPGA), digital logic circuitry, application-specific integrated circuit (ASIC), etc. In some embodiments, logic control circuitry 250 is implemented as or replaced by a processor and a non-transitory computer-readable medium storing instructions that, when executed by the processor, cause the processor to perform the various functions of logic control circuitry 250 described herein. In one aspect, logic control circuitry 250 generates control signals and provides these control signals to precharge circuitry 220, reset voltage control circuitry 230, and sense amplifier 240 to coordinate the operation of precharge circuitry 220, reset voltage control circuitry 230, and sense amplifier 240. In one example, in order to read the data stored in memory cell 125, logic control circuit 250 can configure or operate precharge circuit 220, reset voltage control circuit 230 and sense amplifier 240 through three stages: reset stage, precharge stage and sensing stage.

[0032] During the reset phase, logic control circuit 250 can generate control signals and provide them to precharge circuit 220 and reset voltage control circuit 230 to set the voltage of bit line BL coupled to memory cell 125 to the reset voltage level. For example, logic control circuit 250 can generate control signals during the reset phase to enable reset voltage control circuit 230 and disable precharge circuit 220. Logic control circuit 250 can also generate control signals during the reset phase to disable sense amplifier 240.

[0033] During the pre-charge phase, logic control circuit 250 can generate control signals and provide them to pre-charge circuit 220 and reset voltage control circuit 230 to set the voltage of bit line BL coupled to memory cell 125 to the power supply voltage level. For example, logic control circuit 250 can generate control signals during the pre-charge phase to disable reset voltage control circuit 230 and enable pre-charge circuit 220. Logic control circuit 250 can also generate control signals during the pre-charge phase to disable sense amplifier 240.

[0034] During the sensing phase, bit line BL can discharge based on the data stored in memory cell 125. In one method, during the sensing phase, word line control circuit 114 can generate a control signal based on the data stored in memory cell 125 to couple memory cell 125 to bit line BL, such that the voltage of bit line BL can be changed or adjusted. For example, if memory cell 125 stores a bit '0' corresponding to a ground voltage level (e.g., 0V), the voltage of bit line BL can become or decrease toward a ground voltage level (e.g., 0V). For example, if memory cell 125 stores a bit '1' corresponding to a power supply voltage level (e.g., 1V), the voltage of bit line BL can remain at the power supply voltage level. During the sensing phase, logic control circuit 250 can generate and provide control signals to cause sensing amplifier 240 to sense the voltage of bit line BL. For example, logic control circuit 250 can generate control signals during the sensing phase to disable reset voltage control circuit 230 and precharge circuit 220. The logic control circuit 250 can generate a control signal during the sensing phase to enable the sensing amplifier 240, allowing the sensing amplifier 240 to amplify the voltage of bit line BL, or amplify the difference between the voltage of bit line BL and the voltage of bit line BLB, to provide an amplified voltage as the output voltage. During the sensing phase, the logic control circuit 250 can determine the data stored in the memory cell 125 based on the output voltage of the sensing amplifier 240.

[0035] Advantageously, the memory device 100 can operate faster by setting the voltage of bit line BL to a reset voltage level (e.g., VDD-Vth). By setting the voltage of bit line BL to a reset voltage level instead of a ground voltage level (e.g., GND or 0V) during the reset phase, charging the bit line BL or setting the voltage of bit line BL to a supply voltage level (e.g., VDD or 1V) can be performed faster. Therefore, by setting the voltage of bit line BL to a reset voltage level during the reset phase, the operating speed of the memory device 100 can be improved because the time required to charge the voltage of bit line BL to the supply voltage level during the pre-charge phase can be reduced.

[0036] In one aspect, logic control circuit 250 can selectively enable or disable reset voltage control circuit 230 during the reset phase based on the operating mode of memory device 100. Logic control circuit 250 can receive a mode signal indicating the operating mode of memory device 100 from timing controller 110, a controller, or an external component, and determine the operating mode of memory device 100 according to the indication of the mode signal. For example, in a first operating mode (or normal operating mode), logic control circuit 250 can disable reset voltage control circuit 230 during the reset phase, allowing the voltage of bit line BL to discharge to ground voltage level (e.g., GND or 0V). By setting the voltage of bit line BL to ground voltage level during the reset phase, leakage current during the reset phase can be reduced. For example, in a second operating mode (or turbo operating mode), logic control circuit 250 can enable reset voltage control circuit 230 during the reset phase, allowing the voltage of bit line BL to be set to reset voltage level (e.g., VDD-Vth). By setting the voltage of bit line BL to the reset voltage level (e.g., VDD-Vth) during the reset phase, the time required to charge the voltage of bit line BL to the power supply voltage level during the precharge phase can be reduced, allowing the memory device 100 in the second operating mode (or turbo operating mode) to perform read operations faster than in the first operating mode (or normal operating mode).

[0037] Figure 3 A plan view of a memory device 100 or a portion thereof according to some embodiments is shown. In one configuration, the memory device 100 includes memory arrays 120A, 120B and a word line controller 114 disposed between the memory arrays 120A, 120B. In another configuration, the memory device 100 includes a bit line controller 112 disposed below the memory arrays 120A, 120B and the word line controller 114. In this configuration, memory cells 125 in the memory arrays 120A, 120B can be coupled to the word line controller 114 via word lines WL extending in the X direction. Furthermore, memory cells 125 in the memory arrays 120A, 120B can be coupled to the bit line controller 112 via bit lines BL extending in the Y direction. Thus, the word line controller 114 can provide control signals (e.g., word line control signals) via one or more word lines WL, while the bit line controller 112 can provide or receive signals via one or more bit lines BL to control the operation of the memory arrays 120A, 120B.

[0038] In one configuration, the bit line controller 112 includes I / O circuitry 310 disposed along the X-direction and logic control circuitry 250 disposed below the word line controller 114. Each I / O circuitry 310 may include a precharge circuitry 220, a reset voltage control circuitry 230, and a sense amplifier 240. In one configuration, the bit line controller 112 includes a control line 350 extending along the X-direction. The control line 350 may be a metal rail or a conductive rail that electrically couples the logic control circuitry 250 to the I / O circuitry 310 disposed along the X-direction. For example, the logic control circuitry 250 includes an inverter 320 and an AND gate 330. The inverter 320 may receive a word line control signal 325, based on which the word line controller 114 may drive or control memory cells 125. The AND gate 330 may include a first input coupled to the output of the inverter 320 and a second input, for example, receiving a mode selection signal 335 from a timing controller 110, a processor, or an external component. The output of AND gate 330 can be coupled to the reset voltage control circuit 230 of I / O circuit 310 via control line 350. In this configuration, logic control circuit 250 can control I / O circuit 310, which is positioned along the X direction, by providing a reset control signal 345 via control line 350, based on word line control signal 325 and mode selection signal 335. For example, when mode selection signal 335 has a ground voltage level (e.g., GND or 0V) corresponding to a first operating mode (or normal operating mode), logic control circuit 250 can provide the reset control signal 345 with a ground voltage level (e.g., GND or 0V) to the reset voltage control circuit 230 of I / O circuit 310 via control line 350. For example, when mode selection signal 335 has a power supply voltage level (e.g., VDD or 1V) corresponding to a second operating mode (or turbo operating mode), logic control circuit 250 can provide the reset voltage control circuit 230 of I / O circuit 310 with an inverted word line control signal 325 via control line 350. Therefore, the logic control circuit 250 can selectively configure or operate the I / O circuit 310 in the selected operating mode by providing a reset control signal 345 via the control line 350.

[0039] Figure 4AA schematic diagram shows a group of memory cells 125 arranged along the Y direction and an I / O circuit 310A coupled to the group of memory cells 125. In one configuration, the I / O circuit 310A includes a reset voltage control circuit 230A and a precharge circuit 220 coupled to the memory cells 125 via bit lines BL and BLB. The bit lines BL and BLB can provide differential signals. In this configuration, the precharge circuit 220 and the reset voltage control circuit 230 can set the voltages of the bit lines BL and BLB. For example, the precharge circuit 220 can set the voltages of the bit lines BL and BLB to the power supply voltage level (e.g., VDD or 1V) during the precharge phase according to a precharge control signal 425. For example, the reset voltage control circuit 230A can set the voltages of the bit lines BL and BLB to the reset voltage level (e.g., VDD-Vth) during the reset phase according to a reset control signal 345.

[0040] In some embodiments, the precharge circuit 220 includes transistors M3, M4, and M5. Transistors M3, M4, and M5 may be P-type transistors (e.g., P-type MOSFETs, P-type FinFETs, etc.). In one configuration, transistor M3 includes a source electrode coupled to a power rail to receive a power supply voltage having a power supply voltage level VDD, a gate electrode receiving a precharge control signal 425, and a drain electrode coupled to bit line BL. In one configuration, transistor M4 includes a source electrode coupled to a power rail to receive a power supply voltage having a power supply voltage level VDD, a gate electrode coupled to the gate electrode of transistor M3 to receive the precharge control signal 425, and a drain electrode coupled to bit line BLB. In one configuration, transistor M5 includes a source electrode coupled to bit line BL, a gate electrode coupled to the gates of transistors M3 and M4 to receive the precharge control signal 425, and a drain electrode coupled to bit line BLB. In this configuration, transistors M3, M4, and M5 can be enabled or disabled in response to the precharge control signal 425 from logic control circuit 250. For example, in response to a precharge control signal 425 having a ground voltage level (e.g., GND or 0V), transistors M3, M4, and M5 can be enabled to set the voltages of bit lines BL and BLB to have a supply voltage level VDD. Alternatively, in response to a precharge control signal 425 having a supply voltage level (e.g., VDD or 1V), transistors M3, M4, and M5 can be disabled to prevent the voltages of bit lines BL and BLB from being set to the supply voltage level VDD.

[0041] In some embodiments, the reset voltage control circuit 230A includes transistors M1 and M2. Transistors M1 and M2 may be N-type transistors (e.g., N-type MOSFETs, N-type FinFETs, etc.). In one configuration, transistor M1 includes a drain electrode coupled to a power rail to receive a power supply voltage having a power supply voltage level VDD, a gate electrode receiving a reset control signal 345, and a source electrode coupled to bit line BL. In one configuration, transistor M2 includes a drain electrode coupled to a power rail to receive a power supply voltage having a power supply voltage level VDD, a gate electrode coupled to the gate electrode of transistor M1, and a source electrode coupled to bit line BLB. In one configuration, the drain electrodes of transistors M1 and M2 may be coupled to the same power rail to which the source electrodes of transistors M3 and M4 of the precharge circuit 220 are coupled. In one configuration, the drain electrodes of transistors M1 and M2 may be coupled to a different power rail than the power rail to which the source electrodes of transistors M3 and M4 of the precharge circuit 220 are coupled. In one aspect, transistors M1 and M2 can be selectively operated as diodes according to a reset control signal 345. For example, in response to a reset control signal 345 having a power supply voltage level (e.g., VDD or 1V), transistors M1 and M2 can be arranged in a diode-connected configuration to set the voltages of bit lines BL and BLB to have a reset voltage level VDD-Vth (e.g., the threshold voltages of transistors M1 and M2). For example, in response to a reset control signal 345 having a ground voltage level (e.g., GND or 0V), transistors M1 and M2 can be disabled to prevent the voltages of bit lines BL and BLB from being set to the reset voltage level.

[0042] Figure 4B A schematic diagram is shown of a group of memory cells 125 arranged along the Y direction and an I / O circuit 310B coupled to the group of memory cells 125. In one aspect, the I / O circuit 310B is similar to Figure 4A The IO circuit 310A is included, but the IO circuit 310B includes the reset voltage control circuit 230B instead of the reset voltage control circuit 230A. Therefore, for the sake of brevity, a detailed description of its repeated parts is omitted here.

[0043] In some embodiments, the reset voltage control circuit 230B includes transistors M6 and M7 and diode D. Transistors M6 and M7 may be N-type transistors (e.g., N-type MOSFETs, N-type FinFETs, etc.). In one configuration, diode D includes a first electrode (e.g., anode) coupled to a power rail to receive a power supply voltage having a power supply voltage level VDD and a second electrode (e.g., cathode) coupled to the drain electrode of transistors M6 and M7. In one configuration, transistor M6 includes a gate electrode receiving a reset control signal 345 and a source electrode coupled to bit line BL. In one configuration, transistor M7 includes a gate electrode coupled to the gate electrode of transistor M6 to receive the reset control signal 345 and a source electrode coupled to bit line BLB. In this configuration, transistors M6 and M7 can operate as switches to selectively couple diode D to bit lines BL and BLB according to the reset control signal 345. For example, in response to a reset control signal 345 having a power supply voltage level (e.g., VDD or 1V), transistors M6 and M7 can be enabled to couple diode D to bit lines BL and BLB, such that the voltages of bit lines BL and BLB can have a reset voltage level VDD-Vth (e.g., the threshold voltage of diode D). For example, in response to a reset control signal 345 having a ground voltage level (e.g., GND or 0V), transistors M6 and M7 can be disabled to decouple diode D from bit lines BL and BLB, such that the voltages of bit lines BL and BLB can not have a reset voltage level.

[0044] Figure 5A A timing diagram 500A is shown, according to some embodiments, of signals for performing a read operation in a first operating mode (e.g., normal operating mode). Data stored in memory cell 125 can be read according to signals CLK, 425A, 345A, and 325A. To read the data stored in memory cell 125, memory device 100 can operate in three phases: a reset phase P0, a precharge phase P1, and a sensing phase P2. Figure 5A In this configuration, the mode selection signal 335A can have a ground voltage level (e.g., GND or 0V) during phases P0-P2 to indicate a first operating mode. Therefore, the bit line controller 112 can generate a reset control signal 345A with a ground voltage level (e.g., GND or 0V) during phases P0-P2 in response to the mode selection signal 335A with a ground voltage level (e.g., GND or 0V). In response to the reset control signal 345A with a ground voltage level, the reset voltage control circuit 230 can be disabled in the first operating mode (e.g., normal operating mode).

[0045] In one approach, during reset phase P0, timing controller 110 may generate a clock signal CLK with a ground voltage level (e.g., GND or 0V). During reset phase P0, bit line controller 112 may generate a precharge control signal 425A with a power supply voltage level (e.g., VDD or 1V). In response to the precharge control signal 425A with the power supply voltage level, precharge circuitry 220 may be disabled during reset phase P0. During reset phase P0, word line controller 114 may generate a word line control signal 325A with a ground voltage level (e.g., GND or 0V). In response to the word line control signal 325A with the ground voltage level, memory cell 125 may be decoupled from bit lines BL and BLB during reset phase P0.

[0046] In one approach, during the precharge phase P1, timing controller 110 can generate a clock signal CLK having a supply voltage level (e.g., VDD or 1V). Based on the clock signal CLK, bit line controller 112 can generate a precharge control signal 425A. For example, in response to the rising edge of the clock signal CLK, bit line controller 112 can generate a precharge control signal 425A with a falling edge. Bit line controller 112 can also generate a precharge control signal 425A with a ground voltage level (e.g., GND or 0V) during time period T1. In response to the precharge control signal 425A with a ground voltage level, precharge circuitry 220 can be enabled to set the voltages of bit lines BL and BLB to the supply voltage level (e.g., VDD or 1V) during the precharge phase P1. During the precharge phase P1, word line controller 114 can generate a word line control signal 325A with a ground voltage level (e.g., GND or 0V). In response to a word line control signal 325A with a ground voltage level, memory cell 125 can be decoupled from bit lines BL and BLB during the precharge phase P1.

[0047] In one approach, during the sensing phase P2, timing controller 110 can generate a clock signal CLK having a power supply voltage level (e.g., VDD or 1V). During the sensing phase P2 following the time period T1 used for the precharge phase P1, bit line controller 112 can generate a precharge control signal 425A having a power supply voltage level (e.g., VDD or 1V). In response to the precharge control signal 425A having a power supply voltage level, precharge circuitry 220 can be disabled during the sensing phase P2. Based on the precharge control signal 425A, word line controller 114 can generate a word line control signal 325A. For example, word line controller 114 can generate a word line control signal 325A with a rising edge in response to a rising edge of the precharge control signal 425A. In response to a word line control signal 325A having a power supply voltage level (e.g., VDD or 1V), memory cell 125 can couple to bit lines BL and BLB during sensing phase P2, such that bit lines BL and BLB can discharge according to the data stored in memory cell 125 during the sensing phase. For example, in response to memory cell 125 storing bit '0', the voltage of bit line BL can be lower than a reference voltage or the voltage of bit line BLB. For example, in response to memory cell 125 storing bit '1', the voltage of bit line BL can be higher than a reference voltage or the voltage of bit line BLB. Therefore, by sensing one or more voltages of bit lines BL and BLB during sensing phase P2, the data stored in memory cell 125 can be determined.

[0048] Following the sensing phase P2, the storage device 100 can operate in the subsequent reset phase P0'. The storage device 100 in the subsequent reset phase P0' can operate in a similar manner to that in the reset phase P0. Therefore, for the sake of brevity, a detailed description of its repetitive parts is omitted here.

[0049] Figure 5B A timing diagram 500B is shown for signals used to perform a read operation in a second operating mode (e.g., turbo operating mode) according to some embodiments. In one aspect, the operation of the storage device 100 in the second operating mode (e.g., turbo operating mode) is similar to its operation in the first operating mode (e.g., normal operating mode), but the mode selection signal 335B may have a power supply voltage level (e.g., VDD or 1V) during phases P0-P2, such that i) the reset control signal 345B may have a pulse, and ii) the precharge control signal 425B may have a narrower pulse width than the precharge control signal 425A. Therefore, for the sake of brevity, detailed descriptions of repeated portions are omitted here.

[0050] In one method, in a second operating mode (e.g., turbo operating mode), the reset voltage control circuit 230 can generate a reset control signal 345B having an inverted word line control signal 325B. For example, in the reset phase P0 and the precharge phase P1, the reset voltage control circuit 230 can generate a reset control signal 345B having a power supply voltage level (e.g., VDD or 1V) in response to the word line control signal 325B having a ground voltage level (e.g., GND or 0V). In response to the reset control signal 345B having a power supply voltage level (e.g., VDD or 1V), the reset voltage control circuit 230 can be enabled to set the voltage of bit lines BL, BLB to the reset voltage level (e.g., VDD-Vth of a transistor or diode). For example, in the sensing phase P2, the reset voltage control circuit 230 can generate a reset control signal 345B having a ground voltage level (e.g., GND or 0V) in response to the word line control signal 325B having a power supply voltage level (e.g., VDD or 1V). In response to a reset control signal 345B having a ground voltage level (e.g., GND or 0V), the reset voltage control circuit 230B can be disabled to prevent the voltages of bit lines BL and BLB from being set to the reset voltage level. Simultaneously, in response to a word line control signal 325B having a power supply voltage level (e.g., VDD or 1V) during the sensing phase, memory cell 125 can couple to bit lines BL and BLB during the sensing phase P2, allowing bit lines BL and BLB to discharge according to the data stored in memory cell 125.

[0051] In some embodiments, the memory device 100 can operate faster by setting the voltage of bit line BL to a second voltage level (e.g., VDD-Vth (threshold voltage) of the transistor). For example, the memory device 100 operating in a second operating mode (e.g., turbo operating mode) may have a shorter discharge phase P1 time period T2 than the discharge phase P1 time period T1 in a first operating mode (e.g., normal operating mode). In one aspect, by setting the voltage of bit lines BL, BLB to a reset voltage level in the reset phase P0 of the second operating mode (e.g., turbo operating mode), charging bit lines BL, BLB or setting the voltage of bit lines BL, BLB to a supply voltage level (e.g., VDD or 1V) in the precharge phase P1 can be performed faster than charging bit lines BL, BLB or setting the voltage of bit lines BL, BLB from a ground voltage level to a supply voltage level (e.g., VDD or 1V) in the first operating mode (e.g., normal operating mode). Therefore, the storage device 100 operating in the second operating mode (e.g., turbo operating mode) can have a shorter discharge phase P1 time period T2 than the discharge phase P1 time period T1 in the first operating mode (e.g., normal operating mode). By reducing the time period T2 for the discharge phase P1, the clock signal CLK' in the second operating mode (e.g., turbo operating mode) can have a higher frequency than the clock signal CLK in the first operating mode (e.g., normal operating mode), thereby allowing for a faster operating speed of the storage device 100.

[0052] Figure 6 This is a flowchart illustrating a method 600 for operating a storage device (e.g., storage device 100) according to an operating mode of the storage device, according to some embodiments. In some embodiments, method 600 is performed by a controller (e.g., memory controller 105 or bit line controller 112). In some embodiments, method 600 is performed by other entities. In some embodiments, method 600 includes... Figure 6 Show more, fewer, or different steps.

[0053] In one method, 610, a controller determines an operating mode of a storage device (e.g., storage device 100). Examples of operating modes include a first operating mode (e.g., a normal operating mode) and a second operating mode (e.g., a turbo operating mode). In one aspect, a storage device operating in the first operating mode (or normal operating mode) may consume less power or have less leakage current than in the second operating mode (or turbo operating mode). In one aspect, a storage device operating in the second operating mode (or turbo operating mode) may operate faster than in the first operating mode (or normal operating mode). The controller may obtain or receive, for example, a mode selection signal (e.g., mode selection signal 335) indicating the operating mode of the storage device from a processor or an external component coupled to the storage device. Based on the voltage, current, or state of the mode selection signal, the controller may determine the operating mode of the storage device.

[0054] In one method, 620, the controller determines a time period (e.g., T1 or T2) for a pre-charge phase (e.g., P1). For example, a storage device operating in a first operating mode (e.g., normal operating mode) may have a pre-charge phase time period (e.g., T1) that is longer than the pre-charge phase time period (e.g., T2) in a second operating mode (e.g., turbo operating mode). The controller may receive or acquire a mode selection signal and determine a time period corresponding to the operating mode of the storage device indicated by the mode selection signal. For example, in response to a mode selection signal 335 having a ground voltage level (e.g., GND or 0V) corresponding to the first operating mode, the controller may determine that the pre-charge phase time period is T1. For example, in response to a mode selection signal 335 having a power supply voltage level (e.g., VDD or 1V) corresponding to the second operating mode, the controller may determine that the pre-charge phase time period is T2, which is shorter than T1.

[0055] In one method, 630, the controller sets the voltage of bit line BL during a reset phase (e.g., P0) based on the operating mode of the memory device. For example, if the operating mode of the memory device indicated by the mode selection signal is a first operating mode (e.g., normal operating mode), the controller may disable the reset voltage control circuit 230, such that the voltage of bit line BL can be set to ground voltage level (e.g., GND or 0V). For example, if the operating mode of the memory device indicated by the mode selection signal is a second operating mode (e.g., turbo operating mode), the controller may enable the reset voltage control circuit 230, such that the voltage of bit line BL can be set to reset voltage level (e.g., VDD-Vth of a diode or transistor).

[0056] In one method, 640, the controller sets the voltage of bit line BL to a supply voltage level (e.g., VDD or 1V) during a defined time period, specifically during a pre-charge phase (e.g., P1). For example, the controller may enable pre-charge circuit 220 during the pre-charge phase, such that the voltage of bit line BL can be set to a supply voltage level (e.g., VDD or 1V).

[0057] In one method, the controller discharges bit line BL 650 during a sensing phase (e.g., P2) based on data stored in a memory cell (e.g., memory cell 125). For example, the controller may disable precharge circuit 220 and reset voltage control circuit 230 during the sensing phase. Simultaneously, the controller may provide word line control signal 325 or cause word line controller 114 to generate word line control signal 325 during the sensing phase to couple memory cell 125 to bit line BL. By i) disabling precharge circuit 220 and reset voltage control circuit 230 and ii) coupling memory cell 125 to bit line BL during the sensing phase, bit line BL can discharge based on the data stored in the memory cell. For example, the voltage of bit line BL may decrease based on the data stored in the memory cell.

[0058] In one method, 660, the controller determines the data stored by the memory cell 125 based on the voltage of bit line BL discharged during the sensing phase. For example, if the sensed voltage of bit line BL is lower than a reference voltage or the voltage of bit line BLB, the sense amplifier 240 can generate an output voltage corresponding to logic state '0'. For example, if the sensed voltage of bit line BL is higher than a reference voltage or the voltage of bit line BLB, the sense amplifier 240 can generate an output voltage corresponding to logic state '1'. After the sensing phase, the controller can proceed to step 610 or step 630 and operate in the subsequent reset phase.

[0059] Advantageously, the memory device can operate faster by setting the voltage of the bit lines to a second voltage level (e.g., VDD-Vth (threshold voltage) of the transistor). For example, a memory device 100 operating in a second operating mode (e.g., turbo operating mode) may have a shorter discharge phase P1 time period T2 than the discharge phase P1 time period T1 in a first operating mode (e.g., normal operating mode). In one aspect, charging the bit lines BL, BLB or setting the voltage of the bit lines BL, BLB from the reset voltage level to the supply voltage level (e.g., VDD or 1V) in the second operating mode (e.g., turbo operating mode) can be performed faster than charging the bit lines BL, BLB or setting the voltage of the bit lines BL, BLB from the ground voltage level (e.g., GND or 0V) to the supply voltage level (e.g., VDD or 1V) in the first operating mode (e.g., normal operating mode). Therefore, the storage device 100 operating in the second operating mode (e.g., turbo operating mode) can have a shorter discharge phase P1 time period T2 than the discharge phase P1 time period T1 in the first operating mode (e.g., normal operating mode). By reducing the discharge phase P1 time period T2, the storage device can operate faster in the second operating mode (e.g., turbo operating mode).

[0060] In one aspect, memory devices can be adaptively configured or operated in a selected mode by enabling or disabling the reset voltage control circuit. For example, in a first operating mode (or normal operating mode), the reset voltage control circuit can be disabled during the reset phase, allowing the bit line voltage to be discharged to ground. By setting the bit line voltage to ground during the reset phase, leakage current during the reset phase can be reduced in the first operating mode (or normal operating mode). For example, in a second operating mode (or turbo operating mode), the reset voltage control circuit can be enabled during the reset phase, thereby setting the bit line voltage to a second voltage level (e.g., VDD-Vth (threshold voltage) of the transistor). By setting the bit line voltage to the second voltage level (e.g., VDD-Vth) during the reset phase, memory devices in the second operating mode can perform, for example, read operations faster than in the first operating mode.

[0061] Now for reference Figure 7This diagram illustrates an example block diagram of a computing system 700 according to some embodiments of the present disclosure. A circuit or layout designer may use the computing system 700 for integrated circuit design. As used herein, “circuit” refers to the interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured to perform desired functions. The computing system 700 includes a host device 705 associated with a storage device 710. The host device 705 may be configured to receive input from one or more input devices 715 and provide output to one or more output devices 720. The host device 705 may be configured to communicate with the storage device 710, the input devices 715, and the output devices 720 via appropriate interfaces 725A, 725B, and 725C, respectively. The computing system 700 may be implemented in various computing devices such as computers (e.g., desktops, laptops, servers, data centers, etc.), tablet computers, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and / or layout design using the host device 705.

[0062] Input device 715 may include any of a variety of input technologies, such as a keyboard, stylus, touchscreen, mouse, trackball, keypad, microphone, voice recognition, motion recognition, remote control, input port, one or more buttons, dial, joystick, and any other input peripheral associated with host device 705 that allows external sources such as users (e.g., circuit or layout designers) to input information (e.g., data) into the host device and send instructions to the host device. Similarly, output device 720 may include a variety of output technologies, such as external memory, printer, speaker, display, microphone, LED, headphones, video device, and any other output peripheral configured to receive information (e.g., data) from host device 705. The “data” input to and / or output from host device 705 may include any of a variety of text data, circuit data, signal data, semiconductor device data, graphic data, combinations thereof, or other types of analog and / or digital data suitable for processing using computing system 700.

[0063] Host device 705 includes or is associated with one or more processing units / processors, such as central processing unit (“CPU”) cores 730A...730N. CPU cores 730A...730N may be implemented as application-specific integrated circuits (“ASICs”), field-programmable gate arrays (“FPGAs”), or any other type of processing unit. Each CPU core 730A...730N may be configured to execute instructions for running one or more applications of host device 705. In some embodiments, the instructions and data for running one or more applications may be stored within memory device 710. Host device 705 may also be configured to store the results of running one or more applications within memory device 710. Therefore, host device 705 may be configured to request memory device 710 to perform various operations. For example, host device 705 may request memory device 710 to read data, write data, update or delete data, and / or perform management or other operations. Host device 705 may be configured to run standard cell application 735. Standard cell application 735 may be part of a computer-aided design or electronic design automation software suite of standard cells that a user of host device 705 can use to create or modify circuits. In some embodiments, instructions for executing or running the standard cell application 735 may be stored within the storage device 710. The standard cell application 735 may be executed by one or more CPU cores 730A...730N using instructions associated with the standard cell application from the storage device 710. In one example, the standard cell application 735 allows a user to utilize a pre-generated schematic and / or layout design of the storage device 100 or a portion thereof to aid in integrated circuit design. After the layout design of the integrated circuit is completed, multiple integrated circuits, including, for example, storage device 100 or a portion thereof, may be manufactured by a manufacturing plant according to the layout design.

[0064] Still referencing Figure 7The storage device 710 includes a memory controller 740 configured to read data from or write data to the memory array 745. The memory array 745 may include various volatile and / or non-volatile memories. For example, in some embodiments, the memory array 745 may include NAND flash memory cores. In other embodiments, the memory array 745 may include NOR flash memory cores, static random access memory (SRAM) cores, dynamic random access memory (DRAM) cores, magnetoresistive random access memory (MRAM) cores, phase-change memory (PCM) cores, resistive random access memory (ReRAM) cores, 3DXPoint memory cores, ferroelectric random access memory (FeRAM) cores, and other types of memory cores suitable for use within the memory array. The memories within the memory array 745 may be controlled independently or individually by the memory controller 740. In other words, the memory controller 740 may be configured to communicate with each memory within the memory array 745 individually and independently. By communicating with the memory array 745, the memory controller 740 can be configured to read data from or write data to the memory array in response to instructions received from the host device 705. Although shown as part of the memory device 710, in some embodiments, the memory controller 740 may be part of the host device 705 or another component of the computing system 700 and associated with the memory device 710. The memory controller 740 may be implemented as logic circuitry in the form of software, hardware, firmware, or a combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller 740 may be configured to retrieve instructions associated with a standard cell application 735 stored in the memory array 745 of the memory device 710 after receiving a request from the host device 705.

[0065] It should be understood that, Figure 7 Only some components of the computing system 700 are shown and described herein. However, the computing system 700 may include other components such as various batteries and power supplies, networking interfaces, routers, switches, external storage systems, controllers, etc. In general, the computing system 700 may include any of a variety of hardware, software, and / or firmware components that are necessary or deemed necessary for performing the functions described herein. Similarly, the host device 705, input device 715, output device 720, and storage device 710, including memory controller 740 and memory array 745, may include other hardware, software, and / or firmware components that are deemed necessary or desirable for performing the functions described herein.

[0066] In one aspect of this disclosure, a memory device is disclosed. In some embodiments, the memory device includes a memory cell, a precharge circuit, a reset voltage control circuit, and a logic control circuit. In some embodiments, the precharge circuit is coupled to the memory cell via a bit line. In some embodiments, the precharge circuit is configured to set the voltage of the bit line to a first voltage level. In some embodiments, the reset voltage control circuit includes a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level. The transistor may be arranged or operated as a diode. In some embodiments, the logic control circuit is coupled to the precharge circuit and the reset voltage control circuit. In some embodiments, the logic control circuit: causes the reset voltage control circuit to set the voltage of the bit line to the second voltage level during a reset phase, and causes the precharge circuit to set the voltage of the bit line to the first voltage level during a precharge phase following the reset phase.

[0067] In the aforementioned memory device, the logic control circuit is configured to: discharge the bit line during the sensing phase following the pre-charging phase, based on the data stored in the memory cell, and determine the data stored in the memory cell during the sensing phase based on the voltage of the bit line discharged during the sensing phase.

[0068] In the aforementioned memory device, the logic control circuit is used to enable the reset voltage control circuit to set the voltage of the bit line to a second voltage level in a subsequent reset phase after the sensing phase.

[0069] In the aforementioned memory device, the logic control circuit is used to determine that the data stored in the memory cell is in a first state in response to the voltage of the bit line having a third voltage level, wherein the second voltage level is between the first voltage level and the third voltage level.

[0070] In the aforementioned memory device, the logic control circuit is configured to: disable the reset voltage control circuit to bypass setting the bit line voltage to the second voltage level during the reset phase if the operating mode of the memory device is the first mode, and enable the reset voltage control circuit to set the bit line voltage to the second voltage level during the reset phase if the operating mode of the memory device is the second mode.

[0071] In the aforementioned storage device, the logic control circuit is configured to: if the operating mode of the storage device is a first mode, set the voltage of the bit line to a first voltage level during a pre-charge phase of a first time period after the reset phase; and if the operating mode of the storage device is a second mode, set the voltage of the bit line to the first voltage level during a pre-charge phase of a second time period, the second time period being shorter than the first time period.

[0072] In the aforementioned storage device, the precharge circuit includes another transistor of the first type, while the reset voltage control circuit includes a transistor of the second type.

[0073] In the aforementioned memory device, another transistor is a P-type transistor, and another transistor is an N-type transistor, wherein the other transistor is coupled between the bit line and the first metal rail to receive the power supply voltage, and wherein the transistor is coupled between the bit line and the second metal rail to receive the power supply voltage.

[0074] In the aforementioned memory device, another transistor is a P-type transistor, and another transistor is an N-type transistor, wherein the other transistor is coupled between the bit line and the metal rail to receive the power supply voltage.

[0075] In the aforementioned storage devices, the other transistor of the first type is a P-type transistor, while the transistor of the second type is an N-type transistor.

[0076] In another aspect of this disclosure, a memory device is disclosed. In some embodiments, the memory device includes memory cells, bit lines coupled to the memory cells, and a controller. In some embodiments, if the operating mode of the memory device is a first mode, the controller is configured to set the voltage of the bit lines to a first voltage level during a reset phase. In some embodiments, if the operating mode of the memory device is a second mode, the controller is configured to set the voltage of the bit lines to a second voltage level during a reset phase.

[0077] In the aforementioned storage device, the first voltage level is lower than the second voltage level.

[0078] In the aforementioned memory device, the controller is configured to: set the voltage of the bit line to a third voltage level during a pre-charge phase following a reset phase; discharge the bit line during a sensing phase following a pre-charge phase based on the data stored in the memory cell; and determine the data stored in the memory cell during the sensing phase based on the voltage of the bit line discharged during the sensing phase.

[0079] In the aforementioned storage device, the third voltage level is higher than the first voltage level and the second voltage level.

[0080] In the aforementioned storage device, the controller is configured to: if the operating mode of the storage device is a first mode, set the voltage of the bit line to a third voltage level during a pre-charge phase in a first time period after the reset phase; and if the operating mode of the storage device is a second mode, set the voltage of the bit line to the third voltage level during a pre-charge phase in a second time period, the second time period being shorter than the first time period.

[0081] In another aspect of this disclosure, a method of operating a memory device is disclosed. In some embodiments, the method includes determining an operating mode of the memory device, comprising memory cells coupled to bit lines, by a controller. In some embodiments, the method includes determining a pre-charge phase time period by the controller based on the operating mode of the memory device. In some embodiments, the method includes setting the voltage of the bit lines to a first voltage level by the controller during the pre-charge phase. In some embodiments, the method includes discharging the bit lines according to data stored in the memory cells during a sensing phase following the pre-charge phase. In some embodiments, the method includes determining the data stored in the memory cells during the sensing phase by the controller based on the voltage of the bit lines discharged during the sensing phase.

[0082] The above method further includes: if the operating mode of the storage device is a first mode, then during the reset phase prior to the precharge phase, the voltage of the bit line is set to a second voltage level by the controller; and if the operating mode of the storage device is a second mode, then during the reset phase, the voltage of the bit line is set to a third voltage level by the controller.

[0083] In the above method, the third voltage level is between the first voltage level and the second voltage level.

[0084] In the above method, the time period of the second mode is shorter than that of the first mode.

[0085] The method further includes: if the operating mode of the storage device is a first mode, then in a subsequent reset phase after the sensing phase, the voltage of the bit line is set to a second voltage level by the controller; and if the operating mode of the storage device is a second mode, then in a subsequent reset phase, the voltage of the bit line is set to a third voltage level by the controller.

[0086] The term "coupling" and its variations include joining two components directly or indirectly to each other. The term "electrical coupling" and its variations include joining two components directly or indirectly to each other by means of a conductive material (e.g., a metal or copper trace). This coupling can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). This coupling can be achieved by directly coupling or mutually coupling two components, by coupling two components to each other using a single intermediate component, by coupling two components to each other with any additional intermediate component, or by coupling two components to each other using an intermediate component integrally formed with one of the two components as a single whole. If "coupling" or its variations are modified by an additional term (e.g., direct coupling), the general definition of "coupling" provided above is modified by the simple linguistic meaning of the additional term (e.g., "direct coupling" means the joining of two components without any separate intermediate component), obtaining a narrower definition than the general definition of "coupling" provided above. This coupling can be mechanical, electrical, or fluid.

[0087] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A storage device, comprising: Memory unit; A pre-charge circuit is coupled to the memory cell via a bit line, and the pre-charge circuit sets the voltage of the bit line to a first voltage level. A reset voltage control circuit includes a transistor coupled to the bit line to set the voltage of the bit line to a second voltage level, the transistor operating as a diode; as well as A logic control circuit, coupled to the precharge circuit and the reset voltage control circuit, is configured to: cause the reset voltage control circuit to set the voltage of the bit line to the second voltage level during the reset phase; The pre-charge circuit sets the voltage of the bit line to the first voltage level during the pre-charge phase following the reset phase. Furthermore, in response to the voltage of the bit line having a third voltage level during the sensing phase, the data stored in the memory cell is determined to be in a first state, wherein the second voltage level is between the first voltage level and the third voltage level.

2. The storage device according to claim 1, wherein, In order to determine that the stored data is in the first state, the logic control circuit is used to: Based on the data stored in the memory cell, the bit line is discharged during the sensing phase following the pre-charge phase, and The data stored in the memory cell during the sensing phase is determined based on the voltage of the bit line discharged during the sensing phase.

3. The storage device according to claim 2, wherein, The logic control circuit is used to enable the reset voltage control circuit to set the voltage of the bit line to the second voltage level in a subsequent reset phase after the sensing phase.

4. The storage device according to claim 1, wherein, The logic control circuit is a field-programmable gate array (FPGA).

5. The storage device according to claim 1, wherein, The logic control circuit is used for: If the operating mode of the storage device is the first mode, the reset voltage control circuit is disabled to bypass setting the voltage of the bit line to the second voltage level during the reset phase, and If the operating mode of the memory device is the second mode, then the reset voltage control circuit is enabled to set the voltage of the bit line to the second voltage level during the reset phase.

6. The storage device according to claim 5, wherein, The logic control circuit is used for: If the operating mode of the storage device is the first mode, then the precharge circuit sets the voltage of the bit line to the first voltage level during the precharge phase of a first time period after the reset phase, and If the operating mode of the storage device is the second mode, then the pre-charge circuit sets the voltage of the bit line to the first voltage level during the pre-charge phase of the second time period, which is shorter than the first time period.

7. The storage device according to claim 1, wherein, The precharge circuit includes another transistor of the first type, wherein the reset voltage control circuit includes the transistor of the second type.

8. The storage device according to claim 7, wherein, The other transistor is a P-type transistor, and the transistor is an N-type transistor, wherein the other transistor is coupled between the bit line and the first metal rail to receive the power supply voltage, and wherein the transistor is coupled between the bit line and the second metal rail to receive the power supply voltage.

9. The storage device according to claim 7, wherein, The other transistor is a P-type transistor, and the transistor is an N-type transistor, wherein the other transistor is coupled between the bit line and the metal rail to receive the power supply voltage, and wherein the transistor is coupled between the bit line and the metal rail to receive the power supply voltage.

10. The storage device according to claim 7, wherein, The other transistor of the first type is a P-type transistor, while the transistor of the second type is an N-type transistor.

11. A storage device comprising: Memory unit; Bit lines are coupled to the memory cells; as well as The controller is configured to: if the operating mode of the storage device is a first mode, set the voltage of the bit line to a first voltage level during the reset phase; and if the operating mode of the storage device is a second mode, set the voltage of the bit line to a second voltage level during the reset phase. During the pre-charge phase following the reset phase, the voltage of the bit line is set to a third voltage level, wherein the third voltage level is higher than the first voltage level and the second voltage level.

12. The storage device according to claim 11, wherein, The first voltage level is lower than the second voltage level.

13. The storage device according to claim 11, wherein, The controller is used for: Based on the data stored in the memory cell, the bit line is discharged during the sensing phase following the pre-charge phase, and The data stored in the memory cell during the sensing phase is determined based on the voltage of the bit line discharged during the sensing phase.

14. The storage device according to claim 12, wherein, The memory unit is a static random access memory unit.

15. The storage device according to claim 11, wherein, The controller is used for: If the operating mode of the storage device is the first mode, then during the pre-charge phase in the first time period after the reset phase, the voltage of the bit line is set to the third voltage level, and If the operating mode of the storage device is the second mode, the voltage of the bit line is set to the third voltage level during the pre-charge phase of the second time period, which is shorter than the first time period.

16. A method of operating a storage device, comprising: The operating mode of the storage device is determined by a controller, the storage device including a memory cell coupled to a bit line; The controller determines the time period of the pre-charging phase based on the operating mode of the storage device; During the pre-charging phase of the time period, the voltage of the bit line is set to a first voltage level by the controller; Based on the data stored in the memory cell, during the sensing phase following the pre-charging phase, the bit line is discharged by the controller. The controller determines the data stored in the memory cell during the sensing phase based on the voltage of the bit line discharged during the sensing phase. as well as If the operating mode of the storage device is the first mode, then during the reset phase before the pre-charge phase, the controller sets the voltage of the bit line to the second voltage level. as well as If the operating mode of the storage device is the second mode, then during the reset phase, the controller sets the voltage of the bit line to a third voltage level, wherein the third voltage level is between the first voltage level and the second voltage level.

17. The method according to claim 16, wherein, The first voltage level is lower than the second voltage level.

18. The method according to claim 16, wherein, The memory unit is a static random access memory unit.

19. The method of claim 16, wherein, The time period of the second mode is shorter than that of the first mode.

20. The method of claim 16, further comprising: If the operating mode of the storage device is the first mode, then in the subsequent reset phase after the sensing phase, the controller sets the voltage of the bit line to the second voltage level. as well as If the operating mode of the storage device is the second mode, then during the subsequent reset phase, the voltage of the bit line is set to the third voltage level by the controller.

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