Capacitor structure including ferroelectric capacitor and semiconductor device

Abstract

A capacitor structure including a ferroelectric capacitor and a semiconductor device are provided. The semiconductor device includes a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure includes a plate line extending in a first direction, a ferroelectric capacitor connected to the plate line, a global plate line disposed at the same height as the plate line, and a plate line selection transistor connected to the global plate line and the plate line. The transistor structure includes an access transistor having a gate connected to a word line, one end connected to the ferroelectric capacitor, and the other end connected to a bit line.

Description

Technical Field

[0001] This disclosure relates to ferroelectric capacitors, and more specifically, to a capacitor structure and semiconductor device including a ferroelectric capacitor. Background Technology

[0002] Ferroelectric random access memory (FRAM) is being investigated as a type of non-volatile memory configured to retain data even when power is removed. FRAM has a simpler structure than dynamic random access memory (DRAM) but can be implemented as a high-density non-volatile memory device, such as flash memory. FRAM with a three-dimensional stacked structure can be developed to achieve high density. Summary of the Invention

[0003] In some examples, to overcome the scaling limitations in three-dimensional memory structures, '1TnC' structure FRAMs can be developed. '1TnC' refers to a memory cell unit formed by one access transistor '1T' and 'n' ferroelectric capacitors 'nC'. However, to implement a '1TnC' structure FRAM cell array in a three-dimensional structure, a considerable number of board-line pads or contact plugs may be required compared to the cell area. Therefore, techniques to reduce the number of board-line pads can be explored in the implementation of 3D FRAM devices.

[0004] Embodiments of this disclosure provide a three-dimensional ferroelectric storage device with a reduced number of board wire pads and a method for manufacturing the same.

[0005] One aspect of this disclosure provides a semiconductor device including a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure may include: a board line extending in a first direction, a ferroelectric capacitor connected to the board line, a global board line disposed at the same height as the board line, and a board line select transistor connected to the global board line and the board line. The transistor structure may include an access transistor having a gate connected to a word line, one end connected to the ferroelectric capacitor, and the other end connected to a bit line.

[0006] Another aspect of this disclosure provides a capacitor structure comprising: a board line, a ferroelectric capacitor connected to the board line, a global board line disposed at the same height as the board line, and a board line selection transistor connected to the global board line and the board line.

[0007] Another aspect of this disclosure provides a semiconductor device including a cell array and an address decoder. The cell array includes a plurality of memory cells respectively disposed at intersections of word lines and bit lines. The address decoder is configured to send word line signals and global board line signals to word lines and a plurality of global board lines, respectively. Each of the plurality of memory cells may include: a board line; a ferroelectric capacitor connected to the board line; an access transistor having a gate connected to a corresponding word line, one end connected to the ferroelectric capacitor, and the other end connected to a corresponding bit line; the global board line; and a board line selection transistor connecting the global board line and the board line. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the manufacturing process of an example ferroelectric storage device.

[0009] Figure 2 This is a cross-sectional view showing an example of a ferroelectric storage device.

[0010] Figure 3 This is a block diagram illustrating an example of a ferroelectric storage device.

[0011] Figure 4 It is shown Figure 3 Cross-sectional view and equivalent circuit diagram of the 1TnC structure memory cell MC.

[0012] Figure 5 This is a circuit diagram illustrating an example structure of a three-dimensional array of 1TnC memory cells formed in a global board-line structure.

[0013] Figure 6 This is a circuit diagram that briefly illustrates an example of applying a global board line (GPL) to a memory cell (MC).

[0014] Figure 7 This is a diagram illustrating the characteristics of an example ferroelectric capacitor.

[0015] Figure 8 This is a diagram illustrating an example of a write operation of an example ferroelectric memory cell.

[0016] Figure 9 This is a diagram illustrating an example of a readout operation for a ferroelectric capacitor.

[0017] Figure 10 This is a waveform diagram that briefly illustrates an example of a read operation and a rewrite operation in a global board line structure example.

[0018] Figure 11 This is a diagram showing an example arrangement of the plate line contact plug.

[0019] Figure 12 This is a diagram showing an example arrangement of the plate line contact plug.

[0020] Figure 13 This is a diagram showing an example arrangement of the plate line contact plug.

[0021] Figure 14 This is a diagram showing an example arrangement of the plate line contact plug.

[0022] Figure 15 This is a circuit diagram illustrating an example of applying global board lines to a single memory cell.

[0023] Figure 16 It is shown that... Figure 15 A perspective view of a portion of a semiconductor device corresponding to a circuit diagram.

[0024] Figure 17A , Figure 17B and Figure 17C It is along Figure 16 The cross-sectional views taken by lines A1-A1', B1-B1', and C1-C1'.

[0025] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E , Figure 18F , Figure 18G , Figure 18H , Figure 18I , Figure 18J , Figure 18K , Figure 18L , Figure 18M and Figure 18N The manufacturing process is shown sequentially. Figure 16 A cross-sectional view of the method for the semiconductor device shown.

[0026] Figure 19 This is a perspective view showing an example of a semiconductor device.

[0027] Figure 20 This is a perspective view showing an example of a semiconductor device.

[0028] Figure 21 It is shown that... Figure 15 A perspective view of the semiconductor device corresponding to the circuit diagram.

[0029] Figure 22A , Figure 22B and Figure 22C It is along Figure 16 The cross-sectional view taken by lines A2-A2', B1-B1' and C1-C1'.

[0030] Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23F , Figure 23G and Figure 23H It sequentially illustrates the methods for manufacturing semiconductor devices, along... Figure 21 The cross-sectional view taken from line A2-A2'.

[0031] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 24E , Figure 24F , Figure 24G and Figure 24H It sequentially illustrates the methods for manufacturing semiconductor devices, along... Figure 21 The cross-sectional view taken from line B1-B1'.

[0032] Figure 25A , Figure 25B , Figure 25C , Figure 25D , Figure 25E , Figure 25F , Figure 25G and Figure 25H It sequentially illustrates the methods for manufacturing semiconductor devices, along... Figure 21 The cross-sectional view taken from line C1-C1'.

[0033] Figure 26 This is a perspective view showing an example of a semiconductor device.

[0034] Figure 27 This is a perspective view showing an example of a semiconductor device. Detailed Implementation

[0035] It should be understood that the foregoing general description and the following detailed description are examples, and additional descriptions of this disclosure should be considered as provided. Reference numerals are shown in detail in exemplary embodiments of this disclosure, and examples of this disclosure are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the specification and drawings to refer to the same or similar parts; in such cases, for brevity, repetitive descriptions may be omitted.

[0036] Figure 1 This is a diagram illustrating the manufacturing process of a ferroelectric storage device according to at least some embodiments of the present disclosure. Reference Figure 1 The ferroelectric memory device 1200 can be formed into a stacked semiconductor memory by applying a wafer bonding method.

[0037] Integrated circuits are formed on each of the first wafer WF1 and the second wafer WF2. For example, a cell array can be formed on the first wafer WF1, and peripheral circuitry (configured as a control unit array) can be formed on the second wafer WF1. The peripheral circuitry may include voltage generators, decoders, control circuitry, etc.

[0038] First wafer WF1 and second wafer WF2 are bonded using a hybrid bonding method. That is, the metal (e.g., copper) of each of the first wafer WF1 and second wafer WF2 is bonded to each other, and the dielectric (e.g., oxide layer) of each of the first wafer WF1 and second wafer WF2 is bonded to each other. Bonding is achieved by processing the surfaces of the first wafer WF1 and second wafer WF2 through planarization and cleaning processes. The dielectric is then bonded by applying pressure under low-pressure conditions. Finally, the metal filling the upper and lower vias is bonded by heat treatment.

[0039] The bonded wafers WF1 and WF2 are diced into multiple chips. Each diced chip is then provided as a stacked ferroelectric memory device 1200 in which the upper semiconductor die and the lower semiconductor die are bonded.

[0040] Figure 2 This is a cross-sectional view showing a ferroelectric storage device according to at least some embodiments of the present disclosure. Reference Figure 2 The ferroelectric memory device 1200 has a chip-to-chip (C2C) structure. To form the ferroelectric memory device 1200 with a C2C structure, an upper chip including cell portions (CELL) is fabricated on a first wafer, and a lower chip including peripheral circuit portions (PERI) is fabricated on a second wafer different from the first wafer. Then, the ferroelectric memory device 1200 with a C2C structure is formed by bonding the upper chip and the lower chip at bonding surfaces (I-I').

[0041] The peripheral circuitry portion (PERI) may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220 formed on the first substrate 210, a first metal layer 230 connected to each of the plurality of circuit elements 220, and a second metal layer 240 formed on the first metal layer 230. In some embodiments, the first metal layer 230 may be formed of a first metal having relatively high resistance (e.g., tungsten), and the second metal layer 240 may be formed of a second metal having relatively low resistance (e.g., copper). However, the material types of the first metal layer 230 and the second metal layer 240 are not limited to those disclosed herein.

[0042] An interlayer insulating layer 215 is disposed on the first substrate 210 to cover a plurality of circuit elements 220, a first metal layer 230, and a second metal layer 240, and may include an insulating material, such as silicon oxide, silicon nitride, and / or combinations thereof. A lower bonding metal 270 may be formed on the second metal layer 240 of the board-to-board bonding region (PLBA). In the PLBA, the lower bonding metal 270 of the peripheral circuit portion (PERI) can be electrically connected to the upper bonding metal 370 of the cell portion (CELL) by a bonding method, and the lower bonding metal 270 and the upper bonding metal 370 may include aluminum, copper, tungsten, and / or combinations thereof.

[0043] The cell portion may include a second substrate 310 and a base layer 320 on which access transistors are formed. On the second substrate 310, multiple board lines 330 (e.g., 331, 332, 333, 334, 335, 336, 337) may be stacked along a third direction D3 perpendicular to the upper surface of the second substrate 310.

[0044] In the board line bonding area (PLBA), an internal node IN can extend in a direction perpendicular to the upper surface of the second substrate 310 and pass through the board line 330. The internal node IN may include a ferroelectric layer, a channel layer, etc. In the PLBA, the board line 330 can extend along a first direction D1 parallel to the upper surface of the second substrate 310 and can be connected to a plurality of contact plugs 340 (e.g., 341, 342, 343, 344, 345, 346, 347). The board line 330 and the contact plugs 340 can be connected to each other at pads provided by extending at least some of the board line 330 at different lengths along the first direction D1. In the PLBA, the contact plugs 340 connected to the board line 330 can be connected to the peripheral circuit section PERI via an upper bonding metal 370 of the cell section CELL and a lower bonding metal 270 of the peripheral circuit section PERI. In some embodiments, one or more metal layers may be formed between the lower bonding metal 270 and the upper bonding metal 370.

[0045] Contact plug 340 transmits the board line voltage VPL to each of the board lines 330. Contact plug 340, also referred to as a board line pad, can be configured to provide electrical connection to the outside of the chip. For example, the board line voltage VPL is transmitted to the contact plug 340 and the board line 330 via a lower bonding metal 270 and an upper bonding metal 370 connected to the upper portions of the first metal layer 230 and the second metal layer 240. Here, the bonding of the lower bonding metal 270 and the upper bonding metal 370 is referred to as a board line bond 400. The board line bond 400, formed by the lower bonding metal 270 and the upper bonding metal 370, provides the board line voltage VPL to each of the board lines 330.

[0046] The contact plugs 340 or pads used to connect the bonding metal 370 and the board line 330 occupy a relatively large area and resources. Furthermore, there is a problem that the number of contact plugs 340 is actually excessively increased in order to form a '1TnC' structure 3D FRAM. In some examples, global board line methods and word line structures are provided, which can be used to reduce the number of contact pads or contact plugs 340 in a '1TnC' structure 3D FRAM.

[0047] Figure 3 This is a block diagram illustrating some embodiments of ferroelectric storage devices according to this disclosure. Reference Figure 3 The ferroelectric storage device 1200 may include a cell array 1210, an address decoder 1220, a read / write circuit 1230, a control logic circuit 1240, and a voltage generator 1250.

[0048] Cell array 1210 may include multiple ferroelectric memory cells MC. In these cases, ferroelectric memory device 1200 may be referred to as FeRAM (ferroelectric random access memory) or FRAM. The multiple ferroelectric memory cells MC may be arranged in the region where word lines WL0 to WLi-1 and bit lines BL0 to BLj-1 intersect, and may form a matrix. Each ferroelectric memory cell MC may be connected to a corresponding word line WL and bit line BL. Simultaneously, each ferroelectric memory cell MC may be connected to at least one board line PL. In this case, the at least one board line PL may be arranged corresponding to each word line WL, but is not limited thereto.

[0049] Each ferroelectric memory cell (MC) may include an access transistor and at least one ferroelectric capacitor. The at least one ferroelectric capacitor included in the MC can store and discharge a charge corresponding to data. According to some embodiments, multiple ferroelectric memory cells (MCs) can store multiple bits of data. In this case, according to the embodiment, one multiple bit of data can be stored in one ferroelectric memory cell, or one multiple bit of data can be stored in several ferroelectric memory cells. The ferroelectric memory cells storing multiple bits of data (one or more) can be configured to store a charge corresponding to the multiple bits of data using the ferroelectric capacitors included in the ferroelectric memory cells. The charge stored in the ferroelectric capacitors can be discharged through bit lines connected to the ferroelectric memory cells.

[0050] Specifically, the board lines used to configure the cell array 1210 can be formed as a global board line structure. Access to a memory cell MC is performed by turning on the access transistor AT via the word line and activating the board line. Therefore, in the global board line structure of this disclosure, the access transistor AT and board line select transistor PLST of all memory cells connected to the word line can be turned on by the word line signal VWL. The board line select transistor PLST can transmit the global board line signal VGPL to each board line of the memory cell MC according to the word line signal VWL. Finally, in the cell array 1210 of the global board line structure, the activation of a board line can be achieved by a combination of the global board line signal VGPL and the word line signal VWL. This structure will be described in more detail with reference to the accompanying drawings described below.

[0051] Address decoder 1220 is configured to select a word line or global board line (GPL) of cell array 1210 in response to address ADDR. Address decoder 1220 sends a word line signal VWL to the word line of the selected memory region or cell. During a read or write operation, address decoder 1220 can provide word line signal VWL and global board line signal VGPL to select a cell or board line. The access transistor AT of the cell MC selected by word line signal VWL is turned on. In addition, the board line selection transistor PLST connected to each of the cells in the corresponding word line is turned on by word line signal VWL. Address decoder 1220 can then activate the board line of one of the cells by providing global board line signal VGPL to one of the selected global board lines.

[0052] The read / write circuit 1230 serves as a write driver or sense amplifier for accessing the cell array 1210. The read / write circuit 1230 is configured to detect data stored in the memory cell MC. Specifically, the read / write circuit 1230 detects data stored in the memory cell MC by comparing the bit line voltage VBL, based on the amount of charge released from the memory cell MC to the bit line BL, with a reference voltage Vref. The data detected by the read / write circuit 1230 can be output to the outside of the ferroelectric storage device 1200. Additionally, the read / write circuit 1230 can transmit write data from an external source to the cell array 1210.

[0053] Control logic circuitry 1240 is configured to control read / write circuitry 1230, address decoder 1220, and voltage generator 1250 in response to a command CMD received from an external source. Control logic circuitry 1240 can control voltage generator 1250, read / write circuitry 1230, and address decoder 1220 to perform write, read, and rewrite operations on selected memory cells according to the command CMD. For this purpose, control logic circuitry 1240 may include a command decoder configured to decode the command CMD received from an external device.

[0054] Voltage generator 1250 is configured, under the control of control logic circuit 1240, to generate a word line signal VWL to be supplied to word line WL and a global board line signal VGPL to be supplied to global board line GPL. Voltage generator 1250 can also generate a bit line voltage VBL to be supplied to bit line BL under the control of control logic circuit 1240.

[0055] As described above, the ferroelectric memory device 1200 may include a cell array 1210 forming a global board line structure. Activation of any board line of the memory cell selected via the global board line structure can be performed by a combination of a global board line signal VGPL and a word line signal VWL. This structure serves to electrically connect the board lines to the peripheral circuitry section (PERI, see below). Figure 2 The area occupied by the contact plugs or pads can be minimized.

[0056] Figure 4 It is shown Figure 3 Cross-sectional view and equivalent circuit diagram of the 1TnC structure memory cell MC. (Reference) Figure 4 The pillars or internal nodes IN that form the memory cell MC are formed by passing through the board lines PL1, PL2, PL3, and PL4. Furthermore, the bit line BL and word line WL for forming the access transistor AT are formed at the bottom. Here, as an example, the structure of the memory cell MC, which forms an access transistor AT and four ferroelectric capacitors FC1 to FC4, will be described.

[0057] The internal node IN penetrates the board lines PL1, PL2, PL3, and PL4, as well as the insulating material between the board lines, and connects to the drain of the access transistor AT. Therefore, the internal node IN can be considered as forming the drain of the access transistor AT. Ferroelectric material FM is formed on the outer surface of the cylindrical internal node IN. The ferroelectric material FM can store data through polarization. The polarization state can be switched by an electric field formed between the internal node IN and the board lines PL1, PL2, PL3, and PL4. The access transistor AT connects the bit line BL to the internal node IN according to the word line signal VWL transmitted to the word line WL. The gate electrode GD can be formed around the word line WL to form the access transistor AT.

[0058] As shown in the equivalent circuit, the memory cell MC of the '1T4C' structure is formed by the structure described above. To activate a ferroelectric capacitor FCk, the access transistor AT must be turned on by the word line WL, and a board line signal must be applied to one of the board lines PL1, PL2, PL3, and PL4. In the case of the memory cell MC shown, the channel of the access transistor AT is formed as a two-dimensional transistor parallel to the substrate. However, the channel of the access transistor AT can be implemented as a transistor perpendicular to the substrate (e.g., a vertical channel transistor). In these cases, the bit line BL can be located below the word line WL.

[0059] Each of the ferroelectric capacitors FCk may include a ferroelectric material. The ferroelectric material may include at least one of lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and / or lanthanum bismuth titanate (BLT). Furthermore, the ferroelectric capacitor FCk may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, lead zirconium titanium oxide, or combinations thereof. Here, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide, or it may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O). Each ferroelectric capacitor FCk may also include a dopant element doped into the aforementioned materials. The doping element may be selected from the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), tin (Sn) and / or combinations thereof.

[0060] The '1T4C' memory cell MC structure has been briefly described above. However, for ease of explanation, the circuit structure of the memory cell MC shown is a simplified structure, and the actual memory block is not limited to the example shown. That is, it will be well understood that a memory cell MC can include more ferroelectric capacitors.

[0061] Figure 5 This is a circuit diagram showing the structure of a three-dimensional array of '1TnC' memory cells formed within a global board-line structure. (Reference) Figure 5 In cell array 1210, ferroelectric capacitors located on the same layer share the same global plate line (GPL). <k>The access transistor AT, connected to the memory cell of the corresponding word line WL, and the board line selection transistor PLST, used to connect the board lines of each layer and the global board line, are simultaneously turned on. Therefore, a contact plug (340, see [link]) must be formed to drive the board line. Figure 2 Alternatively, the number of pads can be set to be only as many as the number of global board lines (GPLs).

[0062] Multiple memory cells MC0 to MCk-1 can be connected to word line WL <0> The access transistors AT0 to ATk-1 of each of the multiple memory cells MC0 to MCk-1 can be supplied to the word line WL <0> The word line signal VWL is turned on or off. Each of the memory cells MC0 to MCk-1 can be connected to the corresponding bit line BL only when the access transistors AT0 to ATk-1 are turned on. <0> To BL <i-1>.

[0063] Board line selects transistor PLST0 based on slave word line WL <0> The provided word line signal VWL is used to turn the board line on or off. The board line selection transistor PLST0 is configured to activate the global board line GPL based on its activation. <0> To GPL <j-1>PL on the same layer <0> To PL <j-1>Connect or disconnect (or block). For example, if the board line select transistor PLST0 is supplied to the word line WL <0> If the word line signal VWL is turned on, then the global board line GPL will be activated. <0> To GPL <j-1>Board lines PL<0,0> to PL<0,0> connected to memory cells MC0 to MCk-1 respectively<j-1,0> Therefore, the activation of the ferroelectric capacitor in a selected memory cell depends on the global plate line GPL applied. <0> To GPL <j-1>The global board line signal VGPL is used for each of the memory cells. Therefore, it is not necessary to form contact plugs or pads for all board lines to activate the ferroelectric capacitors of each memory cell. Only the global board line GPL needs to be applied. <0> To GPL <j-1>Each of these forms a contact plug or pad. That is, the number of contact plugs or pads can be as many as the number of stacked global board lines. Therefore, the chip area of ​​the contact plugs or pads can be minimized.

[0064] Word line WL <0> To WL <i-1>Each of these must simultaneously control the access transistor AT of each memory cell and the board line selection transistor PLST of each layer. Therefore, the word line WL extending in the horizontal direction D1... <0> To WL <i-1>Each of them can be extended by changing its direction to the vertical direction D3. That is, the word line WL <0> To WL <i-1>Each of these can be formed into the shape of the letter 'L'. The letter line WL on the horizontal direction D1... <0> To WL <i-1>Each of them can form the common gate of access transistors AT0 to ATk-1, and the word line WL on the vertical direction D3. <0> To WL <i-1>Each of them can form the common gate of each of the board line selection transistors PLST0 to PLSTi-1.

[0065] According to the cell array 1210 of the global board line structure of this disclosure, each layer of board lines can share the global board line GPL of the same layer. Additionally, word lines WL... <0> To WL <i-1>Each of these can simultaneously turn on the board line select transistor PLST and the access transistor AT of the connected memory cell. Therefore, contact plugs or pads for activating the board line can be formed only on the global board line GPL.

[0066] Figure 6 This is a graph illustrating the hysteresis characteristics of the ferroelectric capacitor of this disclosure. (Reference) Figure 6 Ferroelectric capacitors FC exhibit hysteresis loop characteristics to the cell voltage Vcell applied across their terminals.

[0067] The horizontal axis of the cell characteristic curve represents the cell voltage Vcell applied across the ferroelectric capacitor FC, and the vertical axis represents the total charge Q or polarization induced on the surface of the ferroelectric capacitor FC according to the cell voltage Vcell. Furthermore, 'Qr' represents the residual charge, 'Qs' represents the saturation charge, and 'Vc' represents the coercive voltage. The coercive voltage Vc represents the magnitude of the voltage required to make the total charge of the ferroelectric capacitor FC '0'. Meanwhile, 'VPL' and 'VBL' indicated across the ferroelectric capacitor FC represent the voltage applied through the plate line PL and the voltage applied through the bit line BL, respectively.

[0068] As the unit voltage Vcell increases from '0' in the positive direction, polarization occurs in the ferroelectric material of the ferroelectric capacitor FC, and the total charge Q of the ferroelectric capacitor FC increases. When the unit voltage Vcell becomes the positive saturation voltage +Vcc, the total charge Q reaches point 'a', which corresponds to the saturation charge +Qs. At this point, even if the unit voltage Vcell increases further, the total charge Q will not increase further. In other words, when the unit voltage Vcell is greater than the positive saturation voltage +Vcc, the ferroelectric capacitor FC enters a saturated polarization state. Afterward, even if the unit voltage Vcell decreases back to '0', the polarization direction is maintained. Therefore, the total charge Q moves along the curve and reaches point 'b', where point 'b' is the non-zero residual charge +Qr.

[0069] When the total charge Q is a residual charge (+Qr, point 'b'), as the unit voltage Vcell increases in the negative direction, the total charge Q moves from point 'b' along the curve, passes 0, and becomes a negative saturated charge (-Qs, point 'c'). Even if the unit voltage Vcell increases in the negative direction beyond the negative saturation voltage -Vcc, the total charge Q will not increase further in the negative direction. That is, even when the unit voltage Vcell is lower than the negative saturation voltage -Vcc, the ferroelectric capacitor FC enters a saturated polarization state. At this time, the polarization direction of the ferroelectric material in the ferroelectric capacitor FC becomes opposite to the polarization direction at point 'a'. Afterwards, even if the unit voltage Vcell becomes '0' again, the polarization direction is maintained, and the total charge Q moves along the curve and becomes a negative residual charge that is not '0' (-Qr, point 'd'). On the other hand, if the unit voltage Vcell increases again in the positive direction at point 'd', the total charge moves from point 'd' along the curve, passes '0', and changes to point 'a'.

[0070] Based on the above, when a unit voltage Vcell with a positive saturation voltage +Vcc or a negative saturation voltage -Vcc is applied across the ferroelectric capacitor FC, the polarization direction due to spontaneous polarization is maintained even if the applied voltage is removed. The surface charge of the ferroelectric material caused by spontaneous polarization is not naturally lost due to leakage or other reasons. If a coercive voltage (+Vc or -Vc) is not applied to make the polarization '0', the polarization direction is maintained as is.

[0071] According to some implementations, a state in which a positive saturation voltage +Vcc is applied to and then removed from the ferroelectric capacitor FC (e.g., a state where the total charge Q is a positive residual charge (+Qr, point 'b')) can correspond to a state in which data '0' is stored in the ferroelectric capacitor FC. Conversely, a state in which a negative saturation voltage -Vcc is applied to and then removed from the ferroelectric capacitor FC (e.g., a state in which the total charge Q is a negative residual charge (-Qr, point 'd')) can correspond to a state in which data '1' is stored in the ferroelectric capacitor FC. However, the logical value of the data to be stored is not limited to the disclosure herein.

[0072] Figure 7 This is a diagram illustrating the write operation of a ferroelectric memory cell according to some embodiments of this disclosure. (See reference) Figure 7 Based on the data written, saturation polarization occurs in different directions in the ferroelectric capacitor FC.

[0073] In the write operation of data '1', the word line signal VWL, used to turn on the access transistor AT, is applied to the word line WL. Then, the saturation voltage Vcc is applied to the bit line BL, and 0V is applied to the plate line PL. Then, the cell voltage Vcell across the ferroelectric capacitor FC becomes the negative saturation voltage -Vcc. At this time, saturation polarization occurs in the ferroelectric capacitor FC in the 'P1' direction. The total charge Q of the ferroelectric capacitor FC is located at point 'c'. Afterwards, even if the cell voltage Vcell is removed, the polarization direction is maintained, and the total charge Q moves to point 'd'. In this way, data '1' can be written to the ferroelectric capacitor FC.

[0074] During the write operation of data '0', the word line signal VWL is applied to word line WL to turn on the access transistor AT. Then, 0V is applied to bit line BL, and the positive saturation voltage +Vcc is applied to plate line PL. Then, the cell voltage Vcell across the ferroelectric capacitor FC becomes the positive saturation voltage +Vcc. At this time, saturation polarization occurs in the ferroelectric capacitor FC in the 'P0' direction, and the total charge Q of the ferroelectric capacitor FC is located at point 'a'. Afterwards, even if the cell voltage Vcell is removed, the polarization direction is maintained, and the total charge moves to point 'b'. As described above, the write of data '0' to the ferroelectric capacitor FC is performed.

[0075] Figure 8 This is a diagram illustrating the reading operation of the ferroelectric capacitor of this disclosure. (Reference) Figure 8 When reading data stored in the ferroelectric capacitor FC, the plate line voltage VPL, at the saturation voltage Vcc level, is supplied to the plate line PL. Then, the word line signal VWL, used to turn on the access transistor AT, is applied to the gate of the access transistor AT. In this state, the polarization direction of the ferroelectric capacitor FC can be switched or maintained depending on the stored data.

[0076] During a read operation, a voltage of the same level as that used to write data '0' is applied across the ferroelectric capacitor FC. For example, during a read operation, the bit line BL can be pre-charged to 0V, and a saturation voltage Vcc can be applied to the plate line PL. In this case, the polarization direction of the ferroelectric capacitor FC can be switched or maintained depending on the type of data being stored. When the polarization direction is switched, a relatively large amount of charge is discharged from the ferroelectric capacitor FC to the bit line BL. On the other hand, when the polarization direction is maintained, a relatively small amount of charge is discharged from the ferroelectric capacitor FC to the bit line BL. Based on the difference in the amount of charge discharged to the bit line BL, the read amplifier of the read / write circuit 1230 can identify the data.

[0077] When data '1' is stored in the ferroelectric capacitor FC, the total charge Q of the ferroelectric capacitor FC is located at point 'd', and the polarization direction corresponds to 'P1'. At this time, the word line signal VWL, used to turn on the access transistor AT, is applied to the word line WL, and the bit line BL is pre-charged to zero volts (0V). Then, when the saturation voltage Vcc is applied to the plate line PL, the polarization direction is switched to 'P0'. Then, the total charge Q of the ferroelectric capacitor FC moves from point 'd' to point 'a'. In this case, the charge dQ1 corresponding to the difference between point 'd' and point 'a' can be released to the bit line BL through the access transistor AT.

[0078] With data '0' stored, the total charge of the ferroelectric capacitor FC is located at point 'b', and its polarization direction corresponds to 'P0'. At this time, the word line signal VWL, used to turn on the access transistor AT, is applied to the word line WL, and the bit line BL is pre-charged to 0V. Then, when the saturation voltage Vcc is applied to the plate line PL, the total charge Q of the ferroelectric capacitor FC moves from point 'b' to point 'a'. In this case, the polarization direction remains unchanged, and the charge dQ0 corresponding to the difference between points 'b' and 'a' can be released to the bit line BL through the access transistor AT.

[0079] Since the bit line BL has a capacitive component CBL, when a charge is released to the bit line BL, a bit line voltage VBL corresponding to the amount of charge released can be applied to the bit line BL. At this time, the level of the bit line voltage VBL can be proportional to the level of the charge released to the bit line BL. Therefore, the sense amplifier can determine the type of data stored in the ferroelectric capacitor FC by comparing the bit line voltage VBL with the reference voltage Vref.

[0080] Figure 9 This is a diagram illustrating a sensing method using a bit line voltage VBL generated based on the charge discharged from the ferroelectric capacitor FC to the bit line during a read operation. (Reference) Figure 9 During the read operation, the amount of charge discharged to bit line BL varies according to the data stored in the ferroelectric capacitor FC. The level of bit line voltage VBL is detected during the read operation based on the amount of discharged charge to identify the stored data.

[0081] When data '1' is stored in the ferroelectric capacitor FC, a relatively large amount of charge 'dQ1' will be discharged to bit line BL. Therefore, a bit line voltage VBL higher than the reference voltage Vref can be set to bit line BL. The sense amplifier can detect a bit line voltage VBL higher than the reference voltage Vref and identify it as data '1'. On the other hand, if data '0' is stored in the ferroelectric capacitor FC, a relatively small amount of charge 'dQ0' will be released to bit line BL. Therefore, a bit line voltage VBL lower than the reference voltage Vref can be set to bit line BL. The sense amplifier can detect a bit line voltage VBL lower than the reference voltage Vref and identify it as data '0'.

[0082] On the other hand, when data '1' is detected, the bit line voltage VBL corresponding to data '1' is set on bit line BL. Therefore, by reducing the voltage of plate line PL to 0V, data '1' can be reprogrammed to the ferroelectric capacitor FC. This operation can be called a write-back operation.

[0083] The above has explained the case of writing data to or reading data from a ferroelectric capacitor FC. However, it will be well understood that even in a ferroelectric memory cell with a '1TnC' structure, data write or read operations can be performed on each of multiple ferroelectric capacitors in the manner described above.

[0084] Figure 10 This is a waveform diagram briefly illustrating read and rewrite operations in a global board line structure according to some embodiments of this disclosure. (Refer to...) Figure 5 and Figure 10 As an example, the following will describe the situation in multiple global board lines GPL. <0> To GPL <j-1>Select Global Board Line GPL <0> And select the word line WL <0> The situation.

[0085] At time T0, the word line signal VWL is applied to the word line WL corresponding to the selected line. <0> A relatively high voltage (e.g., 3V) can be applied to the word line signal VWL. By providing the word line signal VWL, the gate is connected to the word line WL. <0> The access transistors AT0 to ATk-1 are turned on. Additionally, the gate of each layer is connected to the word line WL. <0> The board line selection transistor PLST will be turned on.

[0086] At time T1, the global board line signal VGPL is applied to the selected global board line GPL. <0> The global board line signal VGPL can be provided at, for example, the saturation voltage Vcc level. On the other hand, 0V will be provided to the unselected global board line GPL. <1> To GPL <j-1>By supplying the global board line signal VGPL to the selected global board line GPL. <0> A positive saturation voltage +Vcc is applied to the capacitor connected to the memory cell MC. <0> Global board line GPL <0> The two ends of the ferroelectric capacitor FC.

[0087] At time T2, the ferroelectric capacitor FC discharges a charge ('dQ1' or 'dQ0'), which is proportional to the difference between the saturation polarization at the positive saturation voltage +Vcc and the polarization at the previous state. In other words, charge sharing occurs.

[0088] At time T3, the read / write circuit 1230 amplifies the bit line voltage VBL set by the amount of discharged charge ('dQ1' or 'dQ0'). The read / write amplifier determines the data stored in the ferroelectric capacitor FC as '1' or '0' based on the level of the amplified bit line voltage VBL.

[0089] At time T4, when the supply reaches the selected global board line GPL <0> When the global board line signal VGPL is blocked, the rewriting of the ferroelectric capacitor FC begins. The negative saturation voltage -Vcc is applied again across the ferroelectric capacitor FC when data '1' is read, and thus, data '1' is written to the ferroelectric capacitor FC again. On the other hand, in the case where data '0' is read from the ferroelectric capacitor FC, since no data corruption occurs, the voltage across the ferroelectric capacitor FC remains at 0V.

[0090] At time T5, the bit line precharge period BL PRCH begins after the rewrite period. Then, at time T6, the read and rewrite sequence of the selected ferroelectric capacitor FC is terminated when the word line signal VWL is deactivated to low.

[0091] As mentioned above, the selection of a ferroelectric capacitor FC in a memory cell can be achieved through a combination of the word line WL and the global board line signal VGPL. Therefore, the number of contact plugs or pads per board line can be significantly reduced.

[0092] Figure 11 This is a diagram showing the arrangement of the plate line contact plug according to the first embodiment. (Refer to...) Figure 11 In the global board layout structure, global board layout GPL can be targeted. <0> To GPL <j-1>Each of these components forms a pad or board line contact plug CP0 to CPj-1 for chip-to-chip bonding. Additionally, a word line WL can be formed. <0> To WL <i-1>Each of the corresponding word line contact plugs is WLCP0 to WLCPi-1.

[0093] Board lines located on the same layer (e.g., PL<1, 0> to PL<1, i-1>) are connected to a global board line GPL via board line select transistors (PLST0 to PLSTi-1). <1> With word lines (e.g., WL) <0> The access transistors AT0 to ATk-1 corresponding to the selected row, as well as the board line selection transistor PLST0, are all activated. Therefore, in a cell array with a global board line structure, the memory cell or ferroelectric capacitor FC of the selected row can be selected by combining the word line signal VWL and the global board line signal VGPL.

[0094] Therefore, it can be achieved via global board line GPL <0> To GPL <j-1>To perform the application of the plate-line voltage VPL to the selected ferroelectric capacitor FC. That is, to apply the global plate-line voltage GPL. <0> To GPL <j-1>Use units rather than individual board lines (PL<0, 0> to PL)<j-1, i-1> This applies a board-line voltage VPL to each ferroelectric capacitor FC in the cell array 1210. Therefore, a global board-line voltage GPL can be applied. <0> To GPL <j-1>Contact plugs or pads are formed on a unit basis for transmitting the board line voltage VPL.

[0095] As shown, the global board line GPL <0> To GPL <j-1>It can be formed into a stepped shape where different layers do not overlap (e.g., GPL steps). A C2C structure can be formed by creating a board line contact plug for each step. In other words, a board line contact plug CP0 can be formed on the global board line GPL shared by board lines PL<0, 0> to PL<0, i-1>. <0> In the middle. A board line contact plug CP1 can be formed on the global board line GPL connected to board lines PL<1, 0> to PL<1, i-1>. <1> In the middle, without being related to the global board line GPL <0> The upper layer overlaps. A board line contact plug CP2 can be formed on the global board line GPL connected to board lines PL<2, 0> to PL<2, i-1>. <2> Above, without global board line GPL <1> The upper layer overlaps. In this way, board line contact plugs CP0 to CPj-1 can be formed to correspond to global board lines GPL respectively. <0> To GPL <j-1>.

[0096] Furthermore, one of the corresponding word line contact plugs WLCP0 to WLCPi-1 can be formed on the word line WL <0> To WL <i-1>superior.

[0097] Based on the configuration of board line contact plugs CP0 to CPj-1 in the global board line structure described above, the number of board line contact plugs used to drive the board line can be significantly reduced.

[0098] Figure 12 This is a diagram showing the arrangement of the plate line contact plug according to the second embodiment. (Refer to...) Figure 13 In the global board layout structure, global board layout GPL can be targeted. <0> To GPL <j-1>Each of these components forms a pad or board line contact plug CP0 to CPj-1 for chip-to-chip bonding. This can be used with word lines WL. <0> To WL <i-1>Each of the corresponding word line contact plugs is WLCP0 to WLCPi-1.

[0099] and Figure 11 The difference lies in Figure 12 In the D1 direction, word line contact plugs WLCP0 to WLCPi-1 can be formed on the same side where board line contact plugs CP0 to CPj-1 are formed. That is, word line contact plugs WLCP0 to WLCPi-1 can be formed to connect the word line and the pad in a layer lower than the layer in which board line contact plugs CP0 to CPj-1 are formed. Specifically, word line contact plugs WLCP0 to WLCPi-1 can extend from the upper side of the gate side of board line select transistors PLST0 to PLSTi-1 to the word line WL. <0> To the corresponding one in WL.

[0100] Based on the configuration of board line contact plugs CP0 to CPj-1 in the global board line structure described above, the number of board line contact plugs used to drive the board lines can be greatly reduced.

[0101] Figure 13 This is a diagram showing the arrangement of the plate line contact plug according to the third embodiment. (Refer to...) Figure 13 In the global board layout structure, global board layout GPL can be targeted. <0> Each of the components in the GPL is individually configured with pads or board line contacts CP0 to CPj-1 for chip-to-chip bonding. Additionally, word lines WL can be formed. <0> To each of the corresponding word line contact plugs WLCP0 to WLCPi-1 in WL. Specifically, board line contact plugs CP0 to CPj-1 are connected to the global board line GPL, which is formed in a stepped shape in the D2 direction. <0> To GPL. Therefore, it is not necessary to occupy too much chip area in the D1 direction to form board line contact plugs CP0 to CPj-1.

[0102] Global board line GPL <0> To GPL <j-1>It can be formed in a stepped shape (e.g., GPL stepped), which does not overlap with other layers in the diagonal direction of the 'D2×D3' plane as shown. Since a board line contact plug is formed for each step, pads or joints for C2C can be formed on the top of the board line contact plugs CP0 to CPj-1. Furthermore, word lines WL can be... <0> To WL <i-1>With the unit array 1210 as the center, word line contact plugs WLCP0 to WLCPi-1 are formed on the opposite sides of the board line contact plugs CP0 to CPj-1.

[0103] Based on the configuration of board line contact plugs CP0-CPj-1 in the global board line structure described above, the number of board line contact plugs used to drive the board lines can be greatly reduced.

[0104] Figure 14 This is a diagram showing the arrangement of the plate line contact plug according to the fourth embodiment. (Refer to...) Figure 14 In the global board layout structure, global board layout GPL can be targeted. <0> Each of the components in the GPL is individually configured to form pads or board line contacts CP0 to CPj-1 for chip-to-chip bonding. This can be used with word lines WL. <0> The corresponding word line contact plugs WLCP0 to WLCPi-1 in WL. Board line contact plugs CP0 to CPj-1 can be used in conjunction with the above. Figure 13 They are formed in essentially the same way.

[0105] Specifically, word line contact plugs WLCP0 to WLCPi-1 can be relative to word line WL <0> To WL L <i-1>The central unit array 1210 is formed on the same side as the board line contact plugs CP0 to CPj-1. That is, with Figure 13 The difference lies in Figure 14 In this configuration, word line contact plugs WLCP0 to WLCPi-1 can be formed on the same side as board line contact plugs CP0 to CPj-1 in the D1 direction. In other words, word line contact plugs WLCP0 to WLCPi-1 can be formed to connect the word line and the pad in a layer lower than the layer forming the board line contact plugs CP0 to CPj-1. Furthermore, word line contact plugs WLCP0 to WLCPi-1 can extend from the upper side of the gate side of the board line select transistors PLST0 to PLSTi-1 to the word line WL. <0> To WL <i-1>The corresponding one in the middle.

[0106] Figure 15 This is a circuit diagram illustrating an example of applying global board lines to a memory cell.

[0107] refer to Figure 15 The semiconductor device may include a first device portion 10 and a second device portion 100. The first device portion 10 may include an access transistor AT0, and the second device portion 100 may include a board line select transistor PLST0 and ferroelectric capacitors FC0, FC1, FC2 and FC3.

[0108] The gate of access transistor AT0 is connected to word line WL <0> One end of the access transistor AT0 is connected to the bit line BL. <0> Ferroelectric capacitors FC0, FC1, FC2 and FC3 can be formed between the other end of access transistor AT0 and one of the corresponding plate lines PL<0, 0>, PL<1, 0>, PL<2, 0> and PL<3, 0>.

[0109] Each of the board lines PL<0, 0>, PL<1, 0>, PL<2, 0>, and PL<3, 0> can be connected to the global board line GPL via the board line select transistor PLST0. <0> GPL <1> GPL <2> and GPL <3> One of the corresponding ones. For example, the board line PL<0, 0> formed on the first layer is connected to the global board line GPL via the board line select transistor PT0. <0> The board line PL<1, 0> formed on the second layer is connected to the global board line GPL via the board line select transistor PT1. <1> The board line PL<2, 0> formed on the third layer is connected to the global board line GPL via the board line select transistor PT2. <2> The board line PL<3, 0> formed on the fourth layer is connected to the global board line GPL via the board line select transistor PT3. <3> Global board line GPL <0> GPL <1> GPL <2> and GPL <3> Each of them is connected to all the board lines PL of the corresponding layer.

[0110] To select the ferroelectric capacitor FC3 for read or write operations, the word line signal VWL (see...) can be used. Figure 3 Apply to word line WL <0> And the bit line voltage VBL (see...) Figure 3 Apply position line BL <0> Access transistor AT0 is turned on by word line signal VWL. Board line select transistors PT0, PT1, PT2, and PT3 are also turned on simultaneously with access transistor AT0 via word line signal VWL. The global board line signal VGPL (see board line contact plug CP or pad) can be enabled via board line contact plug CP or pad. Figure 3 Provided to the global board line GPL <3> To activate board line PL<3, 0>.

[0111] Figure 16 It shows the relationship with Figure 15 The circuit diagram is a perspective view of a portion of the semiconductor device, and the second device portion 100 is shown. Figure 17A , Figure 17B and Figure 17C It is along Figure 16 The cross-sectional views taken by lines A1-A1', B1-B1', and C1-C1'. Figure 16 and Figures 17A to 17C The global board line GPL and board line PL are shown as... Figure 11 An example of the arrangement structure corresponding to the plate line contact plug CP. In the following figures, the numbers in the reference numerals (e.g., <0> , <1> (e.g., <1, 0>, etc.) are used to indicate the connection and / or positional relationship or order of specific components. Furthermore, figure marks without numbers may be used when referring to specific components regardless of their connection and / or positional relationship or order.

[0112] exist Figure 16 and Figures 17A to 17C In the example, four global board lines (GPLs) are shown, arranged on four layers, and three columns of board lines (PLs) corresponding to each GPL. For clarity, in... Figure 16 and Figures 17A to 17C In the diagram, the mutually perpendicular X, Y, and Z axes are shown as the first direction D1 to the third direction D3, respectively.

[0113] refer to Figure 15 , Figure 16 and Figures 17A to 17C A semiconductor device according to one or more embodiments may include a capacitor structure and a transistor structure.

[0114] In this embodiment, the transistor structure corresponds to the first device portion 10, and the capacitor structure corresponds to the second device portion 100. Therefore, for clarity, the reference numerals for the transistor structure and the capacitor structure will be the same as those for the first device portion 10 and the second device portion 100.

[0115] The first device portion 10 may include word lines WL, bit lines BL, and access transistors. Each access transistor may be connected to a corresponding word line WL and a corresponding bit line BL. A detailed description of the transistor structure 10 will be provided later.

[0116] The capacitor structure 100 may be disposed on the transistor structure 10. For example, at least a portion of the capacitor structure 100 may overlap perpendicularly with the transistor structure 10. However, the arrangement relationship between the transistor structure 10 and the capacitor structure 100 is not limited to this and may be different.

[0117] The capacitor structure 100 may include a capacitor region CPT and a stepped region SPT connected to the capacitor region CPT. The capacitor region CPT may be connected to the transistor structure 10 and may be a region that stores charge by forming a ferroelectric capacitor.

[0118] The capacitor region (CPT) can include ferroelectric capacitors and plate-line select transistors (PTs).

[0119] Ferroelectric capacitors can be stacked on a third-direction D3.

[0120] A ferroelectric capacitor may include a plate line PL (e.g., a portion of the plate line PL), a capacitor electrode 133, and a ferroelectric layer 131 disposed between the plate line PL and the capacitor electrode 133.

[0121] In the capacitor region CPT, plate lines PL can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. Furthermore, plate lines PL can be stacked in a multi-layer structure in a third direction D3. The plate lines PL can be arranged in a matrix in the second direction D2 and the third direction D3. The second direction D2 can be a column direction, and the third direction D3 can be a row direction. The accompanying drawings show plate lines PL arranged in a 4x3 matrix. For clarity, some plate lines PL are indicated by both row and column numbers or only by row numbers. For example, "PL<0, 1>" refers to a plate line in the second column of the first row, and "PL1" refers to a plate line in the second row.

[0122] In the top view, the plate line PL may include a first side extending along a first direction D1 and a second side extending along a second direction D2. The length of the first side may be greater than the length of the second side.

[0123] The plate line PL can include various conductive materials, such as doped semiconductor materials, conductive metals, conductive metal nitrides, or metal oxides. For example, the plate line PL can include doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), and / or conductive metal oxides (e.g., iridium oxide or niobium oxide), but the implementation is not limited thereto. In some implementations, the plate line PL can be formed of polysilicon and / or copper.

[0124] Multiple first trenches TCH1 can be disposed in capacitor structure 100. The first trenches TCH1 can penetrate the plate lines PL forming a single column. Multiple first trenches TCH1 can be disposed within the plate lines PL forming a single column. For example, four first trenches TCH1 can be disposed within the plate lines PL forming a single column, as shown in the figure.

[0125] The first insulating layer 110 can be disposed between the transistor structure 10 and the bottommost board line PL, as well as between two adjacent rows of board lines PL. The first insulating layer 110 may not be disposed between two adjacent columns of board lines PL.

[0126] The first insulating layer 110 and the board line PL can be arranged alternately on the third direction D3.

[0127] Each of the first insulating layers 110 may include, but is not limited to, an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first insulating layer 110 may include silicon oxide.

[0128] Ferroelectric layer 131 may be disposed on the inner surface of the first trench TCH1. Ferroelectric layer 131 may cover the side surface of the first trench TCH1. Ferroelectric layer 131 may be conformally disposed on the sidewalls of the plurality of first trench TCH1s. Ferroelectric layer 131 may not be disposed on the bottom surface of the plurality of first trench TCH1s. Ferroelectric layer 131 may alternately contact the board line PL and the first insulating layer 110 in the extension direction of the first trench TCH1. For example, a portion of ferroelectric layer 131 may contact the board line PL, and another portion of ferroelectric layer 131 may contact the first insulating layer 110.

[0129] In some embodiments, the ferroelectric layer 131 may include a ferroelectric layer, a ferroelectric layer, an antiferroelectric layer, and / or a combination thereof. For example, when the ferroelectric capacitor has non-volatile memory characteristics, the ferroelectric layer 131 may include one of the following: a ferroelectric layer, a combination of a ferroelectric layer and an antiferroelectric layer, and a combination of ferroelectric layers. For example, when the ferroelectric capacitor has volatile memory characteristics, the ferroelectric layer 131 may include one of the following: a ferroelectric layer, a combination of a ferroelectric layer and an antiferroelectric layer, and a combination of ferroelectric layers. However, this disclosure is not limited thereto.

[0130] In some embodiments, the ferroelectric material may include one of lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or lanthanum bismuth titanate (BLT). Furthermore, the ferroelectric capacitor may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide, or it may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O). Each ferroelectric material may further include a dopant element doped into the aforementioned material. The dopant element may be an element selected from the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn).

[0131] In some embodiments, the ferroelectric layer may include, for example, perovskite-based materials and / or fluorite-based materials.

[0132] The ferroelectric layer can include materials with high dielectric constants, such as beryllium oxide (BeO2), magnesium oxide (MaO2), calcium oxide (CaO2), strontium oxide (SrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), scandium oxide (Sc2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), vanadium oxide (V2O5), strontium titanium oxide (SrTiO3), or barium strontium titanium oxide (BaSrTiO3). 。 However, this disclosure is not limited thereto.

[0133] The capacitor electrode 133 can fill the remaining portion within the first trench TCH1 where the ferroelectric layer 131 is disposed. The capacitor electrode 133 can extend in a third direction D3 forming the first trench TCH1. At least one capacitor electrode 133 can be provided for each board line PL. In this embodiment, a capacitor electrode 133 is provided for each first trench TCH1 of each board line PL, and the capacitor electrode 133 is illustrated to include four capacitor electrodes. However, the number of capacitor electrodes 133 is not limited to this and can be different.

[0134] Each of the capacitor electrodes 133 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and / or a conductive metal oxide (e.g., iridium oxide or niobium oxide), but the implementation is not limited thereto.

[0135] In the capacitor electrode 133, the plate line PL and the ferroelectric layer 131, a single capacitor electrode 133 and a single plate line PL disposed on opposite sides and a single ferroelectric layer 131 between them can form a single ferroelectric capacitor.

[0136] The board line selection transistor PT can be placed on one side of the ferroelectric capacitor.

[0137] The board line select transistor PT may include a board line PL (e.g., a portion of a board line PL), a global board line GPL (e.g., a portion of a global board line GPL), a select semiconductor pattern 141, a select gate insulating layer 143, and a select gate electrode 145.

[0138] Multiple second trenches TCH2 can be provided in the capacitor structure 100. The second trenches TCH2 can penetrate the single-row board line PL and the global board line GPL located in the same layer as the single-row board line PL. A single second trench TCH2 can be provided for the single-row board line PL.

[0139] Global board lines (GPLs) can be spaced apart from board lines (PLs), and a second trench (TCH2) is located between the global board line (GPL) and the board line (PL). Global board lines (GPLs) can be stacked along a third direction (D3). The number of global board lines (GPLs) can be the same as the number of rows of board lines (PLs) to correspond to the rows of board lines (PLs). In some embodiments, each of the global board lines (GPLs) can be located on the same layer as the board line (PL) in the same row. Global board lines (GPLs) located on a single layer can be connected to each other. For example, a single global board line (GPL) can be located on a single layer.

[0140] Global board line (GPL) can include materials that are substantially the same as board line (PL).

[0141] The select gate electrode 145 may be disposed within the second trench TCH2. The select gate electrode 145 may extend in the third direction D3 within the second trench TCH2. In some embodiments, each of the select gate electrodes 145 may be connected to a corresponding one of the word lines WL of the transistor structure 10.

[0142] Each selected gate electrode 145 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and / or a conductive metal oxide (e.g., iridium oxide or niobium oxide), but the implementation is not limited thereto.

[0143] Select semiconductor patterns 141 may surround the outer surface of each select gate electrode 145. The number of select semiconductor patterns 141 may be the same as the number of rows of board lines PL, corresponding to the rows of board lines PL. Select semiconductor patterns 141 may be disposed on the same plane as each board line PL. In some embodiments, each select semiconductor pattern 141 may be disposed in the same layer as the board line PL in the same row.

[0144] In the top view, each select semiconductor pattern 141 can be arranged in a ring and can be disposed between the corresponding select gate electrode 145 and the board line PL adjacent to the select gate electrode 145. The select semiconductor pattern 141 can also be disposed between the corresponding select gate electrode 145 and the global board line GPL adjacent to the select gate electrode 145. One side of the select semiconductor pattern 141 can be connected to the board line PL adjacent to the select gate electrode 145, and the other side of the select semiconductor pattern 141 can be connected to the global board line GPL adjacent to the select gate electrode 145. The board lines PL and GPL, which are opposite each other and interspersed with individual select semiconductor patterns 141, can be spaced apart from each other. A select gate insulating layer 143 can be disposed between the select gate electrode 145 and the select semiconductor pattern 141. The select gate insulating layer 143 can conformally cover the select gate electrode 145.

[0145] Global board lines GPL and PL, which are opposite to each other and interspersed with individual select semiconductor patterns 141, can be used as source and drain electrodes, respectively. A single gate electrode, a select semiconductor pattern 141 surrounding the single gate electrode, and global board lines GPL and PL, which are positioned opposite to each other and interspersed with select semiconductor patterns 141, can form a single board line select transistor PT.

[0146] The capacitor structure 100 may include an upper insulating layer 150. The upper insulating layer 150 may cover the first insulating layer 110, board line PL, global board line GPL, capacitor electrode 133, select gate electrode 145, etc. The upper insulating layer 150 may include an oxide-based insulating material. The upper insulating layer 150 may include at least one of, for example, silicon oxide, silicon oxynitride, and low-k materials with a dielectric constant lower than silicon oxide, but the implementation is not limited thereto.

[0147] In capacitor structure 100, the stepped region SPT may include a portion of the global board line GPL, a portion of the first insulating layer 110, and board line contact plugs CP.

[0148] The stepped region SPT can be set on one side of the capacitor region CPT. The stepped region SPT and the capacitor region CPT can be arranged sequentially along the second direction D2.

[0149] The global board line (GPL) can extend from the capacitor region (CPT) to the stepped region (SPT). In a top view, the global board line (GPL) in the stepped region (SPT) can extend in a predetermined direction. For example, in the stepped region (SPT), the global board line (GPL) can extend along a second direction (D2). In a top view, the extension direction of the global board line (GPL) can be perpendicular to the extension direction of each board line (PL). Therefore, when viewed from the first direction (D1) to the third direction (D3), the global board line (GPL) may not overlap with the board lines (PL).

[0150] Global board lines (GPLs) in the stepped region SPT can have different lengths in the second direction D2. The length of the global board line GPL in the second direction D2 can decrease from the bottom layer to the top layer. For example, if the global board lines PL arranged from bottom to top are called the first to fourth global board lines GPLs... <0> GPL <1> GPL <2> and GPL <3> Then the first to fourth global board lines GPL <0> GPL <1> GPL <2> and GPL <3> The length in the second direction D2 can decrease sequentially. However, the direction of the steps in the stepped region SPT is not limited to this. For example, the length of the global board line GPL in the second direction D2 can decrease from the top layer to the bottom layer. (First to fourth global board lines GPL) <0> GPL <1> GPL <2> and GPL <3> They can have progressively longer lengths. As mentioned above, the global plate lines (GPLs) in the stepped region SPT can be stacked in a stepped shape.

[0151] Located in the first device section 10 and the first global board line GPL <0> Between the second to fourth adjacent global board lines GPL <1> GPL <2> and GPL <3> The length of the first insulating layer 110 in the second direction D2 can also be shorter from the bottom layer to the top layer. In the stepped region SPT, the end face of each global board line GPL and the end face of the corresponding first insulating layer 110 can be substantially coplanar.

[0152] A portion of the upper surface of each of the Global Board Lines (GPL) may not be covered by the first insulating layer 110 directly disposed above it.

[0153] The upper insulating layer 150 can be set on the global board line GPL of the stepped area SPT.

[0154] A trench may be provided in the upper insulating layer 150 to expose the portion of the upper surface of the global board line GPL not covered by the first insulating layer 110. The trench may be configured to correspond to each of the global board lines GPL. Board line contact plugs CP may be provided within the trench. For example, connected to the first through fourth global board lines GPL. <0> GPL <1> GPL <2> and GPL <3> The first to fourth board line contact plugs CP0, CP1, CP2, and CP3 (hereinafter referred to as "CP") can be respectively disposed in each trench. The board line contact plugs CP can be arranged sequentially along the extension direction of the global board line GPL (e.g., the second direction D2). In some embodiments, the first to fourth board line contact plugs CP0, CP1, CP2, and CP3 can be provided with different lengths and can all have an upper surface disposed on the same plane. However, this disclosure is not limited thereto. In some embodiments, when the length of the global board line GPL increases in the direction from the uppermost layer to the lowermost layer, the trench can be configured to expose a portion of the lower surface of the global board line GPL, and the board line contact plugs CP can be disposed in the trench.

[0155] The board line contact plug CP may include a conductive material. For example, the board line contact plug CP may include tungsten (W) or copper (Cu), but the implementation is not limited to this.

[0156] The board line contact plug (CP) can apply voltage to each of the corresponding global board lines (GPL).

[0157] In some embodiments, in addition to the transistor structure 10, the semiconductor device may also include a peripheral circuit structure. The peripheral circuit structure may include a peripheral circuit substrate and peripheral circuit elements.

[0158] The peripheral circuit structure may be disposed below the transistor structure 10, but is not limited thereto, and may also be disposed on the capacitor structure 100. At least a portion of the peripheral circuit structure may vertically overlap with the capacitor structure 100 and / or the transistor structure 10. The peripheral circuit structure may also be disposed on an additional substrate for electrical connection to the transistor structure 10 and / or the capacitor structure 100.

[0159] The peripheral circuit substrate may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Optionally, the peripheral circuit substrate may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0160] Peripheral circuit elements can be formed on a peripheral circuit substrate. These peripheral circuit elements can constitute the peripheral circuitry controlling the operation of each memory cell of the semiconductor device. For example, peripheral circuit elements may include control logic, row decoders, page buffers, etc. Peripheral circuit elements may include, for example, transistors, but the implementation is not limited thereto. For example, peripheral circuit elements may include various passive elements such as capacitors, resistors, and inductors, as well as various active elements such as transistors.

[0161] Figures 18A to 18N The manufacturing process is shown sequentially. Figure 16 The cross-sectional view of the method for the semiconductor device shown is corresponding to... Figure 17A Cross-sectional view.

[0162] refer to Figure 18A The first insulating layer 110 and the sacrificial layer 120i can be stacked alternately on the transistor structure 10.

[0163] In this embodiment, substrate 11 is shown as a base material, with a first insulating layer 110 and a sacrificial layer 120i stacked on the base material; however, the embodiment is not limited to this. For example, substrate 11 can be replaced with other materials, as long as they are used to fabricate semiconductor devices. In this case, substrate 11 can be, for example, a wafer. The wafer can include, for example, silicon (Si). The wafer can include semiconductor elements such as germanium (Ge) or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). According to some embodiments, the wafer can have a silicon-on-insulator (SOI) structure. In some embodiments, substrate 11 can include a substrate on which a series of processes for fabricating semiconductor devices are performed or will be performed. For example, these processes can include: ion doping processes, oxidation processes to form oxide layers, photolithography processes including spin coating, exposure, and development, thin film deposition processes including chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), dry etching processes, wet etching processes, or metal wiring processes.

[0164] The first insulating layer 110 and the sacrificial layer 120i may have etch selectivity. For example, the first insulating layer 110 may comprise an oxide-based insulating material, and the sacrificial layer 120i may comprise a nitride-based insulating material. In some embodiments, the sacrificial layer 120i may comprise doped polysilicon. However, this disclosure is not limited thereto, and the sacrificial layer 120i may comprise other materials.

[0165] refer to Figure 18B A portion of the first insulating layer 110 and the sacrificial layer 120i can be removed to form a plurality of first trenches TCH1. The plurality of first trenches TCH1 can penetrate the first insulating layer 110 and the sacrificial layer 120i. In a top view, each first trench TCH1 can have various shapes. For example, each first trench TCH1 can be circular, elliptical, or rectangular, and can have other shapes.

[0166] In some embodiments, the side surfaces of the first insulating layer 110 and the sacrificial layer 120i forming the first trench TCH1 may be coplanar. However, the embodiments are not limited to this, and one side surface of either the first insulating layer 110 or the sacrificial layer 120i may be partially recessed in the horizontal direction.

[0167] refer to Figure 18C The ferroelectric layer 131 can be formed along the side surface of the first trench TCH1. The ferroelectric layer 131 can be formed along the side surface of the first insulating layer 110 and the side surface of the sacrificial layer 120i. The ferroelectric layer 131 can conformally cover the sidewall of each first trench TCH1, but the implementation is not limited thereto.

[0168] The ferroelectric layer 131 may not be formed on the bottom surface of the first trench TCH1, but the implementation is not limited thereto. In other embodiments, the ferroelectric layer 131 may also be formed on the bottom surface of the first trench TCH1. When the ferroelectric layer 131 is also formed on the bottom surface of the first trench TCH1, an additional process may then be performed to remove the ferroelectric layer 131 formed on the bottom surface.

[0169] Each ferroelectric layer 131 can be formed by a suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam deposition (MBD), or physical vapor deposition (PVD) using a ferroelectric material as the material. The ferroelectric material may include one of lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth lanthanum titanate (BLT). The ferroelectric capacitor (FCk) may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide, or it may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O). Each of the ferroelectric capacitors may also include a dopant element doped into the aforementioned materials. The doping element can be selected from the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn).

[0170] refer to Figure 18D A capacitor electrode 133 can be formed within the first trench TCH1 in which the ferroelectric layer 131 is formed. The capacitor electrode 133 can fill the first trench TCH1 surrounded by the ferroelectric layer 131.

[0171] refer to Figure 18E A portion of the first insulating layer 110 and the sacrificial layer 120i can be removed to form the second trench TCH2. The second trench TCH2 can penetrate the second insulating layer 30 and the sacrificial layer 120i. In some embodiments, the second trench TCH2 can be formed deeper than the first trench TCH1. Forming a second trench TCH2 deeper than the first trench TCH1 enables the formation of a select gate electrode 145 connected to the word line WL in the second trench TCH2 during subsequent operations of forming the first device portion 10. This will be described later.

[0172] In the top view, each second groove TCH2 can have various shapes. For example, each second groove TCH2 can be circular, elliptical, or rectangular, and can have other shapes.

[0173] refer to Figure 18F A portion of the sacrificial layer 120i can be removed to form the first recess R1. The first recess R1 can be formed by isotropically etching the portion of the sacrificial layer 120i exposed to the outside by the second trench TCH2. A portion of the sacrificial layer 120i can be removed by a wet etching process. The sacrificial layer 120i and the first insulating layer 110 have etch selectivity, so the first recess R1 can be formed by selectively removing a portion of the sacrificial layer 120i. The first insulating layer 110 may not be removed during the removal of a portion of the sacrificial layer 120i.

[0174] refer to Figure 18G A selective semiconductor pattern 141 can be formed within the first recess R1. The side surface of the selective semiconductor pattern 141 is shown as being disposed on the same plane as the side surface of the first insulating layer 110, but this disclosure is not limited thereto.

[0175] refer to Figure 18H A select gate insulating layer 143 can be formed within the second trench TCH2 that forms the select semiconductor pattern 141. The select gate insulating layer 143 can conformally cover the first insulating layer 110 and the side surface of the select semiconductor pattern 141.

[0176] refer to Figure 18I A select gate electrode 145 can be formed within the second trench TCH2 that forms the select gate insulating layer 143. The select gate electrode 145 can fill the remaining portion within the second trench TCH2.

[0177] refer to Figure 18J The sacrificial layer 120i can be selectively removed to form the second recess R2. The second recess R2 can be formed by selectively etching the sacrificial layer 120i only, while selectively leaving the first insulating layer 110 between the first insulating layer 110 and the sacrificial layer 120i using etching.

[0178] In some embodiments, at least one etch trench penetrating the first insulating layer 110 and the sacrificial layer 120i may be additionally formed to efficiently etch the sacrificial layer 120i. The sacrificial layer 120i may be removed between the etch trenches.

[0179] refer to Figure 18K Board lines PL and global board lines GPL can be formed within the second recess R2. For example, first to fourth board lines PL1, PL2, PL3, and PL4, as well as first to fourth global board lines GPL, can be formed within the second recess R2. <0> GPL <1> GPL <2> and GPL <3> The first to fourth board lines PL1, PL2, PL3, and PL4, as well as the first to fourth global board lines GPL, can be formed by filling the second recess R2. <0> GPL <1> GPL <2> and GPL <3> .

[0180] Therefore, a ferroelectric capacitor consisting of a plate line PL, a ferroelectric layer 131, and a capacitor electrode 133 can be formed. Furthermore, a plate line selection transistor PT including a plate line PL, a global plate line GPL, a selection semiconductor pattern 141, and a selection gate electrode 145 can be formed.

[0181] refer to Figure 18L This allows for the removal of the first insulation layer 110 and a portion of the global board line (GPL). Within the stepped region SPT, the first insulation layer 110 and the global board line (GPL) can be removed to varying degrees. For example, the second global board line (GPL) can be removed. <1> A portion of the first insulating layer 110 below, such that the length in the second direction D2 is greater than the first global board line GPL. <0> It is shorter than the first insulating layer 110 below. Similarly, the third global board line GPL can be removed. <2> A portion of the first insulating layer 110 below, such that the length in the second direction D2 is greater than the second global board line GPL. <1> It is shorter than the first insulating layer 110 below. A stepped shape can be formed by sequentially removing a portion of the global board line GPL and the first insulating layer 110 in the same manner.

[0182] In some implementations, a portion of the first insulating layer 110 and the plate line PL can be removed in the capacitor region CPT to form multiple rows of plate lines PL.

[0183] refer to Figure 18M An upper insulating layer 150 can be formed on the board line select transistors and ferroelectric capacitors, including the board line PL and the global board line GPL. The upper insulating layer 150 can cover all the upper surfaces of the global board line GPL arranged in a stepped shape.

[0184] refer to Figure 18N Board line contact plugs (CPs) can be formed within the upper insulating layer 150. The board line contact plugs (CPs) can be formed by the following process: removing a portion of the upper insulating layer 150 to form contact holes that expose a portion of the top surface of the global board line (GPL) arranged in a stepped shape, and then filling the contact holes.

[0185] The capacitor structure 100 can be manufactured using the above process.

[0186] In some embodiments, the capacitor structure 100 can be modified in various ways without departing from this disclosure. For example, in the stepped region SPT, the global board line GPL can extend in various directions. Board line contact plugs CP can be arranged to correspond to the global board line GPL in the direction of its extension.

[0187] Figure 19 and 20 This is a perspective view showing a semiconductor device according to some embodiments.

[0188] Reference Figure 19 The stepped area (SPT) and capacitor area (CPT) can be arranged sequentially along the second direction D2. The global plate line (GPL) can extend from the capacitor area (CPT) to the stepped area (SPT).

[0189] In the above embodiment, the global board line GPL extends along the second direction D2. However, in this embodiment, the global board line GPL can extend in a different direction. For example, in this embodiment, the global board line GPL can extend in the first direction D1. Therefore, each global board line GPL can be parallel to the extension direction of each board line PL. The global board line GPL can be spaced apart from adjacent board lines PL, and the upper insulating layer 150 is located between the global board line GPL and the adjacent board line PL.

[0190] Global board lines (GPLs) in the stepped region SPT can have different lengths in the first direction D1. Global board lines (GPLs) can have shorter lengths in the direction from the bottom layer to the top layer. For example, the first to fourth global board lines (GPLs) can have progressively shorter lengths.

[0191] Reference Figure 20 The stepped region SPT and the capacitor region CPT can be arranged sequentially along the first direction D1. Therefore, when viewed from the first direction D1, the stepped region SPT and the capacitor region CPT can overlap each other.

[0192] The global board line GPL can extend from the capacitor region CPT to the stepped region SPT, and can extend in the second direction D2. Therefore, each of the global board lines GPL can be perpendicular to the extension direction of each board line PL. The global board line GPL can be spaced apart from adjacent board lines PL, and the upper insulating layer 150 is located between the global board line GPL and the adjacent board line PL.

[0193] Global board lines (GPLs) in the stepped region SPT can have different lengths in the second direction D2. Global board lines (GPLs) can have shorter lengths in the direction from the bottom layer to the top layer. For example, the first to fourth global board lines (GPLs) can have progressively shorter lengths.

[0194] Figure 21 It is shown that... Figure 15 The circuit diagram corresponds to a perspective view of the semiconductor device, and shows the case where the semiconductor device includes both capacitor structure 100 and transistor structure 10. Figure 22A , Figure 22B and Figure 22C It is along Figure 21 The cross-sectional view taken by lines A2-A2', B1-B1' and C1-C1'.

[0195] refer to Figure 15 , Figure 21 and Figures 22A to 22C A capacitor structure 100 may be disposed on a transistor structure 10. The transistor structure 10 may correspond to a first device portion 10 and may include a first gate electrode 25 corresponding to a word line WL, a bit line BL, a semiconductor pattern 21, a second gate electrode 27, and a gate insulating layer 23. The semiconductor pattern 21, the first gate electrode 25, the second gate electrode 27, and the gate insulating layer 23 may form an access transistor.

[0196] The access transistor can be a vertical channel transistor. A vertical channel transistor can have a structure in which the channel region 21c extends in the vertical direction (i.e., the third direction D3). However, the type of access transistor is not limited to this, and access transistors can be arranged in various forms. For example, access transistors can include at least one of buried channel array transistors (BCAT), planar transistors, fin transistors (Fin FETs), and / or multi-bridge channel transistors (MBCFETs).

[0197] Semiconductor pattern 21 may be a vertical semiconductor pattern extending in the third direction D3. In some embodiments, each semiconductor pattern 21 has a rectangular shape in a top view, but the embodiments are not limited thereto. For example, in a top view, each semiconductor pattern 21 may have a rounded rectangular shape.

[0198] Each semiconductor pattern 21 may include a first source / drain region 21a, a second source / drain region 21b, and a channel region 21c. The first source / drain region 21a may be disposed at the upper end of each semiconductor pattern 21, and the second source / drain region 21b may be disposed at the lower end of each semiconductor pattern 21. In some embodiments, the first source / drain region 21a may be connected to the capacitor electrode 133 of the capacitor structure 100, and the second source / drain region 21b may be connected to the bit line BL. In some embodiments, additional contact patterns may also be disposed between the first source / drain region 21a and the capacitor electrode 133, and / or between the second source / drain region 21b and the bit line.

[0199] The first source / drain region 21a and the second source / drain region 21b can each serve as a source or drain to supply or release current-carrying carriers. Here, the carriers can be electrons or holes. The channel region 21c can serve as a path through which carriers move. For example, the first source / drain region 21a can serve as a source, the second source / drain region 21b can serve as a drain, and the channel region 21c can serve as a path for carriers to move between the source and the drain. The first source / drain region 21a and the second source / drain region 21b can be regions doped with impurities of a different conductivity type than that of the channel region 21c. For example, when the channel region 21c includes impurities of a first conductivity type, the first source / drain region 21a and the second source / drain region 21b can be regions doped with impurities of a second conductivity type opposite to the first conductivity type. For example, impurities of the first conductivity type can be p-type impurities, such as boron (B) or group 3 elements, and impurities of the second conductivity type can include n-type impurities, such as phosphorus (P) and / or arsenic (As) or group 5 elements.

[0200] Semiconductor pattern 21 may include semiconductor materials such as silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). Vertical semiconductor pattern 21 may include oxide semiconductor materials. The oxide semiconductor material may be, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x ZnySn z O、Yb x Ga y Zn z O、In x Ga y At least one of O and indium gallium zinc oxide (IGZO). The vertical semiconductor pattern 21 may comprise a single layer or multiple layers of oxide semiconductor material. The vertical semiconductor pattern 21 may comprise amorphous, crystalline, or polycrystalline oxide semiconductor material, but the embodiments are not limited thereto. In some embodiments, the vertical semiconductor pattern 21 may comprise a single-crystal semiconductor material. Therefore, the semiconductor pattern 21 may be in a single-crystal state. In some embodiments, the vertical semiconductor pattern 21 may have a bandgap energy greater than that of silicon. In some embodiments, the vertical semiconductor pattern 21 may comprise a two-dimensional semiconductor material. The two-dimensional semiconductor material may comprise, for example, graphene, MoS2, WS2, MoSe2, WSe2, or combinations thereof.

[0201] The gate electrode can be disposed on opposite sidewalls of the channel region 21c. The gate electrode may include a first gate electrode 25 disposed on one side of the channel region 21c and a second gate electrode 27 disposed on the other side of the channel region 22c. The first gate electrode 25 and the second gate electrode 27 may extend in a first direction D1.

[0202] The first gate electrode 25 can be used as a word line and can be referred to as a word line.

[0203] The first gate electrode 25 can be connected to a corresponding board line select transistor PT. For example, the gate electrode can contact the select gate electrode 145 of the corresponding board line select transistor PT. The select gate electrode 145 can extend in the third direction D3 to be disposed inside the transistor structure 10, and can contact one of the first gate electrodes 25 extending in the first direction D1 in the intersecting region.

[0204] The second gate electrode 27 can be a back gate electrode. The second gate electrode 27 can have a shorter length than the first gate electrode 25 and may not contact the select gate electrode 145. In some embodiments, a negative voltage can be applied to the back gate electrode during operation of the semiconductor device, which can increase the threshold voltage of the vertical-channel transistor. Therefore, by controlling the threshold voltage, the back gate electrode can prevent the degradation of leakage current characteristics caused by the decrease in threshold voltage as the vertical-channel transistor is miniaturized.

[0205] A gate insulating layer 23 may be disposed between the first gate electrode 25 and the channel region 21c, and between the second gate electrode 27 and the channel region 22c, to surround the channel region 21c. In some embodiments, the gate insulating layer 23 may surround the entire sidewall of the channel region 21c, or may cover a portion of the sidewalls of the first and second gate electrodes 25 and 27. In some embodiments, the gate insulating layer 23 may extend in the extension direction of the first gate electrode 25 and the second gate electrode 27 (e.g., in the third direction D3), and may only cover the two sidewalls of the channel region 21c opposite to the first gate electrode 25 and the second gate electrode 27.

[0206] The gate insulating layer 23 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0207] The first gate electrode 25 and the second gate electrode 27 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, doped polysilicon, or a combination thereof.

[0208] Bit lines BL can be connected to each of the second source / drain regions 21b. Bit lines BL extend in the second direction D2 and can be spaced apart from each other at a predetermined interval in the first direction D1.

[0209] Bit lines BL can include conductive materials. For example, bit lines BL can include metallic materials (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), conductive metal silicides, conductive metal oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), or LSCo), or doped polycrystalline silicon, etc.

[0210] In some embodiments, the bit line BL is shown as formed as a single layer. However, embodiments are not limited thereto, and the bit line BL may also include sequentially stacked semiconductor layers, barrier patterns, and low-resistance patterns. In some embodiments, the semiconductor layers may include a polycrystalline semiconductor material, such as polycrystalline silicon, and the low-resistance pattern may include a conductive metal nitride, a metal silicide, or a metal. For example, the low-resistance pattern may include tungsten.

[0211] In some embodiments, the second insulating layer 30 and the third insulating layer 50 may be disposed between the bit line BL and the lower surface of the capacitor structure 100.

[0212] The second insulating layer 30 may be disposed between the upper insulating layer 150 and the upper surfaces of the first gate electrode 25 and the second gate electrode 27. The third insulating layer 50 may be disposed between the second insulating layer 30 and the bit line BL. The third insulating layer 50 may be disposed between the vertical semiconductor patterns 21. The third insulating layer 50 can electrically isolate the vertical semiconductor patterns 21 from each other. In some embodiments, the lower surface of the third insulating layer 50 may be substantially coplanar with the bottom surface of the semiconductor pattern 21. The upper surface of the third insulating layer 50 may be substantially coplanar with the upper surfaces of the first gate electrode 25 and the second gate electrode 27. In some embodiments, the second insulating layer 30 and / or the third insulating layer 50 may comprise a material different from the material of the selected gate insulating layer 143.

[0213] In some embodiments, the first to third insulating layers 110, 30, and 50 and the upper insulating layer 150 are shown as a single layer. However, the embodiments are not limited thereto, and the first to third insulating layers 110, 30, and 50 and the upper insulating layer 150 may each have a multilayer structure.

[0214] Semiconductor devices according to some embodiments may have the above-described structure, such that board lines PL disposed in the same layer (e.g., at the same height) can be connected to a global board line GPL via a single board line select transistor PT. Word lines WL can be connected to both the access transistor and the board line select transistor PT, and a memory cell or ferroelectric capacitor in a selected row can be selected by a combination of the word line WL signal and the global board line GPL signal.

[0215] Figures 23A to 23H , Figures 24A to 24H and Figures 25A to 25H The manufacturing process is shown sequentially. Figure 21 and Figures 22A to 22C A cross-sectional view of the method for the semiconductor device shown. Figures 23A to 23H It is along Figure 21 A cross-sectional view taken from line A2-A2'. Figures 24A to 24H It is along Figure 21 The cross-sectional view taken by line B1-B1', and Figures 25A to 25H It is along Figure 21 The cross-sectional view taken from line C1-C1'.

[0216] refer to Figure 23A , Figure 24A and Figure 25A A capacitor structure 100 can be formed on the substrate 11.

[0217] Substrate 11 may be, for example, a wafer. The wafer may include, for example, silicon (Si). The wafer may include semiconductor elements such as germanium (Ge) or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). According to some embodiments, the wafer may have a silicon-on-insulator (SOI) structure. In some embodiments, substrate 11 may include sub-states of a series of processes performed or to be performed for manufacturing semiconductor devices. In some embodiments, substrate 11 may include silicon.

[0218] When the capacitor structure 100 is formed, the select gate electrode 145 can be formed to extend into the substrate 11. Figure 18E When the second trench TCH2 is formed, the second trench TCH2 can be formed to extend downward from the upper surface of the substrate 11 into the substrate 11 to form the select gate electrode 145. Then, the following can be performed: Figures 18F to 18N The process shown is used to form a capacitor structure 100 including a select gate electrode 145 extending into the substrate 11.

[0219] refer to Figure 23B , Figure 24B and Figure 25B The substrate 11 on which the capacitor structure 100 is formed can be flipped, and then a process for forming a transistor structure can be performed on the flipped substrate 11.

[0220] refer to Figure 23C , Figure 24C and Figure 25C Active pillars can be formed by patterning the substrate 11. For the semiconductor pattern 21 of the access transistor (see...), Figure 21 Active pillars are provided. In the following text, for clarity, the active pillars used as semiconductor pattern 21 will be referred to as semiconductor pattern 21.

[0221] As shown in the figure, the semiconductor pattern 21 and the select gate electrode 145 can be formed at different heights. The height of the semiconductor pattern 21 can be formed to be greater than the height of the select gate electrode 145.

[0222] During the operation of the patterned substrate 11, the select gate insulating layer 143 surrounding the select gate electrode 145 can be removed.

[0223] refer to Figure 23D , Figure 24D and Figure 25D A second insulating layer 30 may be formed on the upper surface of the capacitor structure 100. The second insulating layer 30 may be formed on the upper surface of the capacitor structure 100, for example, on the first insulating layer 110. The second insulating layer 30 may cover a portion of the side of the semiconductor pattern 21 and a portion of the side of the capacitor electrode 133.

[0224] A protective layer 40 may be formed on the second insulating layer 30 to cover the select gate electrode 145. The second insulating layer 30 may be formed only in the region where the select gate electrode 145 is arranged, and may not be formed in the region where the semiconductor pattern 21 is arranged.

[0225] The gate insulating layer 23 may be formed on the exposed side surface of the semiconductor pattern 21. The gate insulating layer 23 may not be formed on the upper surface of the semiconductor pattern 21. However, in some embodiments, the gate insulating layer 23 may remain on the upper surface of the semiconductor pattern 21.

[0226] In some embodiments, impurities may be doped into the lower portion of each semiconductor pattern 21. Thus, a first source / drain region 21a can be formed in the semiconductor pattern 21. However, the operation of doping impurities into the semiconductor pattern 21 is not limited to this and can be performed in various other operations.

[0227] refer to Figure 23E , Figure 24E and Figure 25E The protective layer 40 covering the select gate electrode 145 can be removed. Due to the removal of the protective layer 40, a portion of the surface of the select gate electrode 145 can be exposed to the outside.

[0228] refer to Figure 23F , Figure 24F and Figure 25F A first gate electrode 25 may be formed on one side of each semiconductor pattern 21, and a gate insulating layer 23 may be interposed between the first gate electrode 25 and the semiconductor pattern 21. A second gate electrode 27 may be formed on the other side of the semiconductor pattern 21, and a gate insulating layer 23 may be interposed between the second gate electrode 27 and the semiconductor pattern 21. The first gate electrode 25 may extend in a first direction D1 to contact the select gate electrode 145. The second gate electrode 27 may have a shorter length than the first gate electrode 25 to prevent contact with the select gate electrode 145.

[0229] In some embodiments, impurities may be doped into the upper portion of each semiconductor pattern 21. Thus, a second source / drain region 21b and a channel region 21c located between the first source / drain region 21a and the second source / drain region 21b can be formed in the semiconductor pattern 21. However, the operation of doping impurities into the semiconductor pattern 21 is not limited to this and can be performed in various ways.

[0230] refer to Figure 23G , Figure 24G and Figure 25G A third insulating layer 50 is formed on the second insulating layer 30. The third insulating layer 50 may cover the exposed surfaces of the first gate electrode 25, the select gate electrode 145, and the gate insulating layer 23. The third insulating layer 50 does not cover the second source / drain region 21b of the semiconductor pattern 21 and the upper surface of the gate insulating layer 23; therefore, the second source / drain region 21b of the semiconductor pattern 21 and the upper surface of the gate insulating layer 23 may be exposed to an external entity.

[0231] refer to Figure 23H , Figure 24H and Figure 25H Bit line BL can be formed on the third insulating layer 50. Bit line BL can contact the exposed second source / drain region 21b.

[0232] In some implementations, the access transistor can take various forms. Figure 26 and Figure 27 This is a perspective view illustrating a semiconductor device according to some embodiments, showing a case where the access transistor is provided in a form different from the embodiments described above.

[0233] refer to Figure 26 The capacitor structure 100 can be disposed on the transistor structure 10. The capacitor structure 100 can be provided as one of the embodiments described above. In the accompanying drawings, Figure 26 The implementation shown is illustrated as an example.

[0234] The transistor structure 10 may include a first gate electrode 25 corresponding to a word line WL, a bit line BL, a semiconductor pattern 21, and a gate insulating layer 23. The semiconductor pattern 21, the first gate electrode 25, and the gate insulating layer 23 may form an access transistor. In this embodiment, each access transistor is connected to a single first gate electrode 25, and a second gate electrode corresponding to a back gate electrode may not be provided.

[0235] refer to Figure 27 The transistor structure 10 may include: a full-ring gate electrode 29 corresponding to the word line WL, a bit line BL, a semiconductor pattern 21, and a gate insulating layer 23. The semiconductor pattern 21, the full-ring gate electrode 29, and the gate insulating layer 23 may form an access transistor.

[0236] Each gate insulating layer 23 may surround a corresponding semiconductor pattern 21 within the semiconductor pattern 21. Each full-around gate electrode 29 may surround the semiconductor pattern 21, and each gate insulating layer 23 is located between the full-around gate electrode 29 and the semiconductor pattern 21. For example, each full-around gate electrode 29 may surround a channel region 21c of the corresponding semiconductor pattern 21.

[0237] As described above, the semiconductor device according to the embodiments can provide a cell array structure configured to significantly reduce the number of board line pads or contact plugs. Therefore, when the semiconductor device according to some embodiments is applied, the area efficiency of the three-dimensional ferroelectric memory can be improved.

[0238] As used herein, the term "at least one of..." can refer to and cover any and all possible combinations of one or more of the associated listed terms. For example, the term "at least one of A, B or C" means that: (i) at least one of A, (ii) at least one of B, (iii) at least one of C, (iv) at least one of A and at least one of B, (v) at least one of B and at least one of C, (vi) at least one of A and at least one of C, or (vi) at least one of A, at least one of B and at least one of C are possible, wherein A, B and C can be singular or plural.

[0239] While this specification contains numerous specific details of implementation, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in this specification within the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0240] While various embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims. < / k>

Claims

1. A semiconductor device, said semiconductor device comprising: Transistor structure; as well as A capacitor structure connected to the transistor structure. The capacitor structure includes: A plate line extending in a first direction. A ferroelectric capacitor, wherein the ferroelectric capacitor is connected to the plate wire. Global board line, the global board line and the board line are at the same height, and A board line selection transistor is connected to the global board line and the board line, and The transistor structure includes an access transistor, which includes a gate connected to a word line, a first terminal connected to the ferroelectric capacitor, and a second terminal connected to a bit line.

2. The semiconductor device according to claim 1, wherein, The ferroelectric capacitor includes: A portion of the plate line; Capacitor electrodes, the capacitor electrodes being located in a first trench extending into the plate line; and A ferroelectric layer is located between the plate line and the capacitor electrode.

3. The semiconductor device according to claim 1, wherein, The board line selection transistor includes: A portion of the plate line; A portion of the global board line; Select a gate electrode, wherein the selected gate electrode is located between the board line and the global board line; Select a semiconductor pattern, the selected semiconductor pattern surrounding at least a portion of the selected gate electrode; and Select a gate insulating layer, which is located between the select gate electrode and the select semiconductor pattern.

4. The semiconductor device according to claim 3, wherein, The capacitor structure includes multiple board lines and multiple global board lines, wherein the multiple board lines include the board lines and the multiple global board lines include the global board lines; The multiple plate lines are arranged in a matrix in the second direction and the third direction, and the first direction, the second direction and the third direction are perpendicular to each other; Among them, the multiple global board lines are stacked upwards on the third party, and Each of the multiple global board lines is located on the same layer as the board lines arranged in the same row among the multiple board lines.

5. The semiconductor device according to claim 4, wherein, The capacitor structure includes: (i) a capacitor region containing the ferroelectric capacitor, and (ii) a stepped region connected to the capacitor region and having a stepped shape.

6. The semiconductor device according to claim 5, wherein, In the stepped region, the multiple global board lines are stacked in multiple layers, and The lengths of the multiple global board lines decrease from the bottom layer to the top layer.

7. The semiconductor device according to claim 5, wherein, Each of the capacitor region and the stepped region extends in either the first direction or the second direction.

8. The semiconductor device according to claim 5, wherein, In the stepped region, the plurality of global plate lines extend in the same direction as the extension direction of the plurality of plate lines.

9. The semiconductor device according to claim 5, wherein, In the stepped region, the plurality of global plate lines extend in a direction perpendicular to the extension direction of the plurality of plate lines.

10. The semiconductor device of claim 5, further comprising a plurality of board line contact plugs, each board line contact plug contacting the upper or lower surface of a corresponding global board line among the plurality of global board lines in the stepped region.

11. The semiconductor device according to claim 1, wherein, The ferroelectric capacitor includes capacitor electrodes, and The access transistor includes: A semiconductor pattern, the semiconductor pattern including a first end connected to the capacitor electrode and a second end connected to the bit line. A gate electrode, the gate electrode being located on at least one side of the semiconductor pattern, and A gate insulating layer is located between the semiconductor pattern and the gate electrode.

12. The semiconductor device according to claim 11, wherein, The board line select transistor includes a select gate electrode extending into the transistor structure; Wherein, the gate electrode extends in a direction perpendicular to the selected gate electrode, and The selected gate electrode contacts the gate electrode in the cross region.

13. The semiconductor device according to claim 11, wherein, The gate electrode includes a first gate electrode located on a first side of the semiconductor pattern and a second gate electrode located on a second side of the semiconductor pattern.

14. The semiconductor device according to claim 13, wherein, The second gate electrode is a back gate electrode and has a shorter length than the first gate electrode.

15. The semiconductor device according to claim 11, wherein, The gate electrode is a full-ring gate electrode surrounding at least a portion of the semiconductor pattern.

16. The semiconductor device according to claim 1, wherein, The access transistor includes at least one of a buried channel array transistor, a planar transistor, a fin field-effect transistor, or a multi-bridge channel field-effect transistor.

17. A capacitor structure, the capacitor structure comprising: Board line; A ferroelectric capacitor, the ferroelectric capacitor being connected to the plate wire; Global board line, wherein the global board line and the board line are at the same height; as well as A board line selection transistor is connected to the global board line and the board line.

18. The capacitor structure according to claim 17, wherein, The plate line extends in a first direction and includes multiple plate lines arranged in a matrix in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other; The global board line includes multiple global board lines, which are stacked upwards on the third side. Each of the global board lines is at the same height as each of the multiple board lines located in the same row.

19. The capacitor structure according to claim 17, wherein, The ferroelectric capacitor includes a ferroelectric layer, and The ferroelectric layer includes at least one of lead zirconate titanate, strontium bismuth tantalate, lanthanum bismuth titanate, hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide.

20. A semiconductor device, said semiconductor device comprising: A cell array, the cell array comprising multiple memory cells located at the intersection of multiple word lines and multiple bit lines; as well as An address decoder, configured to send word line signals and global board line signals to the plurality of word lines and the plurality of global board lines, respectively. Each of the plurality of storage units includes: Multiple production lines Multiple ferroelectric capacitors, wherein the multiple ferroelectric capacitors are connected to the multiple plate lines, An access transistor includes a gate connected to one of the plurality of word lines, a first terminal connected to one of the plurality of ferroelectric capacitors, and a second terminal connected to one of the plurality of bit lines. Multiple global board lines, and Multiple board line selection transistors, each of which is connected to a corresponding one of the multiple global board lines and a corresponding one of the multiple board lines.

Images