EFUSE MEMORY

Abstract

A storage device and array architecture incorporate transmission gates and intermediate amplifiers to improve signal integrity and performance. The device includes multiple storage segments, each connected to a decoder via transmission gates, and an intermediate amplifier circuit arranged along word lines. The storage cells within the segments can be eFuse cells in various configurations, such as 2T / 1R and 1T / 1R. The intermediate amplifiers, designed as two-stage inverters with PMOS and NMOS transistors, are strategically positioned to ensure robust signal propagation. The storage array includes multiple word and bit lines, with intermediate amplifiers isolating adjacent storage cells, and incorporates decoders for voltage level shifting.The architecture supports various threshold voltage intermediate amplifiers, thus ensuring flexibility and energy efficiency under different operating conditions.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS This application claims priority over preliminary US application No. 63 / 737,253, filed on December 20, 2024, the entire disclosure of which is incorporated herein by reference. BACKGROUND Many integrated circuits (ICs) consist of millions of interconnected devices such as transistors, resistors, capacitors, and diodes on a single chip of a semiconductor substrate. Generally, the fastest possible operation and the lowest possible power consumption are desirable for ICs. Semiconductor ICs often incorporate one or more types of memory, such as complementary metal-oxide-semiconductor (CMOS) memory, antifuse memory, and electrical resistance memory (eFuse). Electronic memory used in integrated circuits (ICs) can be configured to store data bits in corresponding memory cells. A memory cell is a circuit configured to store one bit of data, typically using one or more transistors. The memory can be in the form of non-volatile memory (NVM). One type of NVM is one-time programmable (OTP) memory. Data stored in NVM is not lost when the IC is powered off. NVM allows an IC manufacturer, for example, to store a batch number and security information on the IC and can be used in many other applications. One type of NVM uses an electrical fuse, the eFuse. eFuses are typically integrated into semiconductor ICs by using a narrow strip (commonly called a "fuse connection") of conductive material (metal, polysilicon, etc.) between two pads commonly referred to as the anode and cathode. When a programming current is applied to the eFuse, the connection is broken (i.e., fused), changing the resistance of the eFuse. This is commonly referred to as "programming" the eFuse. The eFuse connection is sometimes referred to as a resistor in this application because the resistance of the eFuse changes during the programming process. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included in and form part of the description, illustrate various aspects of the present disclosure. A brief description of the drawings follows: Figures 1 and 2 show a storage device according to one embodiment. Figures 3 and 4 show storage segments that can be used in the storage devices of Figures 1 and 2. Figures 5, 6, 7 to 8 show memory cells that can be used in the storage segments of Figures 3 and 4. Figure 9 shows an intermediate amplifier architecture according to one embodiment. Figure 10 shows a process sequence suitable for operating a storage device with word line intermediate amplifiers. DETAILED DESCRIPTION Reference will now be made in detail to exemplary aspects of the present disclosure, which are shown in the accompanying drawings. Wherever possible, the same reference symbols are used in the drawings to denote identical or similar parts. The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For instance, the forming of a first element over or on top of a second element in the following description may cover embodiments in which the first and second elements are in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations. Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of an element or section to one or more other elements or sections, as shown in the figures. These spatially relative terms are intended to cover various orientations of the device used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly. A two-transistor, one-resistor memory cell (2T(NMOS)1R) is a type of dynamic random-access memory (DRAM) that uses two n-channel metal-oxide-semiconductor (NMOS) transistors and a single resistor to store one bit of information. In its basic configuration, the cell uses one NMOS transistor as the access transistor and another NMOS transistor as the storage transistor. The access transistor is connected to the word line (WL), which controls access to the memory cell, while the storage transistor is connected to the bit line (BL), which serves as the data input / output line. The resistor, typically implemented as a high-impedance element, is used to maintain the charge of the storage capacitor, ensuring that the data is retained for an extended period despite inherent leakage current. During a write operation, the word line is activated, turning on the access transistor and allowing the bit line to address the memory node. A voltage corresponding to a logic '1' or '0' is applied to the bit line, which then charges or discharges the storage capacitor via the storage transistor. The resistor helps stabilize the voltage at the memory node by providing a resistive path to the power supply or ground, which helps retain the stored charge. Once the word line is deactivated, the access transistor is turned off, isolating the memory node and trapping the charge representing the stored bit. During the read operation, the word line is reactivated, turning on the access transistor and connecting the memory node to the bit line. The voltage at the memory node is then sampled by a read amplifier connected to the bit line, which uses the detected voltage level to determine whether the stored bit is a '1' or '0'. The resistance plays a crucial role during the read operation, as it helps maintain the state of the stored charge and ensures that the measured voltage accurately reflects the stored data. However, due to the dynamic nature of charge storage, the data in a 2T(NMOS)1R memory cell must be refreshed periodically to counteract leakage currents and maintain data integrity over time.This regular refresh is a requirement typical of DRAM technology and ensures that the stored information remains correct and reliable. As described in the background of the invention, eFuses represent a type of NVM used in various IC devices. Such an eFuse memory can comprise an array of eFuse memory cells arranged in rows and columns, with each column having a corresponding bit line (BL) and each row having a corresponding word line (WL). Larger arrays of eFuse memory can be useful for programming purposes but also have disadvantages related to the IC design. In particular, longer WL and / or BL paths can lead to reduced programming performance. Longer WLs and BLs in memory circuits not only result in increased resistance and capacitance but also in signal integrity problems such as voltage drop, noise, and crosstalk, which can hinder proper data reading and writing.Another consequence is increased power consumption, as transmitting signals over longer lines requires more energy. Parasitic resistance can be higher along the line link (BL), which can impede current flow and thus affect power consumption and the speed of memory cell programming, leading to further effects as described below. Variations in line characteristics across the array can result in uneven performance, and reliability issues such as electromigration can occur, which can degrade line integrity over time. Furthermore, the additional latency caused by longer lines can affect the timing and speed of memory operations, thereby degrading the overall system performance. In a larger storage device, the programming current can therefore be increased, but at the cost of higher leakage current in the WL path. As described above, a longer BL path can also lead to higher parasitic resistance. In an ultra-high-density memory (UHD) structure, the performance with respect to programming current (the current used to write data to the memory cells) can be worse than in a conventional storage structure. This performance degradation is attributed to higher parasitic resistance in the BL. The Ron value of a programming device denotes the device's on-resistance when it is in a conductive state. In the context of memory circuits such as eFuse memory, the Ron value represents the resistance of the programming device (e.g., a transistor) when it is switched on and current can flow through it. A lower Ron value generally means that the device can conduct current more efficiently, resulting in better performance during programming operations. Conversely, a higher Ron value indicates a higher resistance when the device is conducting, which can restrict current flow and degrade the memory's programming performance. As detailed in the figures, an intermediate amplifier circuit can be implemented on the WL to amplify or restore the signal as it travels along the WL. Due to the inherent resistance and capacitance of long transmission paths, signals can degrade as they propagate, leading to slower response times and potential errors when accessing memory cells. To address this issue, intermediate amplifier circuits are strategically placed along the WL to ensure signal strength and integrity are maintained, enabling reliable and fast access to memory cells located further away from the WL driver. When a voltage signal is applied to a waveguide (WL) to activate a row of memory cells, the intermediate amplifier circuit can detect this signal and restore it to its original amplitude. This involves amplifying the voltage level and, if necessary, reshaping the signal to remove any distortion that may have occurred along the way. In this way, intermediate amplifiers ensure that the signal remains strong and clear enough to reliably turn on the access transistors of the memory cells along the entire length of the WL. The placement and design of these intermediate amplifiers were carefully optimized to balance signal integrity, power consumption, and overall circuit complexity. By using intermediate amplifier circuits, memory designers can ensure that word line signals remain stable, thereby improving the speed and reliability of memory access operations across the entire array. Fig. 1 shows a schematic layout of a circuit implementing a storage device 100 within the scope of the present disclosure. The storage device 100 comprises a first array 102, also referred to as a storage array, which is a main array among a larger number of main arrays. The first array 102 is connected to a first transmission gate 104. The first transmission gate 104 is one among a large number of transmission gates 104, each belonging to one or more main arrays.A set of main arrays (e.g., the first array 102) can be connected via the transmission gates 104 to a first decoder and a second decoder. In the embodiment shown in Fig. 1, the first array 102 is connected via the transmission gates 104 to a common bit-line decoder 106 and a common word-line decoder 108. The entire set of main arrays connected to the same bit-line decoder 106 and the same word-line decoder 108 is called the first memory segment 110. The first memory segment 110 includes a main array 102, a second array to its right in Fig. 1 (connected along the same word line), a third array below the main array 102 (connected along the same bit line), and a fourth array (which is not connected to the main array 102 by any word or bit lines).In alternative embodiments, there can be any number of main arrays within a given memory segment. There can also be any number of transfer gates 104. It is possible for multiple memory arrays (e.g., the main array 102) to be connected to adjacent memory arrays via designated transfer gates. Alternatively, a single transfer gate 104 can connect more than two memory arrays. This means that multiple transfer gates can be replaced by a single connected transfer gate. Fig. 1 shows four memory segments (including the first memory segment 110, a second memory segment in the upper right quadrant, a third memory segment in the lower left quadrant, and a fourth memory segment in the lower right quadrant). In practice, there may be several memory segments in a given device such as the memory device 100. The four memory segments are each connected to a bitline decoder 106 and a wordline decoder 108, which can also be referred to as level shifters. In the context of a 2T(NMOS)1R memory cell, a decoder or level shifter (e.g., the bitline decoder 106 and the wordline decoder 108) is a circuit component that serves to convert voltage levels between different parts of the memory circuit. This is used, for example, in scenarios where the memory cell operates at a different voltage level than peripheral circuits such as wordline drivers or read amplifiers. The level shifter ensures that signals across these different voltage domains are correctly interpreted and transmitted, thus facilitating proper operation and improving data integrity within the memory cell. Level shifters are components in memory circuits that enable voltage conversion between different parts of the circuit. In memory devices using 2T(NMOS)1R cells, these components are used to ensure proper data transmission between the memory cells and their associated peripheral circuitry, as shown in Memory Device 100. The primary function of level shifters is to convert voltage signals between different parts of the memory circuit, especially when the memory cell operates at a different voltage level than peripheral circuitry such as word line drivers or read amplifiers. The basic function of a level shifter is to receive an input signal with a specific voltage level and generate a corresponding output signal with a different voltage level. This conversion process is crucial for maintaining correct signal interpretation across different voltage domains within the memory architecture. For example, if the memory cells operate at a lower voltage than the peripheral logic circuits, the level shifter converts the lower-voltage signals from the cells to higher-voltage signals compatible with the peripheral logic, and vice versa. This conversion ensures that the correct logic levels are maintained and that the transistors in both the memory cells and the peripheral circuits switch accordingly. In the context of memory operations, level shifters play a particularly important role in both read and write operations. During write operations, the level shifter adjusts the voltage levels of the signals controlling the access transistor, ensuring that it is correctly switched on or off so that the data can be properly written to the memory node. Similarly, during read operations, the level shifter adjusts the voltage levels sampled by the memory node to ensure compatibility with the read amplifier 114 and other readout circuitry. The implementation of level shifters in memory architectures is particularly important when connected to word lines 120 and bit lines 122. These components work together with decoders such as the bit line decoder 106 and the word line decoder 108 to ensure correct voltage conversion throughout the memory circuitry. This voltage level adjustment is fundamental for maintaining signal integrity and ensuring reliable data transmission between the various sections of the memory architecture. The importance of level shifters extends beyond their basic functionality, broadly impacting the reliability and power consumption of memory operations. By enabling different sections of the circuit to operate at their optimal voltage levels while maintaining proper data transmission between these sections, level shifters help avoid potential problems such as data misinterpretation due to voltage errors. This capability is particularly crucial in modern memory architectures where energy efficiency and reliable operation are paramount. In a 2T(NMOS)1R memory cell, level shifters can be used for controlling the WL or for connection to the BL circuit. During a write operation, the level shifter adjusts the voltage levels of the signals controlling the access transistor, ensuring that it is correctly switched on or off so that data can be written to the memory node. During a read operation, the level shifter adjusts the voltage levels sampled by the memory node so that they are compatible with the read amplifier and other readout circuitry. As described above, the first memory segment 110 comprises a series of word lines and bit lines. Although longer word and bit lines can generally offer advantages, the functionality of the memory device 100 may be lost if there is a significant voltage or current drop due to parasitic loads. The first memory segment 110 includes an intermediate amplifier 112, which restores the voltage of the word lines to the desired voltage level at the midpoint of the word line. Although a single intermediate amplifier 112 is shown at the midpoint of the word lines, one, two, or more intermediate amplifiers 112 may be present in the first memory segment 110 or in any of the other multiple memory segments. A controller 116 serves as a central control unit for coordinating the operations in the various components of the storage device 100. In conjunction with a power supply 118, the controller 116 controls the operation of the word line decoder 108 and the read amplifier 114 to ensure proper memory access and data processing. The controller 116 is coordinated with the word line decoder 108 in such a way that the voltage levels applied to the word lines 120 are managed, which is particularly important when intermediate amplifiers 112 distributed across the memory segments 110 are used. By controlling the word line decoder 108, the controller 116 helps to maintain suitable voltage levels along the word lines 120, even when the signals pass through several intermediate amplifiers 112. During read operations, the controller 116 works closely with the read amplifier 114 to accurately acquire and interpret the stored data values. The controller 116 manages the timing and sequence of operations between the bit line decoder 106 and the read amplifier 114, thus ensuring proper coordination during memory accesses. This is particularly important considering the various memory cell configurations supported by the device, including both 2T(NMOS)1R and 2T(PMOS)1R arrays. The interaction of the controller 116 with these components is particularly important during the programming of the eFuse memory cells. When programming operations are performed, the controller 116 must ensure that an appropriate programming current flows through the bit lines 122 while simultaneously maintaining word line activation by the word line decoder 108. This coordination is essential for achieving reliable programming and limiting the effects of parasitic resistance and leakage current, which can impair programming performance. By controlling the two decoders and the read amplifier 114, the controller 116 helps to maintain signal integrity in the memory segments 110, especially in scenarios where multiple memory segments are connected via transmission gates 104. This comprehensive control ensures that memory operations remain reliable even in ultra-high-density memory structures where parasitic resistances and signal degradation could impair performance. Fig. 2 is a schematic view of the storage device 100 from Fig. 1, showing in particular some of the electrical structures contained therein. Fig. 2 shows in particular an array of 2-transistor-1-resistor memory cells (here referred to as 2T(NMOS)1R memory cells) that form the main array 102. For the sake of simplicity, a single 2T(NMOS)1R memory cell is shown in Fig. 2, although it is clear that the main array 102 has several such memory cells in an array or other repeating arrangement. Fig. 2 also shows several word lines 120 (here designated WL) and several bit lines 122 (here designated BL). As shown in Fig. 2, intermediate amplifiers 112 are arranged along the length of the several word lines 120 in the first memory segment 110 (as well as the other memory segments). These intermediate amplifiers 112 maintain the voltage level of the word line along its length. The illustration shows a 2T(NMOS)1R memory cell as the core component of each of the main arrays, but it is understood that in alternative embodiments any number of memory cell architectures can be used, some of which are shown in Figures 5, 6, 7 to 8. The multiple memory cells could, for example, be multiple eFuse memory cells, as described above. The memory device 100 can be implemented with various memory cell architectures beyond the basic 2T(NMOS)1R configuration shown in the figures. These architectures include both NMOS and PMOS implementations, with configurations ranging from two-transistor arrangements to single-transistor designs. While the 2T(NMOS)1R memory cell represents one specific implementation, alternative arrangements such as a 2T(PMOS)1R configuration can be used to achieve similar functionality with different electrical characteristics. The memory cell architecture is also flexible with respect to different resistor configurations. Some implementations use a direct connection to VDD instead of a resistor, while others retain the traditional resistor arrangement. These variations in memory cell design allow for optimization based on specific performance requirements and manufacturing constraints. The choice between NMOS and PMOS implementations, as well as the decision to use one or two transistors, can be made based on factors such as power consumption, speed requirements, and integration considerations. In the context of eFuse implementations, the memory cells utilize a narrow strip of conductive material, commonly referred to as a "resistive junction," located between two pads that serve as the anode and cathode. Programming these eFuse cells involves applying a programming current that physically alters the resistive junction, changing its resistance and thereby storing data. This basic eFuse structure can be integrated into various memory cell architectures, enabling flexible implementation while maintaining the core functionality of non-volatile memory. The eFuse implementation is particularly useful in non-volatile memory applications where data must be retained even after the device is disconnected from the power supply. This makes eFuse memory cells especially suitable for storing critical information such as batch numbers and safety data. The programming process permanently alters the physical structure of the resistive junction, ensuring that the stored data remains stable and reliable over time. This characteristic makes eFuse implementations particularly useful for applications where data permanence is critical. When implementing these different memory cell architectures, the storage device can use 100 transmission gates 104 and intermediate amplifiers 112 to maintain signal integrity across the memory segments 110. This approach ensures reliable operation regardless of the chosen memory cell architecture and enables a flexible design while maintaining robust performance characteristics. Figures 3 and 4 show a comparison of a simple design with one intermediate amplifier and a more complex design with several intermediate amplifiers. Fig. 3 shows a memory segment 110 with a single intermediate amplifier 112. As indicated by the ellipsis, several 2T(NMOS)1R memory cells can be arranged on the word line 120 on both sides of the intermediate amplifier 112. Fig. 4 shows, as a counterpart, a memory segment 110 with several intermediate amplifiers 112. In the embodiment of Fig. 4, each of the 2T(NMOS)1R memory cells is separated from adjacent 2T(NMOS)1R memory cells by an intermediate amplifier 112. Fig. 4 thus shows a system in which the input voltage along the word line 120 should be nearly identical, because each 2T(NMOS)1R memory cell receives a signal whose voltage has been adjusted by an intermediate amplifier 112. It goes without saying that Figures 3 and 4 show two limiting cases, but embodiments are also considered in which there is more than one intermediate amplifier 112, but not necessarily an associated intermediate amplifier 112 for each individual memory cell. For example, a system could have a pair of intermediate amplifiers 112 or one intermediate amplifier 112 for every n memory cells, where n is greater than 1. In general, WL intermediate amplifiers 112 are used to balance WL loads and to provide programmability and leakage currents similar to a standard-structure memory architecture. Local transmission gate circuits (e.g., transmission gate 104) are used to improve the parasitic resistance of the BL and achieve high performance. For this reason, the intermediate amplifiers 112 are shown only along the word lines 120 and not along the bit lines 122. This configuration offers improved performance in terms of programmability and leakage current. A minimum gate length can be selected for high-voltage operation. In some examples, an arrangement with two transistors and one resistor (2T1R) is used, wherein a transmission gate circuit is connected to the bit lines 122 and an intermediate amplifier 112 is connected to the word lines 120. One or more intermediate amplifiers 112 can be connected to the memory segments. Other embodiments use a memory cell arrangement with one transistor and one resistor (1T1R). The threshold voltage (VT) of the one or more transistors of the memory cell can fluctuate in some embodiments. Furthermore, NMOS and PMOS memory cell transistors are disclosed. The memory segment 110 can be implemented with different configurations of intermediate amplifiers 112 along the word lines 120, as shown in Figs. 3 and 4. In the simpler configuration shown in Fig. 3, the memory segment 110 uses a single intermediate amplifier 112 located centrally along the word line 120. This arrangement allows multiple 2T(NMOS)1R memory cells to be placed on either side of the intermediate amplifier 112, with the intermediate amplifier serving to maintain signal integrity along the word line. A more sophisticated implementation is shown in Fig. 4, in which the memory segment 110 has several intermediate amplifiers 112 in a distributed arrangement along the word line 120. In this configuration, each individual 2T(NMOS)1R memory cell is separated from neighboring memory cells by a designated intermediate amplifier 112. This arrangement ensures that the input voltage remains nearly constant along the entire word line 120, since each memory cell receives a signal that has been freshly set by its corresponding intermediate amplifier. Between these two extreme cases, various intermediate configurations are possible in memory segment 110. For example, the system could be designed with two intermediate amplifiers 112 or with intermediate amplifiers placed at regular intervals corresponding to every nth memory cell, where n represents any number greater than one. This flexibility in the arrangement of the intermediate amplifiers allows for optimization based on specific design and performance requirements. The implementation of intermediate amplifiers 112 specifically along the word lines 120, and not along the bit lines 122, serves an important purpose: to overcome difficulties with word line loads while maintaining programmability comparable to standard memory structures. This arrangement operates using local transmission gate circuits (the transmission gates 104) specifically designed to improve the parasitic resistance of the bit lines and achieve optimal performance. The combination of these elements enables improved performance in terms of programmability and leakage current, particularly in high-voltage operating modes. The effectiveness of this architecture is particularly evident in ultra-high-density memory structures, where the strategic placement of the intermediate amplifiers 112 helps to maintain consistent signal strength and integrity throughout the entire memory segment 110. This approach ensures that the voltage levels remain stable and suitable for the proper operation of the memory cells, regardless of a cell's position along the word line 120. Figures 5, 6, 7 to 8 show some examples of memory cell arrangements considered in an eFuse environment. Figure 5 is a circuit diagram of a memory cell 124. Figure 5 shows the 2T(NMOS)1R memory cell 124 already described in Figures 2, 3 to 4. Figure 6 shows an alternative memory cell 124 with a PMOS architecture, still with two transistors and a resistor (i.e., a 2T(PMOS)1R memory cell). Figure 7 shows an alternative embodiment of a memory cell 124 in which the resistor has been removed and replaced by a direct connection to VDD. Figure 8 shows an alternative embodiment of a memory cell 124 in which a single transistor is connected to the WL, while the bit line is connected to one side of the transistor via a resistor, and the other side of the transistor is connected to ground. The 2T(NMOS)1R memory cell 124 shown in Fig. 5 represents a basic architecture that utilizes two n-channel metal-oxide-semiconductor transistors and a single resistor for data storage. This configuration uses one NMOS transistor as the access transistor and another as the storage transistor, with the access transistor connected to the word line for controlling memory cell access and the storage transistor connected to the bit line for data input / output. The resistor helps maintain the charge of the storage capacitor, thus ensuring improved data retention. In the 2T(NMOS)1R memory cell shown in Fig. 5, the activation of word line 120, when a current is initially applied, triggers the access transistor by applying a voltage to its gate terminal. When this transistor is switched on, it creates a conduction path between its source and drain terminals, allowing bit line 122 to be connected to the memory node. The voltage applied across bit line 122 then acts on the gate of the memory transistor, while the resistor provides a path either to the power supply or to ground, depending on the logic state being written. During this process, the storage capacitor begins to charge or discharge through the storage transistor, with the current flow being determined by the voltage difference between the bit line and the memory node. An alternative implementation, shown in Fig. 6, utilizes the PMOS architecture while retaining the configuration with two transistors and resistors (2T(PMOS)1R). This variant offers different electrical characteristics with similar functionality to its NMOS counterpart. When implemented in the storage device 100, the PMOS configuration can offer specific advantages in terms of power consumption and switching characteristics, particularly when integrated with systems featuring word-line decoder 108 and bit-line decoder 106. The structure shown in Fig. 6 exhibits different current and voltage behavior than the 2T(NMOS)1R configuration shown in Fig. 5. In the 2T(PMOS)1R configuration shown in Fig. 6, the basic operating principle remains similar, but the current flow characteristics differ due to the use of PMOS transistors instead of NMOS transistors. While the NMOS configuration relies on the output being pulled low upon activation, the PMOS implementation pulls the output high, resulting in different voltage swing characteristics during switching operations. The configuration shown in Fig. 7 represents a significant departure from the structure of Fig. 5, in that the resistor has been removed and a direct connection to VDD has been established. This modification alters the current path for both write and read operations and eliminates the resistive element that contributes to stabilizing the voltage at the memory node. Without the voltage-stabilizing effect of the resistor, the circuit relies more heavily on the transistors' characteristics to maintain the stored charge, which can affect both power consumption and data retention. Fig. 7 shows a modified architecture in which the resistor is omitted and replaced by a direct connection to VDD. This simplified structure reduces the number of components while maintaining the essential memory characteristics. When this configuration is integrated into the larger memory device 100, it can offer advantages in terms of ease of manufacture and potentially lower parasitic effects, while simultaneously benefiting from the maintenance of signal integrity ensured by the intermediate amplifiers 112 along the word lines 120. The single-transistor configuration shown in Fig. 8 represents a further simplified architecture in which a single transistor is connected to the word line, with the bit line connected to one side of the transistor via a resistor, while the other side is connected to ground. This minimalist approach can be particularly advantageous in ultra-high-density memory applications where space saving is paramount. When implemented in the memory segments 110, this configuration can achieve a high integration density while ensuring reliable operation through the strategic placement of the intermediate amplifiers 112. Fig. 8 shows a simplified architecture with a single transistor, where the bit line is connected to one side of the transistor via a resistor, while the other side is connected to ground. The current behavior of this configuration differs significantly from the structure in Fig. 5, as a single transistor is used for both access and storage functions. During write operations, the current path runs directly through the resistor to ground, with the voltage level at the storage node determined by the resistance value and the applied bit line voltage. Each of these memory cell architectures can be effectively integrated into the broader structure of the Memory Device 100 and works in conjunction with the Transmission Gates 104 and the Intermediate Amplifiers 112 to maintain signal integrity. The choice between these configurations can be optimized based on specific application requirements such as power consumption, speed requirements, and integration density. The flexibility of the Memory Device 100 in accommodating these different cell architectures while maintaining robust performance characteristics through its intermediate amplifier and transmission gate infrastructure makes it particularly versatile for diverse implementation scenarios. The reliability and fabrication requirements for these memory cell architectures vary considerably depending on the implementation. In the 2T(NMOS)1R configuration, the use of two NMOS transistors provides robust data storage capabilities by combining an access transistor connected to the word line and a storage transistor connected to the bit line. The reliability of this architecture is enhanced by the resistor's role in maintaining the charge of the storage capacitor, which is particularly important for data storage in high-density applications. The 2T(PMOS)1R implementation offers significant manufacturing advantages in certain scenarios, particularly when considering power consumption characteristics. The PMOS configuration can be especially beneficial when integrated into systems with word-line and bit-line decoders, although it requires careful consideration of voltage level conversion between the different circuit domains to ensure reliable operation. In ultra-high-density memory structures, the choice between NMOS and PMOS implementations is particularly important due to parasitic resistance and leakage currents. NMOS implementations generally offer better programming performance due to their inherent characteristics, while PMOS configurations can offer advantages in limiting leakage current. These aspects are especially important when dealing with longer bit and word lines, where signal degradation can impair programming effectiveness. Questions of production yield are closely linked to the complexity of the respective architecture. The simplified single-transistor configuration can potentially offer a higher production yield due to the smaller number of components, but this must be weighed against potential disadvantages regarding reliability. In contrast, while dual-transistor configurations are more complex to manufacture, their dual-transistor control scheme can provide greater stability. Long-term stability in high-density applications is significantly influenced by the presence of intermediate amplifiers and transmission gates in the overall architecture. These components help maintain signal integrity regardless of the chosen transistor implementation, although their effectiveness can vary depending on whether NMOS or PMOS configurations are used. Strategic placement of intermediate amplifiers along the word lines is particularly important to ensure consistent performance across large memory arrays, regardless of whether NMOS or PMOS implementations are selected. The issues surrounding parasitic resistance in ultra-high-density structures have a significant impact on programming current characteristics, requiring careful design optimization for both NMOS and PMOS implementations to ensure reliable programming performance. This is particularly important when considering the Ron value of program devices, which directly affects the effectiveness of programming operations and the overall reliability of the memory structure. The power consumption characteristics of 2T(NMOS)1R versus 2T(PMOS)1R memory cell configurations represent important trade-offs in the operation of the memory device 100. In the 2T(NMOS)1R configuration, the memory cell uses one NMOS transistor as the access transistor and another as the storage transistor, with the access transistor connected to word line 120 and the storage transistor to bit line 122. This arrangement affects power consumption, particularly during data storage, where the resistor helps to maintain the charge of the storage capacitor. The power consumption of the 2T(NMOS)1R configuration is particularly important during write operations, where word line 120 is activated to turn on the access transistor, allowing bit line 122 to address the memory node. During this process, power is consumed because the voltage corresponding to the logic states charges or discharges the storage capacitor via the storage transistor. The resistor's role in stabilizing the voltage at the memory node affects the overall power consumption during active operation. In the 2T(PMOS)1R configuration, the performance characteristics differ primarily due to the inherent properties of PMOS transistors. This configuration becomes particularly attractive when considered in conjunction with word line decoders 108 and bit line decoders 106, especially in scenarios requiring voltage level conversion between different circuit domains. The PMOS implementation can offer advantages in terms of standby power consumption due to its inherent properties. In both configurations, power consumption is significantly affected by the presence of parasitic resistances and leakage currents, particularly in ultra-high-density memory structures. The parasitic resistance along the bit lines can affect programming current characteristics, which directly impacts active power consumption during write operations. These issues are especially important when considering the Ron value of programming devices, as it affects the effectiveness of programming operations and the overall active-state power consumption. The implementation of intermediate amplifiers 112 along the word lines 120 affects power consumption in both architectures, as these components, while contributing to maintaining signal integrity, also incur additional power requirements. This is particularly important for larger memory arrays, where signal degradation would otherwise necessitate higher power consumption to maintain reliable operation. The strategic placement of the intermediate amplifiers 112 helps to optimize power consumption while ensuring consistent performance across all memory segments 110. Fig. 9 shows a circuit of an intermediate amplifier 112 according to one embodiment. The intermediate amplifier 112 is connected to several word lines 120. These individual word lines are numbered word line 120A to 120n. The intermediate amplifier 112 shown in Fig. 9 is used for amplifying or restoring signals in digital circuits, e.g., on word lines 120A-120n. The specific architecture of the intermediate amplifier 112 in Fig. 9 consists of two CMOS inverter stages connected in series. Each inverter stage comprises one PMOS transistor and one NMOS transistor. The uppermost transistor in each inverter stage is a PMOS transistor. The sources of the PMOS transistors are connected to the supply voltage (VDD), and their drains are connected to the output of the inverter stage. The gates of the PMOS transistors are connected to the input signal of the inverter stage. The lower transistors in each inverter stage are NMOS transistors. Their sources are connected to ground (GND), and their drains are connected to the output of the inverter stage.The gates of the NMOS transistors are also connected to the input signal of the inverter stage. The input signal (output from word lines 120A-120n) is fed into the gate terminals of both the PMOS and NMOS transistors of the first inverter. When the input is high, the PMOS transistor is turned off and the NMOS transistor is turned on, pulling the output of this stage to ground and producing a low output. Conversely, when the input is low, the PMOS transistor is turned on and the NMOS transistor is turned off, pulling the output of this stage to VDD and producing a high output. The output of the first inverter stage serves as the input for the second inverter stage. This stage functions similarly: if the input of the second stage is high, the output is low, and if the input is low, the output is high. Therefore, the second inverter stage inverts the signal again, restoring it to its original logic level, but with a refreshed signal strength. The intermediate amplifier 112 as a whole amplifies the signal input via the word lines 120A-120n as it travels from input to output. The two inverter stages work together to correct any signal degradation or attenuation, thus maintaining signal integrity and strength. This is particularly useful for long word line paths (120A-120n) in integrated circuits, where signal degradation due to resistance and capacitance can be significant. By placing intermediate amplifiers at intervals along the word lines (120A-120n), the signal can be kept strong and reliable, ensuring the proper operation of the memory cells, memory segments, and storage device. Naturally, there are various alternative architectures that can be used to implement the intermediate amplifier 112. For example, the intermediate amplifier 112 could take the form of a standard threshold voltage intermediate amplifier, a low threshold voltage intermediate amplifier, a high threshold voltage intermediate amplifier, or a mixed threshold voltage intermediate amplifier. Not all of these intermediate amplifiers need to consist of two-stage inverters 112 like the one shown in Fig. 9. Although other intermediate amplifier architectures are not specifically shown here, many such alternative designs are known and could be used instead of the specific implementation shown in Fig. 9. Several alternative intermediate amplifier architectures could be implemented in the storage device 100 to maintain signal integrity along the word lines 120. A standard threshold voltage intermediate amplifier represents an alternative approach in which the threshold voltage of both the PMOS and NMOS transistors is maintained at standard values ​​for the respective process technology. This configuration offers a balanced approach to signal recovery while maintaining common power consumption characteristics. Low-threshold voltage intermediate amplifiers offer another alternative architecture in which the transistor threshold voltages are reduced compared to standard values. This configuration can provide faster switching speeds and better performance in low-voltage operation, although it may be associated with increased leakage currents. This trade-off is particularly important when implementing intermediate amplifiers in ultra-high-density memory structures. High-threshold voltage intermediate amplifiers represent a third alternative, employing transistors with high threshold voltages. This configuration can be particularly advantageous in scenarios where minimizing leakage current is a priority, even if it may result in somewhat slower switching speeds. The higher threshold voltages can help maintain signal integrity while simultaneously reducing the standby current consumption of the 120 word lines. Mixed-threshold voltage inter-amplifiers represent a hybrid approach in which transistors with different threshold voltages are combined in the same inter-amplifier structure. This configuration allows for optimization of both performance and power consumption characteristics and can offer advantages in certain implementations of the memory segment 110 where different power requirements exist along different sections of the word lines 120. These alternative intermediate amplifier architectures, while differing from the two-stage inverter implementation shown in the figures, all serve the fundamental purpose of maintaining signal integrity along the word lines 120 in the storage device 100. The choice between these different intermediate amplifier architectures can be optimized based on the specific requirements for power consumption, switching speed, and leakage current in the overall storage architecture. The different intermediate amplifier architectures have a significant impact on the timing characteristics of the signals on word line 120. The standard two-stage inverter implementation of the intermediate amplifier 112 processes signals by having each inverter stage respond to input changes, with the PMOS transistor being switched off and the NMOS transistor being switched on at high inputs, and vice versa at low inputs. This configuration provides a basis for signal propagation and recovery along word lines 120. Standard threshold voltage amplifiers maintain the usual rise and fall times based on the standard threshold voltages of the process technology. When used along the 120 word lines, these amplifiers provide smooth signal amplification and recovery, ensuring that the voltage signal remains strong enough to reliably turn on the memory cell access transistors along the entire length of the word line. Low-threshold voltage intermediate amplifiers can achieve faster switching speeds due to their lower threshold voltages, thereby reducing both the rise and fall times of signals on the word lines 120. This improved switching speed can be particularly advantageous in memory segments 110, where fast access times are critical. However, this increased speed must be balanced against a potential increase in leakage current, which can degrade the stability of the voltage levels between switching operations. High-threshold voltage intermediate amplifiers typically exhibit longer rise and fall times due to their high threshold voltages. While this can lead to increased propagation delay along the 120 word lines, the higher thresholds offer improved noise immunity and more stable voltage levels. This characteristic is particularly important for signal integrity in larger storage arrays, where noise and signal degradation are significant concerns. Mixed-threshold voltage intermediate amplifiers offer the possibility of optimizing various aspects of signal timing control by combining transistors with different threshold voltages. This architecture can be particularly useful in resolving the trade-off between switching speed and signal stability by enabling tailored timing characteristics based on the specific requirements of different sections within the memory segments 110. The placement and architecture of these intermediate amplifiers have a significant impact on the overall timing characteristics of the storage device 100, particularly in scenarios where the word lines 120 extend across multiple memory segments 110. The strategic positioning of the intermediate amplifiers 112 helps to ensure that the signals remain robust and the timing characteristics stay within appropriate parameters, thereby improving the speed and reliability of memory accesses across the entire array. Fig. 10 is a flowchart showing a method 126 for operating a device according to Fig. 1 or Fig. 2 with a storage segment as shown in Fig. 3 and Fig. 4. Method 126 comprises outputting a time-varying voltage at a WL at 128 and outputting a time-varying voltage at a BL at 130. In practice, each storage device (e.g., the storage device 100 of Figs. 1 and 2) contains multiple memory cells, so that outputting a time-varying voltage at a WL at 128 involves sending a time-varying voltage to a large number of WLs. This can be done, for example, by forwarding signals to multiple WLs 120 through a word line decoder 108, as shown and described in Figs. 1 and 2. Similarly, multiple BLs at 130 can be output with a time-varying voltage by using the structures shown and described with respect to the bit line decoder 106 and the bit lines 122 of Figs. 1 and 2. At 132, intermediate amplifiers are used to amplify the signal output to the WLs at 128. As described above, the use of intermediate amplifiers to amplify the signal at the WLs counteracts parasitic signal losses and improves the operation of the storage device. In the embodiments shown in Figs. 1, 2, 3 to 4, for example, intermediate amplifiers 112 were used to amplify the signal output to the WLs. In various embodiments, the amplification can be achieved by connecting NMOS and PMOS transistors, as shown in Fig. 9, among other known variants of intermediate amplifiers. At 134, the WL and BL voltages are received at each of the memory cells. Many of the memory cells receiving the WL and BL voltages receive an amplified signal at the WL terminal because the signal was amplified at 132 by an intermediate amplifier. This avoids the signal quality degradation that could occur with a conventional device. The structures and methods described in this document address several important challenges in the development of storage devices, with a focus on signal integrity and programming performance in large memory arrays. The fundamental problem arises from the inherent limitations of longer word lines (WLs) and bit lines (BLs) in memory circuits, which face increased resistance and capacitance, leading to signal integrity issues such as voltage drop, noise, and crosstalk. These problems can significantly disrupt the proper reading and writing of data while simultaneously increasing power consumption, as more energy is required to transmit signals over longer lines. A particular challenge is the degradation of programming performance in ultra-high-density memory structures due to the higher parasitic resistance in the bit lines. This parasitic resistance impedes current flow and impairs power consumption and the speed of programming memory cells. Furthermore, longer word line paths can lead to increased leakage currents, so a trade-off must be found between achieving higher programming current capabilities and limiting leakage current in the word lines. The solution implements a sophisticated combination of amplifiers and transmission gates to ensure signal integrity throughout the memory array. Amplifier circuits are strategically placed along the word lines to amplify or restore signals along their path, counteracting the degradation that naturally occurs due to resistance and capacitance in long transmission paths. These amplifiers ensure that the signals maintain sufficient strength to reliably activate the memory cells, regardless of their position along the word line. The architecture solves these problems by implementing transmission gates between memory segments, which help limit the parasitic resistance of the bit lines and achieve optimal performance. This approach is particularly effective in ultra-high-density memory structures, where maintaining consistent signal strength and programmability is critical. The combination of intermediate amplifiers on the word lines and transmission gates on the bit lines provides a comprehensive solution to signal degradation problems while maintaining programmability comparable to standard memory structures. The solution also supports various memory cell architectures, including 2T(NMOS)1R, 2T(PMOS)1R, and simplified single-transistor configurations, enabling flexible implementation while maintaining robust performance characteristics. This versatility allows for optimization based on specific application requirements, while ensuring reliable operation through the strategic placement of intermediate amplifiers and transmission gates. The architecture effectively mitigates drawbacks in signal integrity, power consumption, and overall circuit complexity, providing a practical solution for high-density memory applications. Implementing level shifters in the architecture solves the challenge of voltage conversion between different domains of the circuit and ensures proper data transmission between the memory cells and peripheral circuits. This aspect of the solution is particularly important when different parts of the memory circuitry operate at different voltage levels, helping to prevent data corruption and ensure reliable operation of the entire storage device. According to a first aspect, a device is disclosed comprising a first memory segment connected to a first decoder via a first transmission gate; a second memory segment separated from the first memory segment by a second transmission gate and connected to the first decoder via the second transmission gate; a third memory segment connected to the first decoder via a third transmission gate; and an intermediate amplifier circuit connected between the first memory segment and the third memory segment via several word lines connected to a second decoder. According to a second aspect, a storage array is disclosed, comprising several word lines; several bit lines; several memory cells, each of the several memory cells being connected to a corresponding one of the several word lines and a corresponding one of the several bit lines; and several intermediate amplifiers arranged along the several word lines such that each of the several memory cells is separated from a neighboring one of the several memory cells along its associated word line by at least one of the several intermediate amplifiers. According to a third aspect, a method for operating a memory segment is disclosed, comprising outputting a time-varying voltage signal to several word lines via a word line decoder; outputting a time-varying voltage signal to several bit lines via a bit line decoder; receiving, at each of the several memory cells, the time-varying voltage belonging to one of the several word lines and the time-varying voltage belonging to one of the several bit lines; and amplifying the time-varying voltage on each of the several word lines at at least one intermediate amplifier, wherein the at least one intermediate amplifier is arranged along each of the several word lines such that each of the several memory cells is separated from an adjacent one of the several memory cells along its associated word line by the at least one intermediate amplifier. This disclosure describes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying further processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. They should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications here without deviating from the spirit and scope of the present disclosure. After describing the preferred aspects and implementations of the present disclosure, it is readily apparent to those skilled in the art that modifications and equivalents of the disclosed concepts can be found. However, it is intended that such modifications and equivalents be included within the scope of the accompanying claims. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature US 63 / 737,253

[0001]

Claims

Device comprising: a first memory segment connected to a first decoder via a first transmission gate; a second memory segment separated from the first memory segment by a second transmission gate and connected to the first decoder via the second transmission gate; a third memory segment connected to the first decoder via a third transmission gate; and an intermediate amplifier circuit connected between the first memory segment and the third memory segment via several word lines connected to a second decoder. Device according to claim 1, wherein each memory segment has multiple eFuse memory cells. Device according to claim 2, wherein each of the eFuse memory cells comprises an arrangement of two transistors and a resistor (2T / 1R arrangement). Device according to claim 2, wherein each of the eFuse memory cells comprises an arrangement of a transistor and a resistor (1T / 1R arrangement). Device according to one of the preceding claims, wherein the first transmission gate and the third transmission gate are two sections of a single transmission gate. Device according to one of the preceding claims, wherein the intermediate amplifier circuit comprises a two-stage inverter with a first stage comprising a PMOS and an NMOS transistor and a second stage comprising a PMOS and an NMOS transistor. A storage array comprising: several word lines; several bit lines; several memory cells, each of the several memory cells being connected to a corresponding one of the several word lines and to a corresponding one of the several bit lines; and several intermediate amplifiers arranged along the several word lines such that each of the several memory cells is separated from an adjacent one of the several memory cells along its associated word line by at least one of the several intermediate amplifiers. Storage array according to claim 7, further comprising a word line decoder connected to the multiple word lines and configured to shift a voltage level of the word lines. Storage array according to claim 7 or 8, further comprising a bit line decoder connected to the multiple bit lines and configured to shift a voltage level of the bit lines. Storage array according to one of claims 7 to 9, wherein the storage array has multiple storage segments, each storage segment of the multiple storage segments having a subset of the multiple storage cells. Storage array according to claim 10, wherein each of the multiple storage segments has more than one pair of the multiple intermediate amplifiers. Storage array according to one of claims 7 to 11, wherein each of the multiple intermediate amplifiers is selected from the group consisting of: a standard threshold voltage intermediate amplifier, a low threshold voltage intermediate amplifier, a high threshold voltage intermediate amplifier and a mixed threshold voltage intermediate amplifier. Memory array according to one of claims 7 to 12, wherein each of the multiple memory cells is a 2T(NMOS)1R memory cell or a 2T(PMOS)1R memory cell. Storage array according to one of claims 7 to 13, wherein the multiple intermediate amplifiers each have a two-stage inverter with a first stage comprising a PMOS and an NMOS transistor and a second stage comprising a PMOS and an NMOS transistor. A method comprising: outputting a time-varying voltage signal to several word lines via a word line decoder; outputting a time-varying voltage signal to several bit lines via a bit line decoder; receiving, at each of several memory cells, the time-varying voltage belonging to one of the several word lines and the time-varying voltage belonging to one of the several bit lines; and amplifying the time-varying voltage on each of the several word lines at at least one intermediate amplifier, wherein the at least one intermediate amplifier is arranged along each of the several word lines such that each of the several memory cells is separated from an adjacent of the several memory cells along its associated word line by the at least one intermediate amplifier. The method of claim 15, wherein a memory segment comprises a subset of the multiple memory cells of a memory array with multiple memory segments, and wherein a corresponding time-varying voltage signal is provided to each of the multiple memory segments for its corresponding multiple bit lines and its corresponding multiple word lines. Method according to claim 15 or 16, wherein the amplification comprises arranging multiple intermediate amplifiers along each of the multiple word lines. Method according to any one of claims 15 to 17, wherein the at least one intermediate amplifier is selected from the group consisting of: a standard threshold voltage intermediate amplifier, a low threshold voltage intermediate amplifier, a high threshold voltage intermediate amplifier and a mixed threshold voltage intermediate amplifier. Method according to any one of claims 15 to 18, wherein each of the multiple memory cells is a 2T(NMOS)1R memory cell or a 2T(PMOS)1R memory cell. Method according to one of claims 15 to 19, wherein the at least one intermediate amplifier comprises a two-stage inverter with a first stage comprising a PMOS and an NMOS transistor and a second stage comprising a PMOS and an NMOS transistor.

Images