Terminal protection structure for high voltage power devices and method of making same

Abstract

The application provides a terminal protection structure and a preparation method thereof, and a high-voltage power device. The terminal protection structure comprises a substrate of a first conductive type, an insulating layer, metal field plates and a protection layer. Two or more heavily doped terminal rings of a second conductive type are formed in the substrate. The insulating layer is located on the surface of the substrate. One end of the metal field plate penetrates through the insulating layer and is connected to the two terminal rings on the outermost side one by one. The other end of the metal field plate extends to the upper side of the insulating layer. The metal field plates are insulated from each other. The protection layer is located on the insulating layer and the metal field plates. The preparation method of the terminal protection structure for the high-voltage power device provided by the application only needs to use four photoetching plates for four times of photoetching, compared with the prior art which needs to use six photoetching plates for six times of photoetching. The application can greatly simplify the process steps, reduce the device preparation cost and improve the process yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a termination protection structure for high-voltage power devices and its preparation method, as well as a high-voltage power device based on the termination protection structure. Background Technology

[0002] A fundamental requirement for power semiconductor devices is their ability to operate under high voltage and high current. Due to their limited size, power devices require wafer dicing for chip packaging. For power devices, dicing through a high-voltage PN junction can lead to a decrease in breakdown voltage and stability. To address this, termination protection technology is typically employed at the device boundaries to improve the breakdown voltage and ensure the chip can operate normally under high voltage.

[0003] For high-voltage semiconductor power devices, especially those above 3000V, the terminal design presents significant challenges. For instance, the terminal design of general high-voltage devices typically employs either a simple planar junction, but the breakdown voltage of this structure is only about 50% of that of a parallel planar junction, resulting in extremely low terminal utilization efficiency. Another approach is to improve the terminal utilization rate, achieving a breakdown voltage of over 90% of that of a parallel planar junction. However, this approach involves overly complex manufacturing processes, leading to higher manufacturing costs and poor stability and reliability.

[0004] Existing device termination technologies primarily involve forming a "PN field-limiting ring" by performing N-type and P-type doping in the termination region, and then depositing polysilicon and metal as field plates on the "PN field-limiting ring." The main steps of these existing technologies include:

[0005] Step 1: The first photolithography is performed on the N-type substrate under the action of the first photolithography plate, followed by N-type doping;

[0006] Step 2: After a second photolithography under the action of the second photolithography plate, P-type doping is performed. Steps 1 and 2 form a "PN field confinement ring".

[0007] Step 3: After depositing polycrystalline silicon, a third photolithography etching is performed under the action of the third photolithography plate to form a polycrystalline field plate;

[0008] Step 4: After depositing a thick oxide layer, a fourth photolithography etching is performed under the action of the fourth photolithography plate to form a protective layer for the metal field plate.

[0009] Step 5: After the fifth photolithography process under the action of the fifth photolithography plate, through-hole etching is performed;

[0010] Step 6: After depositing the metal layer, a sixth photolithography etching is performed under the action of the sixth photolithography plate to form the metal field plate;

[0011] Step 7: Finally, deposit a layer of polyimide as a protective layer.

[0012] As can be seen, existing technologies require multiple photolithography etching processes, which are overly complex. Besides resulting in high costs, low efficiency, and long wafer fabrication cycles, these processes, especially thin-film deposition, easily introduce electrical charges. For high-voltage power devices, due to the high operating voltage, the charges within the device will accumulate in large quantities on the device surface under the influence of high voltage and strong electric fields, easily causing various electrical failures and leading to a decrease in device reliability. Summary of the Invention

[0013] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a terminal protection structure for high-voltage power devices and its preparation method, which solves the problems of the prior art device terminal technology mainly involves N-type doping and P-type doping in the terminal region, which are complex processes, resulting in high production costs and low production efficiency. In addition, the process introduces charges, which can easily lead to electrical failure of the device and reduce device reliability.

[0014] To achieve the above and other related objectives, the present invention provides a method for fabricating a termination protection structure for high-voltage power devices, comprising the following steps:

[0015] A substrate of a first conductivity type is provided, and a first insulating layer is formed on the substrate;

[0016] The first insulating layer is photolithographically etched by the first photolithography plate to form two or more spaced first through holes in the first insulating layer, the first through holes exposing the substrate;

[0017] Ion implantation and annealing are performed on the substrate below the first via to form two or more heavily doped second conductivity type terminal rings spaced apart in the substrate.

[0018] Metal field plates are formed, with one end of each of the two metal field plates connected to the two outermost terminal rings in a one-to-one correspondence, and the other end extending towards each other above the first insulating layer, with each metal field plate being mutually insulated;

[0019] A protective layer is formed on the metal field plate and the first insulating layer.

[0020] Optionally, after forming the terminal ring but before forming the protective layer, the steps include:

[0021] A second insulating layer is formed on the first insulating layer, the second insulating layer fills the first through hole and is located on the surface of the first insulating layer;

[0022] Under the action of the second photolithography plate, the second insulating layer is photolithographically etched to form a field plate passivation layer. The field plate passivation layer is located on the gap surface of two adjacent terminal rings and extends to a portion of the surface of the two adjacent terminal rings.

[0023] Photolithography is performed under the action of the third photolithography plate to form a second through hole that exposes the two outermost terminal rings;

[0024] A metal layer is formed, which fills the second via and extends to the surface of the field plate passivation layer;

[0025] Under the action of the fourth photolithography plate, the metal layer is photolithographically etched to form the metal field plate.

[0026] Optionally, the lateral dimension of the terminal ring is 20μm-60μm.

[0027] Optionally, when there are two terminal rings, the distance between the two terminal rings is 100μm-200μm; when there are more than two terminal rings, the distance between the two adjacent outermost terminal rings is 100μm-200μm, and the distance between the other two adjacent terminal rings is 10μm-50μm.

[0028] Optionally, the minimum spacing between adjacent metal field plates in the lateral direction is 100μm-300μm.

[0029] Optionally, the terminal ring is formed by boron ion implantation, wherein the implantation energy is 40–150 keV and the implantation dose is 1 × 10⁻⁶. 14 ~8×10 15 .

[0030] Optionally, the high-voltage power device is an ultra-high-voltage power device with a voltage of 3000V or higher.

[0031] Optionally, the thickness of the second insulating layer is greater than zero and less than or equal to 10 μm.

[0032] Optionally, the first conductivity type is N-type and the second conductivity type is P-type.

[0033] Optionally, the substrate comprises a lightly doped silicon substrate.

[0034] Optionally, the first insulating layer and the second insulating layer comprise silicon oxide layers, and the protective layer comprises a polyimide layer.

[0035] The present invention also provides a termination protection structure for high-voltage power devices, comprising: a substrate of a first conductivity type, an insulating layer, a metal field plate, and a protective layer; two or more heavily doped termination rings of a second conductivity type are formed in the substrate at intervals; the insulating layer is located on the surface of the substrate; one end of the metal field plate penetrates the insulating layer and is connected to the two outermost termination rings in a one-to-one correspondence; the other end extends towards each other above the insulating layer; the metal field plates are mutually insulated; and the protective layer is located on the insulating layer and the metal field plate.

[0036] Optionally, the first conductivity type is N-type and the second conductivity type is P-type.

[0037] Optionally, the lateral dimension of the terminal ring is 20μm-60μm.

[0038] Optionally, when there are two terminal rings, the distance between the two terminal rings is 100μm-200μm; when there are more than two terminal rings, the distance between the two adjacent outermost terminal rings is 100μm-200μm, and the distance between the other two adjacent terminal rings is 10μm-50μm.

[0039] Optionally, the minimum spacing between adjacent metal field plates in the lateral direction is 100μm-300μm.

[0040] Optionally, the terminal ring is formed by boron ion implantation, wherein the implantation energy is 40–150 keV and the implantation dose is 1 × 10⁻⁶. 14 ~8×10 15 .

[0041] Optionally, the high-voltage power device is an ultra-high-voltage power device with a voltage of 3000V or higher.

[0042] Optionally, the substrate comprises a lightly doped silicon substrate.

[0043] Optionally, the insulating layer includes a silicon oxide layer.

[0044] Optionally, the protective layer includes a polyimide layer.

[0045] The present invention also provides a high-voltage power device, the high-voltage power device including the terminal protection structure as described in any of the above embodiments.

[0046] As described above, the terminal protection structure for high-voltage power devices and its fabrication method of the present invention have the following beneficial effects: The fabrication method of the terminal protection structure for high-voltage power devices provided by the present invention requires at most four photolithography plates for four photolithography etchings, compared with the prior art which requires at least six photolithography plates for six photolithography etchings. The present invention can greatly simplify the process steps, help reduce device fabrication costs and improve process yield. Attached Figure Description

[0047] Figure 1-5 The diagram shows an exemplary structural schematic of the fabrication method for the terminal protection structure of a high-voltage power device provided by the present invention, presented in each step of the fabrication process.

[0048] Component designation explanation

[0049] 11 Substrate

[0050] 12 Terminal Ring

[0051] 13 First Insulation Layer

[0052] 131 First Through Hole

[0053] 14 Second Insulation Layer

[0054] 141 Second Through Hole

[0055] 142 Field plate passivation layer

[0056] 15 metal field plates

[0057] 16 protective layers Detailed Implementation

[0058] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0059] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0060] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0062] Please see Figures 1 to 5 .

[0063] This invention provides a method for fabricating a termination protection structure for high-voltage power devices, comprising the following steps:

[0064] S1: A substrate 11 of a first conductivity type is provided, and a first insulating layer 13 is formed on the substrate 11; for example, the first conductivity type is N-type, and the second conductivity type is P-type accordingly. The substrate 11 is, for example, a phosphorus-doped silicon substrate 11, and the substrate 11 is typically lightly doped. In other examples, the substrate 11 may also be a composite structure including a silicon substrate and an epitaxial layer located on the silicon substrate. In this case, the subsequent termination ring 12 is formed in the epitaxial layer. The material and formation method of the first insulating layer 13 depend on the material of the substrate 11. For example, when the substrate 11 is a lightly doped silicon substrate, the first insulating layer 13 is preferably a silicon dioxide layer, and is preferably formed by thermal oxidation. The thickness of the first insulating layer 13 formed by thermal oxidation is preferably 200 angstroms to 500 angstroms. Of course, in other examples, the first insulating layer 13 may also be formed by chemical vapor deposition. However, using thermal oxidation not only shortens the preparation time of the first insulating layer 13, but also makes the formed first insulating layer 13 easier to etch in subsequent etching processes.

[0065] S2: The first insulating layer 13 is photolithographically etched using a first photolithography plate to form two or more spaced first vias 131 in the first insulating layer 13. The first vias 131 expose the substrate 11. The spacing of the first vias 131 determines the spacing between the terminal rings 12. Therefore, the spacing between the two outermost adjacent first vias 131 is usually greater than the spacing between adjacent first vias 131 at other locations. It should be noted that the "two outermost adjacent first vias 131" refers to the two first vias 131 that are farthest and second farthest from the device working area (i.e., the active area). The structure obtained after this step is as follows: Figure 1 As shown;

[0066] S3: Ion implantation and annealing are performed on the substrate 11 below the first via 131 to form two or more heavily doped second conductivity type terminal rings 12 spaced apart within the substrate 11. The formed n terminal rings 12 are, for example, P-type rings. These P-type rings can be defined sequentially as R1 to Rn along the direction away from the device working area. The R1 terminal ring 12 is closest to the device working area, while the two outermost Rn-1 terminal rings 12 and Rn terminal rings 12 are farther from the device working area. The width of each terminal ring 12 is defined as Wn, and the distance between the two outermost adjacent terminal rings 12 (Rn-1 and Rn) is defined as Sn-1, where n>1 and is an integer. The dimensions of each terminal ring 12 are preferably the same, but the distance between the two outermost adjacent terminal rings 12 (terminal rings 12Rn-1 and Rn) is preferably greater than the distance between other adjacent terminal rings 12. The structure obtained after this step is as follows: Figure 2 As shown;

[0067] S4: Form metal field plates 15, with one end of each of the two metal field plates 15 connected to the two outermost terminal rings 12 in a one-to-one correspondence, and the other end extending towards each other above the first insulating layer 13. Each metal field plate 15 is insulated from the other. By setting metal field plates that are electrically connected to the outermost terminal rings, the electric field is pulled to the periphery of the device, thereby avoiding breakdown in the device's working area and improving the device's withstand voltage performance.

[0068] S5: Form a protective layer 16, which is located on the metal field plate 15 and the first insulating layer 13. The forming process of the protective layer depends on the material of the protective layer. For example, when the protective layer is a polyimide layer, the method for forming the protective layer can be spin coating.

[0069] It should be noted that if the first insulating layer 13 is relatively thick, after photolithography etching, the remaining first insulating layer 13 can still ensure that the surface of the subsequently formed metal field plate 15 and the substrate 11 does not contact. In this case, it is not necessary to form an additional insulating material between the metal field plate 15 and the substrate 11. For example, if the first insulating layer 13 is a composite structure layer using silicon oxide and silicon nitride, it is not necessary to form an additional insulating material layer after forming the terminal ring 12.

[0070] However, in one example, to improve etching efficiency and ensure ion implantation depth, the thickness of the first insulating layer 13 is relatively small (e.g., within 500 angstroms). Therefore, to ensure electrical isolation between the subsequent metal field plate 15 and the substrate 11, as an example, a step is included after forming the terminal ring 12 and before forming the protective layer 16.

[0071] A second insulating layer 14 is formed on the first insulating layer 13, the second insulating layer 14 filling the first through-hole 131 and extending over the surface of the first insulating layer 13; the material of the second insulating layer 14 is preferably the same as or has similar properties to the material of the first insulating layer 13 to minimize interlayer stress, for example, the first insulating layer 13 is a silicon oxide layer, and the second insulating layer 14 is also a silicon oxide layer; of course, in other examples, the materials of the first insulating layer 13 and the second insulating layer 14 may be different, for example, the second insulating layer 14 is a silicon oxynitride layer; the structure obtained after this step is as follows. Figure 3 As shown;

[0072] Under the action of the second photolithography plate, the second insulating layer 14 is photolithographically etched to form a field plate passivation layer 142. The field plate passivation layer 142 is located on the gap surface of the two outermost adjacent terminal rings 12 and extends to a portion of the surface of the two adjacent terminal rings 12. The structure obtained after this step is as follows: Figure 4 As shown; the thickness d of the field plate passivation layer 142 is determined by the thickness of the second insulating layer 14, and this thickness has a significant impact on the withstand voltage performance of the device. Preferably, the thickness of the second insulating layer 14, that is, the thickness d of the field plate passivation layer 142 (which is also the vertical distance between the metal field plate 15 and the first insulating layer 13), is greater than zero and less than or equal to 10 μm (in fact, the structure without the field plate passivation layer 142 can also be considered as having a thickness of zero, so the thickness of the field plate passivation layer 142 can be considered to be 0-10 μm).

[0073] Photolithography is performed under the action of a third photolithography plate to form second vias 141 (in the second insulating layer 14) exposing the two outermost terminal rings 12 (i.e., second vias 141 are etched above the Rn-1 terminal ring 12 and the Rn terminal ring 12 shown in the figure). The second vias 141 are located on opposite sides of the field plate passivation layer 142. The planar dimensions of the second vias 141 are typically smaller than the planar dimensions of the terminal rings 12 to ensure that the metal (i.e., the metal field plate 15) subsequently filled in the second vias 141 makes electrical contact with the terminal rings 12 and does not overflow to other structural surfaces; the structure obtained after this step is as follows. Figure 4 As shown;

[0074] A metal layer is formed using a process including but not limited to sputtering. The metal layer fills the second via 141 and extends to the surface of the field plate passivation layer 142. The metal layer includes, but is not limited to, an aluminum layer, a copper layer, or an alloy layer. Of course, in this step, the formed metal layer usually extends to the entire surface of the device, that is, to the exposed first insulating layer 13, the terminating ring 12, and the gap surface between the terminating ring 12.

[0075] Under the action of the fourth photolithography plate, the metal layer is photolithographically etched to form the metal field plate 15. One end of the metal field plate 15 is located in the aforementioned second through hole 141 and contacts the terminal ring 12, while the other end extends towards the passivation layer 142 of the field plate. The structure obtained after this step is as follows: Figure 5 As shown.

[0076] As can be seen, the method for fabricating the terminal protection structure for high-voltage power devices provided by the present invention requires at most four photolithography plates for four photolithography etching processes. Compared with the prior art, which requires at least six photolithography plates for six photolithography etching processes, the present invention can greatly simplify the process steps, help reduce device fabrication costs and improve process yield.

[0077] Through extensive experimentation, the inventors discovered that, in order to ensure high device performance while minimizing manufacturing complexity, the lateral dimension Wn of the terminating ring 12 is preferably 20μm-60μm (in this embodiment, unless otherwise specified, all descriptions involving numerical ranges include endpoint values), for example, 20μm, 30μm, 40μm, 50μm, 60μm, or any value within this range, more preferably 30μm-40μm; when there are two terminating rings 12, the spacing between the two terminating rings 12 is preferably 100μm-200μm; when the number of terminating rings 12... When there are more than two, the spacing Sn-1 between the two outermost adjacent terminal rings 12 is preferably 100μm-200μm (e.g., 100, 120, 130, ... 200 or any value within this range, more preferably 120-150μm), while the spacing between other adjacent terminal rings 12 is preferably 10μm-50μm, e.g., 10, 20, 30, ... 50 or any value within this range, more preferably 20-30μm; that is, the spacing between the two outermost adjacent terminal rings 12 is greater than the spacing between adjacent terminal rings at other positions. Generally, the more terminal rings 12 there are, the better the withstand voltage performance of the device. However, considering device size and manufacturing process, the number of terminal rings is preferably no more than 10.

[0078] As an example, the minimum horizontal spacing 'a' between adjacent metal field plates 15 is preferably 100μm-300μm, for example, 100, 110, 120, ..., 300 or any value within this range, more preferably 150μm-200μm. It should be noted that, since the metal field plates 15 themselves are not regular shapes, the spacing between adjacent metal field plates 15 at different positions is not entirely consistent. For example, the spacing at the bottom of two adjacent metal field plates 15 is essentially the spacing between two adjacent second through holes 141. Two adjacent metal field plates 15 extend onto the same field plate passivation layer 142, and the spacing between these two metal field plates 15 extending onto the same field plate passivation layer 142 is the minimum horizontal spacing between adjacent metal field plates 15.

[0079] In one example, the terminal ring 12 is formed by boron ion implantation, wherein the implantation energy is 40–150 keV and the implantation dose is 1 × 10⁻⁶. 14 ~8×10 15 This ensures that the terminal protection structure has excellent high-voltage resistance.

[0080] The method for preparing the terminal protection structure for high-voltage power devices provided in this embodiment can be applied to the preparation of various types of devices, but is particularly suitable for the preparation of terminal protection structures for ultra-high voltage power devices above 3000V.

[0081] In one example, the protective layer 16 is preferably a polyimide layer. Of course, in other examples, the protective layer 16 can also be an organic material layer such as an epoxy resin layer, or an inorganic material layer such as a silicon oxide layer; there is no strict limitation on this. However, using a polyimide layer allows for better compatibility with subsequent packaging processes. The thickness of the protective layer 16 is not strictly limited, as long as it ensures that it covers the metal field plate 15.

[0082] like Figure 5 As shown, the present invention also provides a termination protection structure for high-voltage power devices. This termination protection structure can be fabricated based on the preparation method described in any of the foregoing schemes; therefore, the foregoing description of the preparation method of the termination protection structure is incorporated herein by reference in its entirety. The termination protection structure for high-voltage power devices includes: a substrate 11 of a first conductivity type, an insulating layer, a metal field plate 15, and a protective layer 16; two or more heavily doped termination rings of a second conductivity type are formed within the substrate 11 at intervals; the insulating layer is located on the surface of the substrate 11; one end of the metal field plate 15 penetrates the insulating layer until it is connected to the two outermost termination rings 12 in a one-to-one correspondence, and the other end extends towards each other above the insulating layer; the metal field plates 15 are mutually insulated; the protective layer 16 is located on the insulating layer and the metal field plate 15.

[0083] It should be noted that the insulating layer can be a single-layer structure, or as described above, it can be composed of a first insulating layer 13 and a field plate passivation layer 142. That is, the thickness of the field plate passivation layer 142 can be zero or greater than zero, and preferably less than or equal to 10 μm. The material of the insulating layer is preferably a silicon oxide layer, but it is not limited to this; for example, it can also be a silicon oxynitride layer.

[0084] In a preferred example, the first conductivity type is N-type and the second conductivity type is P-type. For example, the substrate 11 is a phosphorus-doped substrate 11, and the substrate 11 is typically lightly doped, while the N-type active region is a heavily doped arsenic-doped region.

[0085] In a preferred example, the lateral dimension of the terminal ring 12 is 20μm-60μm.

[0086] In a preferred example, when there are two terminating rings, the spacing between the two terminating rings is 100μm-200μm; when there are more than two terminating rings, the spacing between the two outermost adjacent terminating rings is 100μm-200μm, and the spacing between the other adjacent terminating rings is 10μm-50μm.

[0087] In a preferred example, the minimum lateral spacing of adjacent metal field plates 15 is 100μm-300μm, which typically refers to the horizontal spacing between two metal field plates 15 extending onto the same field passivation layer 142.

[0088] In a preferred example, the terminal ring 12 is formed by boron ion implantation, wherein the implantation energy is 40–150 keV and the implantation dose is 1 × 10⁻⁶. 14 ~8×10 15 .

[0089] In a preferred example, the high-voltage power device is an ultra-high-voltage power device of 3000V or above.

[0090] As an example, the protective layer 16 is preferably a polyimide layer, but is not limited to it. For example, it can also be other organic material layers such as an epoxy resin layer, or inorganic material layers such as a silicon oxide layer.

[0091] The metal plate 16 can be, for example, an aluminum plate, a copper plate, or an alloy plate.

[0092] For a more detailed description of the terminal protection structure for high-voltage power devices, please refer to the foregoing content; for the sake of brevity, it will not be repeated here.

[0093] This invention also provides a high-voltage power device, which includes a termination protection structure as described in any of the foregoing embodiments. The termination protection structure is typically located around the active region of the high-voltage power device, or in other words, the termination protection structure surrounds the active region of the device, meaning the active region of the device is adjacent to the aforementioned R1 termination ring. Further details regarding the termination protection structure can be found in the foregoing description, and will not be repeated here for the sake of brevity. Due to the use of the aforementioned termination protection structure, the high-voltage power device provided by this invention can withstand high voltages, such as those exceeding 3000V, and the manufacturing method is simple, which helps to reduce device costs.

[0094] In summary, this invention provides a termination protection structure for high-voltage power devices, a method for fabricating the same, and a high-voltage power device. The termination protection structure for high-voltage power devices includes: a substrate of a first conductivity type, an insulating layer, a metal field plate, and a protective layer; two or more heavily doped termination rings of a second conductivity type are formed within the substrate at intervals; the insulating layer is located on the surface of the substrate; one end of each metal field plate penetrates the insulating layer and connects to the two outermost termination rings; the other end extends towards each other above the insulating layer; the metal field plates are mutually insulated; and the protective layer is located on the insulating layer and the metal field plates. The method for fabricating the termination protection structure for high-voltage power devices provided by this invention requires at most four photolithography plates for four photolithography etching processes, compared to at least six photolithography plates for six photolithography etching processes in the prior art. This invention significantly simplifies the process steps, helps reduce device fabrication costs, and improves process yield.

[0095] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a terminal protection structure for high-voltage power devices, characterized in that, The high-voltage power device is an ultra-high-voltage power device of 3000V or above, and includes the following steps: A substrate of a first conductivity type is provided, and a first insulating layer is formed on the substrate; The first insulating layer is photolithographically etched by the first photolithography plate to form two or more spaced first through holes in the first insulating layer, the first through holes exposing the substrate; Ion implantation and annealing are performed on the substrate below the first via to form two or more heavily doped second conductivity type terminal rings spaced apart within the substrate. The lateral dimension of the terminal rings is 20μm-60μm. When there are two terminal rings, the distance between the two terminal rings is 100μm-200μm. When there are more than two terminal rings, the distance between the two outermost adjacent terminal rings is 100μm-200μm, and the distance between the other adjacent terminal rings is 10μm-50μm. Metal field plates are formed, with one end of each metal field plate connected to the two outermost adjacent terminal rings in a corresponding manner, and the other end extending towards each other above the first insulating layer. Each metal field plate is insulated from the other, and the minimum horizontal spacing between adjacent metal field plates is 100μm-300μm. A protective layer is formed on the metal field plate and the first insulating layer.

2. The method for preparing a terminal protection structure for high-voltage power devices according to claim 1, characterized in that, After the terminal ring is formed, the steps before forming the protective layer include: A second insulating layer is formed on the first insulating layer, the second insulating layer fills the first through hole and is located on the surface of the first insulating layer; Under the action of the second photolithography plate, the second insulating layer is photolithographically etched to form a field plate passivation layer, which extends from the gap surface of the two outermost terminal rings to a portion of the surface of the two terminal rings. Photolithography is performed under the action of the third photolithography plate to form a second through hole that exposes the two outermost terminal rings; A metal layer is formed, which fills the second via and extends to the surface of the field plate passivation layer; Under the action of the fourth photolithography plate, the metal layer is photolithographically etched to form the metal field plate.

3. The method for preparing a terminal protection structure for high-voltage power devices according to claim 2, characterized in that, The thickness of the second insulating layer is greater than zero and less than or equal to 10 μm.

4. The method for preparing a terminal protection structure for high-voltage power devices according to claim 2, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; the substrate includes a lightly doped silicon substrate, the first insulating layer and the second insulating layer include silicon oxide layers, and the protective layer includes a polyimide layer.

5. The method for preparing a terminal protection structure for high-voltage power devices according to claim 1, characterized in that, The terminal ring is formed by boron ion implantation, wherein the implantation energy is 40~150 keV and the implantation dose is 1×10⁻⁶. 14 ~8×10 15 .

6. A termination protection structure for high-voltage power devices, characterized in that, The high-voltage power device is an ultra-high-voltage power device of 3000V or above, comprising: a substrate of a first conductivity type, an insulating layer, a metal field plate, and a protective layer; two or more heavily doped terminal rings of a second conductivity type are formed in the substrate at intervals; the insulating layer is located on the surface of the substrate; one end of the metal field plate penetrates the insulating layer and connects to the two outermost terminal rings one-to-one; the other end extends towards each other above the insulating layer; the metal field plates are mutually insulated; the lateral dimension of the terminal ring is 20μm-60μm; when there are two terminal rings, the distance between the two terminal rings is 100μm-200μm; when there are more than two terminal rings, the distance between the two outermost adjacent terminal rings is 100μm-200μm, and the distance between the other two adjacent terminal rings is 10μm-50μm; the minimum lateral spacing between adjacent metal field plates is 100μm-300μm; the protective layer is located on the insulating layer and the metal field plate.

7. The terminal protection structure for high-voltage power devices according to claim 6, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; the substrate includes a lightly doped silicon substrate, the insulating layer includes a silicon oxide layer, and the protective layer includes a polyimide layer.

8. The termination protection structure for high-voltage power devices according to claim 6, characterized in that, The terminal ring is formed by boron ion implantation, wherein the implantation energy is 40~150 keV and the implantation dose is 1×10⁻⁶. 14 ~8×10 15 .

9. A high-voltage power device, characterized in that, The high-voltage power device includes the terminal protection structure as described in any one of claims 6-8.

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