A germanium-silicon heterojunction bipolar transistor and a method of fabricating the same

Abstract

The application provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. The application adopts a pseudo buried layer, a wedge-shaped base contact surface and a nickel-silicon process, forms a pseudo buried layer in a substrate, forms a base on a front surface of the substrate, and forms a wedge-shaped dielectric structure as a side groove on a first base region. Ion implantation is performed by using the wedge-shaped dielectric structure as a mask, a collector is formed at the bottom of the first base region and the top of the pseudo buried layer, an emitter is formed in the dielectric structure as a side groove, and a metal layer with ohmic contact is formed on the emitter, the base and the collector by using the nickel-silicon process. The first base region and the second base region are connected by using the wedge shape, the contact area is increased, the base resistance is reduced, the formation of the buried layer is reduced by forming the pseudo buried layer in the substrate and the nickel-silicon process, the demand for heat budget is reduced, and the process reusability and reliability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronic integrated circuit manufacturing, and in particular to a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] In an analog circuit, the germanium-silicon heterojunction bipolar transistor is applied to a high-frequency high-speed scene. As the germanium-silicon material is used as the base region of the transistor, the germanium-silicon heterojunction bipolar transistor has higher cutoff frequency, greater current gain and lower noise than the conventional silicon transistor. The germanium-silicon heterojunction bipolar transistor has good compatibility with the silicon process, and can be mixed and integrated with the CMOS (Complementary Metal-Oxide Semiconductor) process to form a germanium-silicon CMOS process, so that the high-frequency characteristics of the heterojunction bipolar transistor and the low-power consumption and high-integration of the CMOS can coexist. However, in the conventional germanium-silicon CMOS process, in order to manufacture a high-performance germanium-silicon heterojunction bipolar transistor, a buried layer needs to be made and an epitaxial layer needs to be grown on the buried layer to reduce the resistance of the collector. The buried layer has a relatively high doping concentration and needs high-temperature annealing for impurity diffusion and impurity activation, and an additional thermal process is introduced in the manufacturing process flow. In order to prevent leakage between devices and maintain the stability of the performance of the devices, a deep trench isolation structure needs to be introduced to achieve electrical isolation between devices, and the process flow needs to be adjusted and optimized. In the prior art, the germanium-silicon material needs to be introduced into the CMOS process, which increases the manufacturing cost and complicates the process flow.

[0003] Therefore, how to control the thermal process in the process of combining the germanium-silicon heterojunction bipolar transistor with the CMOS process, while reducing the complexity of the process, is a technical problem that needs to be solved at present. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a technical solution of a germanium-silicon heterojunction bipolar transistor. The present application provides a substrate, forms a pseudo-buried layer in the substrate, forms a first base region with a wedge-shaped side surface on the pseudo-buried layer, and realizes low-temperature integration with the base CMOS process by using a low-temperature nickel-silicon alloy process, so as to solve the above-mentioned technical problems.

[0005] To achieve the above object and other related objects, the technical solution provided by the present application is as follows.

[0006] A method for manufacturing a GeSi heterojunction bipolar transistor, comprising: providing a substrate, the substrate comprising opposite front and back surfaces, and a pseudo buried layer formed in the substrate; forming a composite sacrificial layer on the front surface of the substrate, etching the composite sacrificial layer to expose the substrate and obtain a first trench, the side surface of the first trench being wedge-shaped; forming a first base region in the first trench; forming a dielectric layer on the composite sacrificial layer and the first base region, etching the dielectric layer to expose a portion of the first base region and obtain a second trench, and forming a wedge-shaped dielectric structure on the side surface of the second trench; performing ion implantation with the wedge-shaped dielectric structure as a mask to form a collector region, the collector region being arranged at the bottom of the first base region and extending into the pseudo buried layer; forming an emitter structure in the second trench; removing the remaining composite sacrificial layer to expose the first base region, and forming a base connection structure and a second base region on the position of the composite sacrificial layer, the base connection structure being connected with the first base region; forming an emitter ohmic contact, a base ohmic contact and a collector ohmic contact.

[0007] Optionally, the step of forming the pseudo buried layer in the substrate comprises: forming a protection layer on the substrate; forming a mask layer on the protection layer, performing a patterning process on the mask layer to obtain a first mask; and performing ion implantation with the first mask as a mask to pass through the protection layer and form the pseudo buried layer in the substrate.

[0008] Optionally, after the pseudo buried layer is formed in the substrate, before the composite sacrificial layer is formed on the substrate, the method further comprises: removing the first mask and the protection layer.

[0009] Optionally, the step of forming the composite sacrificial layer on the front surface of the substrate comprises: forming a first sacrificial layer on the front surface of the substrate; forming a second sacrificial layer on the first sacrificial layer; and forming a third sacrificial layer on the second sacrificial layer.

[0010] Optionally, the step of etching the composite sacrificial layer to expose the substrate and obtain the first trench comprises: performing dry etching on the composite sacrificial layer, the dry etching stopping in the first sacrificial layer; performing wet etching on the composite sacrificial layer; and etching the exposed sacrificial layer by the wet etching to expose the substrate.

[0011] Optionally, along the direction from the first sacrificial layer to the third sacrificial layer, the distance between the side wall of the first trench and a reference center line first decreases and then increases.

[0012] Optionally, the step of forming the first base region in the first trench comprises: forming, in the first trench, a first buffer layer, a first epitaxial layer and a first cap layer in sequence along a direction from the first sacrificial layer to the third sacrificial layer, the first epitaxial layer being of a germanium-silicon material, the first buffer layer, the first epitaxial layer and the first cap layer constituting the first base region.

[0013] Optionally, the step of forming the emitter structure in the second trench comprises: forming an emitter material layer covering the remaining dielectric layer and filling the second trench; and removing the emitter material layer outside the second trench, the emitter material layer remaining in the second trench constituting the emitter structure.

[0014] Optionally, the step of forming the base structure at the position of the composite sacrificial layer comprises: forming, in sequence at the position of the composite sacrificial layer along a direction outward from the reference line center line, a base region connecting structure and a second base region, the base region connecting structure being connected to the first base region, the second base region being connected to the base region connecting structure, the base region connecting structure and the second base region constituting the first base region.

[0015] Optionally, the step of forming the emitter ohmic contact, the base ohmic contact and the collector ohmic contact comprises: forming a first metal layer covering at least the second base region and the emitter structure; etching the first metal layer to form the base ohmic contact on the second base region and the emitter ohmic contact on the emitter structure; and forming a second metal layer on the back surface of the substrate and etching the second metal layer to obtain the collector ohmic contact.

[0016] A germanium-silicon heterojunction bipolar transistor comprises: a substrate comprising opposite front and back surfaces, the substrate comprising a pseudo buried layer; a base disposed on the front surface of the substrate, the base comprising a first base region, a base connecting structure and a second base region, the first base region being disposed on the front surface of the substrate and contacting the pseudo buried layer, the base connecting structure being connected to the first base region, and the second base region being connected to the base connecting structure; a collector disposed in the substrate and contacting the first base region; and an emitter disposed on the first base region.

[0017] Optionally, the collector, the first base region and the emitter are disposed in sequence along a first direction, the first base region, the base connecting structure and the second base region are disposed in sequence along a second direction, the first direction being perpendicular to the substrate and pointing from the back surface of the substrate to the front surface of the substrate, and the second direction being parallel to the substrate and diverging from the reference center line to the periphery.

[0018] Optionally, a wedge-shaped dielectric structure is disposed between the emitter and the base, and a dielectric window is disposed in the wedge-shaped dielectric structure, the emitter contacts the first base region through the dielectric window, and the collector is in line with the dielectric window as viewed along the first direction.

[0019] Optionally, a base ohmic contact is disposed on the second base region, an emitter ohmic contact is disposed on the emitter, and a collector ohmic contact is disposed on the back surface of the substrate.

[0020] As described above, the germanium-silicon heterojunction bipolar transistor and the manufacturing method provided by the present application have at least the following beneficial effects:

[0021] A dummy buried layer is formed in a substrate, a composite sacrificial layer is formed on a front surface of the substrate and etched to obtain a first trench, a first base region is formed in the first trench, a contact surface of the first base region is wedge-shaped, a dielectric layer is formed on the composite sacrificial layer, the dielectric layer is etched to obtain a second trench, a side surface of the second trench forms a wedge-shaped dielectric structure, ion implantation is performed using the wedge-shaped dielectric structure as a mask to form a collector region, an emitter structure is formed in the second trench, the composite sacrificial layer is removed to expose the contact surface structure of the first base region, a base structure is formed at a position of the composite sacrificial layer, the base structure is in contact with the first base region, and an emitter ohmic contact, a base ohmic contact, and a collector ohmic contact are formed to complete the manufacturing of the germanium-silicon heterojunction bipolar transistor. The present application reduces the buried layer for the collector in the process by forming a dummy buried layer in the substrate, does not introduce an additional thermal process in the manufacturing process, saves the process cost, increases the contact area by using a bevel contact surface of the base region to reduce the base resistance, reduces the process complexity by not using a deep trench isolation structure, uses a low-temperature nickel-silicon process when forming the ohmic contact to further reduce the thermal budget requirement and does not affect the high-temperature process of the baseline CMOS process, and greatly improves the reusability and reliability of the process. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a step schematic diagram of the manufacturing method of the germanium-silicon heterojunction bipolar transistor in the embodiment of the present application;

[0023] Figures 2-10 is a process flow diagram of the manufacturing method of the germanium-silicon heterojunction bipolar transistor of the present application.

[0024] REFERENCE SIGNS:

[0025] 101 - substrate; 102 - shallow trench structure; 103 - silicon nitride film protective layer; 104 - photoresist mask layer; 105 - dummy buried layer; 106 - silicon dioxide / silicon nitride / silicon dioxide three-layer composite sacrificial layer; 107 - selective silicon epitaxial layer; 108 - carbon-doped germanium-silicon epitaxial layer; 109 - P-type cap layer; 110 - emitter and base wedge-shaped dielectric structure; 111 - collector; 112 - emitter; 113 - base connection structure; 114 - second base region; 115 - nickel-silicon alloy. DETAILED DESCRIPTION

[0026] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0027] It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can also be more complex. The structures, proportions and sizes shown in the diagrams attached to the specification are only used to cooperate with the content disclosed in the specification, so that those skilled in the art can understand and read, and do not define the limited conditions for implementing the present application, so they do not have technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0028] The inventors have found that in the germanium-silicon heterojunction bipolar transistor combined with the CMOS process in the prior art, in order to manufacture a high-performance germanium-silicon heterojunction bipolar transistor, a buried layer needs to be made and an epitaxial layer needs to be grown on the buried layer to reduce the resistance of the collector. Due to the process flow of adding the buried layer, high-temperature annealing process is needed to activate the buried layer, and the isolation problem between devices also needs to be considered, which to some extent needs to adjust and optimize the process flow of the existing germanium-silicon heterojunction bipolar transistor. Not only does it introduce an additional thermal process, but it also increases the complexity of the process and increases the manufacturing cost.

[0029] In order to solve the above problems, the application provides a technical scheme of a germanium-silicon heterojunction bipolar transistor, a substrate, opposite front and back surfaces are included in the substrate, a pseudo buried layer is formed in the substrate, a composite sacrificial layer is formed on the front surface of the substrate and etched to obtain a first groove, the side surface of the first groove is wedge-shaped, a first base region is formed in the first groove, a dielectric layer is formed on the first base region and etched to obtain a second groove, the side surface of the second groove forms a wedge-shaped dielectric structure; ion implantation is performed by taking the wedge-shaped dielectric structure as a mask to form a collector region, an emitter structure is formed in the second groove, the residual sacrificial layer is removed to expose the first base region, a base structure is formed at the position of the composite sacrificial layer, the base structure is connected with the first base region, and ohmic contacts of the emitter, the base and the collector are formed.The germanium-silicon heterojunction bipolar transistor provided by the application does not need to bury the collector, reduces the demand for high-temperature processes, avoids the leakage between devices, the side surface of the first base region is wedge-shaped, the contact area of the base region is increased, the resistance is reduced, the ohmic contacts of the emitter, the base and the collector are completed by using a low-temperature nickel-silicon alloy process, the demand for thermal budget of the process is reduced, and the complexity and cost of the process are reduced.

[0030] As shown in Figure 1 The application provides a manufacturing method of a germanium-silicon heterojunction bipolar transistor, which comprises the following steps:

[0031] S110, a substrate is provided, the substrate includes opposite front and back surfaces, and a pseudo buried layer is formed in the substrate;

[0032] S120, a composite sacrificial layer is formed on the front surface of the substrate, the composite sacrificial layer is etched to expose the substrate and obtain a first groove, and the side surface of the first groove is wedge-shaped;

[0033] S130, a first base region is formed in the first groove;

[0034] S140, a dielectric layer is formed on the composite sacrificial layer and the first base region, the dielectric layer is etched to expose part of the first base region and obtain a second groove, and a wedge-shaped dielectric structure is formed on the side surface of the second groove;

[0035] S150, ion implantation is performed by taking the wedge-shaped dielectric structure as a mask to form a collector region, the collector region is arranged at the bottom of the first base region and extends into the pseudo buried layer;

[0036] S160, an emitter structure is formed in the second groove;

[0037] S170, the residual composite sacrificial layer is removed to expose the first base region, and a base connection structure is formed at the position of the composite sacrificial layer and connected with the second base region, and the base connection structure is connected with the first base region;

[0038] S180, an emitter ohmic contact, a base ohmic contact and a collector ohmic contact are formed.

[0039] In detail, such as Figure 2 As shown, in step S110, the step of forming a pseudo buried layer in the substrate includes: manufacturing NMOS and PMOS transistors in the substrate according to the CMOS standard process, completing gate patterning, forming a shallow trench structure 102 in the substrate, forming a silicon nitride film protection layer 103 on the substrate, forming a photoresist buried layer 104 on the silicon nitride film protection layer 103, and patterning the photoresist buried layer 104 to obtain a first mask after exposure; and performing arsenic ion implantation using the first mask as a mask, wherein the implantation dose is not less than 3×10 15 cm -2 , passing through the silicon nitride thin film protection layer 103, forming a pseudo buried layer 105 in the substrate.

[0040] In more detail, the substrate may be at least a silicon wafer or a silicon wafer having an SOI (Silicon-On-Insulator) substrate.

[0041] In detail, such as Figure 3 As shown, between step S110 and step S120 , that is, after forming the pseudo buried layer on the substrate and before forming the composite sacrificial layer on the substrate, the method further includes: removing the first mask and the silicon nitride thin film protection layer 103 .

[0042] In detail, in step S120, the step of forming the composite sacrificial layer 106 on the front side of the substrate includes: forming a first sacrificial layer of silicon dioxide on the front side of the substrate; forming a second sacrificial layer of silicon nitride on the first sacrificial layer; and forming a third sacrificial layer of silicon dioxide on the second sacrificial layer.

[0043] In detail, such as Figure 4 As shown, in step S120, the step of etching the composite sacrificial layer 106 to expose the substrate and obtain the first groove includes: performing a first etching on the composite sacrificial layer 106, and the first etching stops in the first sacrificial layer silicon dioxide; performing a second etching on the composite sacrificial layer, and etching the sacrificial layer exposed by the first etching to expose the pseudo buried layer 105 formed in the substrate.

[0044] In more detail, when etching the composite sacrificial layer 106 , the first etching process adopts a dry etching process, and the second etching process adopts a wet etching process.

[0045] In more detail, Figure 4 As shown, the etching feature of the composite sacrificial layer is that, along the direction from the first sacrificial layer silicon dioxide to the third sacrificial layer silicon dioxide, the distance between the sidewall of the first trench and the reference center line first decreases and then increases.

[0046] In detail, such as Figure 5As shown, in step S130, the step of forming a first base region in the first trench includes: forming a first buffer layer selective silicon epitaxial layer 107, a first epitaxial layer being a carbon-doped silicon germanium epitaxial layer 108 and a first cap layer P-type cap layer 109 stacked in sequence in the first trench along the direction from the first sacrificial silicon dioxide layer to the third sacrificial silicon dioxide layer, the first buffer layer selective silicon epitaxial layer 107, the first epitaxial layer being a carbon-doped silicon germanium epitaxial layer 108 and the first cap layer P-type cap layer 109 constituting the first base region.

[0047] In detail, such as Figure 6 As shown, in step S140, the step of forming the second trench includes: depositing a dielectric silicon dioxide film on the composite sacrificial layer 106 and the first base region using a high-density plasma process, etching the dielectric silicon dioxide film to expose a portion of the first base region and obtain a second trench, and the dielectric silicon dioxide film deposited at the emitter window has conformal properties, so that a wedge-shaped dielectric structure 110 is formed on the side of the second trench. It should be noted that Figure 6 This is to better demonstrate the structure of the device and is not a proportional scale of the actual device structure. The actual structure is steeper and the side wall structure is more obvious.

[0048] In detail, such as Figure 6 As shown, in step S150 , the step of forming the collector region includes: performing SIC collector region ion implantation with the wedge-shaped dielectric structure 110 as a burial, and the collector region 111 is set at the bottom of the first base region and extends into the pseudo buried layer.

[0049] In detail, such as Figure 7 As shown, in step S160, the step of forming an emitter structure in the second trench includes: forming emitter material layer crystals, the emitter material layer crystals covering the remaining dielectric layer and filling the second trench; removing the emitter material layer crystals outside the second trench, and the remaining emitter material layer in the second trench constitutes the emitter structure.

[0050] In detail, such as Figure 8 As shown, in step S170 , the second sacrificial layer of silicon nitride and the third sacrificial layer of silicon dioxide of the remaining composite sacrificial layer are removed to expose the first base region, and the side surface of the first base region is wedge-shaped.

[0051] In detail, such as Figure 9 As shown, in step S170, the step of forming a base structure at the position of the first sacrificial layer silicon dioxide 106 of the composite sacrificial layer includes: forming a base region connection structure 113 and a second base region 115 in sequence at the position of the first sacrificial layer silicon dioxide 106 of the composite sacrificial layer along the center line of the reference line outward, the base region connection structure 113 is connected to the first base region, and the second base region 114 is connected to the base region connection structure 113.

[0052] In detail, such as Figure 10 As shown, in step S180, the steps of forming an emitter ohmic contact, a base ohmic contact and a collector ohmic contact include: forming a first metal layer of nickel-silicon alloy, the first metal layer of nickel-silicon alloy at least covering the second base region and the emitter structure 112; etching the first metal layer of nickel-silicon alloy to form a base ohmic contact 115 on the second base region, and forming an emitter ohmic contact 115 on the emitter structure; forming a second metal layer of nickel-silicon alloy on the back side of the substrate, and etching the second metal layer of nickel-silicon alloy to obtain a collector ohmic contact 115.

[0053] A germanium-silicon heterojunction bipolar transistor comprises: a substrate 101 comprising a front side and a back side arranged opposite to each other, a pseudo-buried layer 105 being provided in the substrate 101; a base arranged on the front side of the substrate 101, comprising a first base region, a base connection structure 113, and a second base region 114, wherein the first base region is arranged on the front side of the substrate and contacts the pseudo-buried layer 105, the base connection structure 113 is connected to the first base region, and the second base region 114 is connected to the base connection structure 113; a collector 111 is arranged in the substrate and contacts the first base region; and an emitter is arranged on the first base region.

[0054] In detail, such as Figure 10 As shown, the collector 111, the first base region and the emitter 112 are arranged in sequence along a first direction, and the first base region, the base connection structure 113 and the second base region 114 are arranged in sequence along a second direction. The first direction is perpendicular to the substrate 101 and points from the back side of the substrate 101 to the front side of the substrate 101. The second direction is parallel to the substrate 101 and diverges from the reference center line to the surrounding areas.

[0055] In detail, such as Figure 10 As shown, the wedge-shaped dielectric structure 110 is disposed between the emitter 112 and the base, and a dielectric window is disposed therein. The emitter 112 contacts the first base region through the dielectric window. When viewed along the first direction, the collector 112 is aligned with the dielectric window.

[0056] In detail, the base ohmic contact is provided on the second base region 114 ; the emitter ohmic contact is provided on the emitter 112 ; and the collector ohmic contact is provided on the back side of the substrate 101 .

[0057] The present application provides a germanium-silicon heterojunction bipolar transistor, which comprises a substrate, a first base region, a second base region, a collector, an emitter and a base structure, wherein the substrate is provided with a pseudo buried layer and a composite sacrificial layer on the front surface thereof; the first base region is formed in the first groove; the second base region is formed in the second groove; the collector is formed by ion implantation; the emitter is formed in the second groove; the base structure is formed by etching the residual composite sacrificial layer to expose the side surface of the wedge-shaped first base region; and the ohmic contact metal layer is formed on the emitter, the collector and the base by a nickel-silicon alloy process. Compared with the existing germanium-silicon CMOS process, the present application adopts a pseudo buried layer structure, the collector is formed by ion implantation with the wedge-shaped dielectric structure as a mask, the buried layer of the collector is not needed, the heat process caused by the buried layer oxidation process and high-temperature annealing is reduced, the resistance of the collector is reduced, the side surface of the first base region and the base connection structure is wedge-shaped, the contact area is increased, the base resistance is reduced, the deep trench isolation structure is abandoned, the process complexity is reduced, the low-temperature nickel-silicon process is adopted, the demand for heat budget is further reduced, the process flow is optimized without affecting the function of the transistor, the manufacturing cost is reduced, and the demand for heat budget is reduced to a certain extent.

[0058] The above examples only illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art can make modifications or changes to the above examples without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present application should be covered by the claims of the present application.

Claims

1. A method for manufacturing a silicon-germanium heterojunction bipolar transistor, characterized in that: include: Providing a substrate, the substrate comprising a front surface and a back surface arranged opposite to each other, and forming a pseudo buried layer in the substrate; forming a composite sacrificial layer on the front surface of the substrate, etching the composite sacrificial layer to expose the substrate and obtain a first trench, wherein the side surface of the first trench is wedge-shaped; forming a first base region in the first trench; forming a dielectric layer on the composite sacrificial layer and the first base region, etching the dielectric layer to expose a portion of the first base region and obtain a second trench, and forming a wedge-shaped dielectric structure on a side of the second trench; Using the wedge-shaped dielectric structure as a mask, ion implantation is performed to form a collector region, where the collector region is disposed at the bottom of the first base region and extends into the pseudo buried layer; forming an emitter structure in the second trench; removing the remaining composite sacrificial layer to expose the first base region, and forming a base region connection structure and a second base region at the location of the composite sacrificial layer, wherein the base region connection structure is connected to the first base region; An emitter ohmic contact, a base ohmic contact, and a collector ohmic contact are formed.

2. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein: The step of forming a pseudo buried layer in the substrate comprises: forming a protective layer on the substrate; forming a mask layer on the protective layer, and performing patterning on the mask layer to obtain a first mask; Using the first mask as a mask, ion implantation is performed to penetrate the protective layer and form the pseudo buried layer in the substrate.

3. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 2, wherein: After forming the pseudo buried layer on the substrate and before forming a composite sacrificial layer on the substrate, the method further includes: The first mask and the protection layer are removed.

4. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein: The step of forming a composite sacrificial layer on the front surface of the substrate comprises: forming a first sacrificial layer on the front surface of the substrate; forming a second sacrificial layer on the first sacrificial layer; A third sacrificial layer is formed on the second sacrificial layer.

5. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 4, wherein: The step of etching the composite sacrificial layer to expose the substrate and obtain the first trench includes: performing dry etching on the composite sacrificial layer, wherein the dry etching stops in the first sacrificial layer; The composite sacrificial layer is wet-etched, and the sacrificial layer exposed by the wet etching is etched to expose the substrate.

6. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 5, wherein: Along the direction from the first sacrificial layer to the third sacrificial layer, the distance between the sidewall of the first trench and the reference center line first decreases and then increases.

7. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 4, wherein: The step of forming a first base region in the first trench includes: Along the direction from the first sacrificial layer to the third sacrificial layer, a first buffer layer, a first epitaxial layer and a first cap layer are stacked in sequence in the first trench, the first epitaxial layer is made of germanium silicon, and the first buffer layer, the first epitaxial layer and the first cap layer constitute the first base region.

8. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 1, wherein: The step of forming an emitter structure in the second trench comprises: forming an emitter material layer, wherein the emitter material layer covers the remaining dielectric layer and fills the second trench; The emitter material layer outside the second trench is removed, and the emitter material layer remaining in the second trench constitutes the emitter structure.

9. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 6, wherein: The step of forming a base region connection structure and a second base region at the position of the composite sacrificial layer includes: A base region connection structure and a second base region are sequentially formed at the position of the composite sacrificial layer along the outward direction of the reference center line. The base region connection structure is connected to the first base region, and the second base region is connected to the base region connection structure.

10. The method for manufacturing a silicon-germanium heterojunction bipolar transistor according to claim 9, wherein: The steps of forming an emitter ohmic contact, a base ohmic contact and a collector ohmic contact include: forming a first metal layer, wherein the first metal layer at least covers the second base region and the emitter structure; Etching the first metal layer to form the base ohmic contact on the second base region and the emitter ohmic contact on the emitter structure; A second metal layer is formed on the back side of the substrate, and the second metal layer is etched to obtain the collector ohmic contact.

11. A germanium-silicon heterojunction bipolar transistor, characterized in that: include: A substrate, comprising a front surface and a back surface arranged opposite to each other, wherein a pseudo buried layer is provided in the substrate; a base, arranged on the front surface of the substrate, comprising a first base region, a base connection structure and a second base region, wherein the first base region is arranged on the front surface of the substrate and contacts the pseudo buried layer, the base connection structure is connected to the first base region, and the second base region is connected to the base connection structure; a collector electrode, disposed in the substrate and in contact with the first base region; an emitter, disposed on the first base region; Wherein, the base ohmic contact is provided on the second base region; an emitter ohmic contact, disposed on the emitter; The collector ohmic contact is arranged on the back side of the substrate.

12. The silicon-germanium heterojunction bipolar transistor according to claim 11, wherein: The collector, the first base region and the emitter are arranged in sequence along a first direction, and the first base region, the base connection structure and the second base region are arranged in sequence along a second direction. The first direction is perpendicular to the substrate and points from the back side of the substrate to the front side of the substrate. The second direction is parallel to the substrate and diverges from a reference center line to all sides.

13. The silicon-germanium heterojunction bipolar transistor according to claim 12, wherein: include: A wedge-shaped dielectric structure is arranged between the emitter and the base, and a dielectric window is provided therein. The emitter contacts the first base region through the dielectric window. When viewed along the first direction, the collector is aligned with the dielectric window.

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