Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first dielectric layer, a first conductive structure, a second conductive structure, a first via, a second via, a polymer liner layer, and a second dielectric layer. The first conductive structure is in the first dielectric layer. The second conductive structure is in the first dielectric layer and is separated from the first conductive structure. The first via is on the first conductive structure. The second via is on the second conductive structure. The polymer liner layer laterally surrounds the second via. The second dielectric layer laterally surrounds the first via and the polymer liner layer, wherein the second dielectric layer contacts the first via and is separated from the second via by the polymer liner layer. In the present invention, the polymer liner layer can be used to adjust the via opening size to form vias of different sizes in the same process.

Description

TECHNICAL FIELD

[0001] Some embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same. BACKGROUND

[0002] In back end of line (BEOL) of semiconductor devices, interconnect structures are formed on a device layer of a wafer. The interconnect structures can be used to provide electrical interconnections between different devices, such as transistors. The interconnect structures can include multiple metal layers and via structures connecting different metal layers. SUMMARY

[0003] Some embodiments of the present disclosure provide a semiconductor device including a first dielectric layer, a first conductive structure, a second conductive structure, a first via structure, a second via structure, a polymer liner layer, and a second dielectric layer. The first conductive structure is in the first dielectric layer. The second conductive structure is in the first dielectric layer and is separated from the first conductive structure. The first via structure is on the first conductive structure. The second via structure is on the second conductive structure. The polymer liner layer laterally surrounds the second via structure. The second dielectric layer laterally surrounds the first via structure and the polymer liner layer, wherein the second dielectric layer contacts the first via structure and is separated from the second via structure by the polymer liner layer.

[0004] In some embodiments, a width of the first via structure is greater than a width of the second via structure.

[0005] In some embodiments, a width of the second via structure is different from the second conductive structure.

[0006] In some embodiments, a side surface of the polymer liner layer forms an angle with an upper surface of the second conductive structure, and the angle is between 65 degrees and 75 degrees.

[0007] In some embodiments, the polymer liner layer contacts the second conductive structure and the first dielectric layer.

[0008] Some embodiments of the present disclosure provide a method of fabricating a semiconductor device, including forming a first conductive structure and a second conductive structure in a first dielectric layer. An etch stop layer is formed on the first conductive structure, the second conductive structure, and the first dielectric layer. A second dielectric layer is formed on the etch stop layer. A photoresist layer is formed on the second dielectric layer, wherein the photoresist layer has a first opening and a second opening, the first opening and the second opening have different sizes, and the first opening is located above the first conductive structure and the second opening is located above the second conductive structure. The second dielectric layer and the etch stop layer are etched by the photoresist layer to form a first via opening and a second via opening in the second dielectric layer and the etch stop layer, the first via opening exposes the first conductive structure, the second via opening exposes the second conductive structure, and a width of the first via opening is substantially the same as a width of the first conductive structure and a width of the second via opening is wider than a width of the second conductive structure. A polymer layer is formed in an upper surface of the second dielectric layer, the first via opening, and the second via opening. An etching process is performed to remove the polymer layer on the upper surface of the second dielectric layer, a bottom surface of the first via opening, and the second via opening, and to partially laterally remove the polymer layer on sidewalls of the second via opening to form a polymer liner layer on the sidewalls of the second via opening. A metal material is filled in the first via opening and the second via opening to form a first via in the first via opening and a second via in the second via opening.

[0009] In some embodiments, the polymer layer in the second via opening is thicker than the polymer layer in the first via opening when the polymer layer is formed.

[0010] In some embodiments, when the polymer layer is formed, the method includes using a gas to deposit the polymer layer, the gas including hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or a combination thereof.

[0011] In some embodiments, the etching process includes using a gas with a high fluorine ratio.

[0012] In some embodiments, the first via and the second via have different widths.

[0013] In summary, some embodiments of the present disclosure can be used to form vias with different sizes in the same process. Specifically, a photoresist layer with openings of different sizes can be formed on a dielectric layer first, and then a polymer layer is deposited on the photoresist layer. When the dielectric layer is etched, the polymer layer can be used to adjust the opening size to form vias with different sizes. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figures 1 to 8 Cross-sectional views illustrating intermediate stages of a process of fabricating a semiconductor device in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The present application will now be described more fully with reference to the accompanying drawings, in which several embodiments of the application will be shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, like reference numerals refer to like elements throughout.

[0016] Some embodiments of the present application are directed to methods of adjusting via sizes using deposition of a polymer. Specifically, a photoresist layer having openings of different sizes can be formed on a dielectric layer, and a polymer layer can be deposited on the photoresist layer. During etching of the dielectric layer, the polymer layer can be used to adjust the opening sizes to form vias of different sizes.

[0017] Figures 1 to 8 Cross-sectional views of intermediate stages of a process for fabricating a semiconductor device in accordance with some embodiments of the present application are shown. Referring to FIG. 1A, a first dielectric layer 102 is formed on a substrate 100. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. The first dielectric layer 102 can be formed on the substrate 100 using a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The first dielectric layer 102 can be formed of a dielectric material having a low dielectric constant, such as a dielectric constant less than 3.0. In some embodiments, the first dielectric layer 102 can be formed of a low-k or ultra-low-k dielectric material. Figure 1 A first conductive structure 112, a second conductive structure 114, and a third conductive structure 116 are formed in the first dielectric layer 102. The first dielectric layer 102 can be formed on elements of the semiconductor device, such as transistors, diodes, capacitors, resistors, or the like. Then, a plurality of openings are formed in the first dielectric layer 102 using an etching process, and appropriate conductive materials are filled in the openings to form the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 in the first dielectric layer 102. The first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are not interconnected with each other and are separated from each other by the first dielectric layer 102. The first dielectric layer 102 can provide electrical isolation between the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116. In some embodiments, the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 can be made of a metal, such as copper, and the first dielectric layer 102 can be made of a low-k or ultra-low-k dielectric material, such as a dielectric material having a dielectric constant less than 3.0.

[0018] In some embodiments, the first, second, and third conductive structures 112, 114, and 116 can be metal lines in interconnect structures in a semiconductor device, and thus the bottoms of the first, second, and third conductive structures 112, 114, and 116 can be connected to other elements in the semiconductor device, such as transistors, diodes, capacitors, resistors, or the like. Alternatively, the bottoms of the first, second, and third conductive structures 112, 114, and 116 can be connected to via elements in the interconnect structures. The first, second, and third conductive structures 112, 114, and 116 can be located in different regions of a wafer, such as in different peripheral circuit regions. Since the via elements in different regions require different resistance values, the sizes (e.g., widths) of the via elements in different regions are different to meet the required resistance values in the respective regions.

[0019] Referring to Figure 2 An etch stop layer 122 is formed on the first conductive structures 112, the second conductive structures 114, the third conductive structures 116, and the first dielectric layer 102, such that the etch stop layer 122 completely covers the first conductive structures 112, the second conductive structures 114, and the third conductive structures 116. In some embodiments, the etch stop layer 122 can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.

[0020] In some embodiments, the etch stop layer 122 can be formed of a suitable material, such as silicon nitride, silicon carbide, silicon carbon nitride, or the like.

[0021] Referring to Figure 3 A second dielectric layer 124 is formed on the etch stop layer 122. In some embodiments, the second dielectric layer 124 can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the second dielectric layer 124 can be made of a low dielectric constant dielectric material, such as a dielectric material having a dielectric constant lower than 3.0. In some embodiments, the second dielectric layer 124 can be made of the same material as the first dielectric layer 102.

[0022] Referring to Figure 4The photoresist layer PR is formed on the second dielectric layer 124, wherein the photoresist layer PR has the first opening O1, the second opening O2 and the third opening O3. Specifically, a photoresist material layer can be first formed on the second dielectric layer 124. Then, the photoresist material layer can be exposed to a light opaque pattern and developed to form the photoresist layer PR with a pattern on the second dielectric layer 124, wherein the pattern includes the first opening O1, the second opening O2 and the third opening O3. The first opening O1 is located above the first conductive structure 112, the second opening O2 is located above the second conductive structure 114, and the third opening O3 is located above the third conductive structure 116. In some embodiments, the first opening O1, the second opening O2 and the third opening O3 can be formed with different sizes according to the width of the via to be formed later. For example, the first opening O1 and the second opening O2 are different in size, and the first opening O1 and the third opening O3 are the same in size. Specifically, the second opening O2 can be larger than the first opening O1 and the third opening O3. Therefore, the sidewalls of the first opening O1 and the third opening O3 can be aligned with the edges of the upper surfaces of the first conductive structure 112 and the third conductive structure 116, respectively. The sidewalls of the second opening O2 are not aligned with the edges of the upper surface of the second conductive structure 114, and the width of the second opening O2 is wider than the width of the upper surface of the second conductive structure 114.

[0023] Referring to Figure 5 The second dielectric layer 124 and the etching stop layer 122 are etched by the photoresist layer PR to form the first via opening VO1, the second via opening VO2 and the third via opening VO3 in the second dielectric layer 124 and the etching stop layer 122. In some embodiments, a first etching process can be performed to etch the second dielectric layer 124 by the photoresist layer PR, and then a second etching process can be performed to etch the etching stop layer 122 by the photoresist layer PR and the second dielectric layer 124 to form the first via opening VO1, the second via opening VO2 and the third via opening VO3 in the second dielectric layer 124 and the etching stop layer 122. Then, the photoresist layer PR can be removed by a suitable method, such as photoresist ashing. The first etching process and the second etching process can be dry etching, wet etching or a combination thereof.

[0024] The first via opening VO1 exposes the first conductive structure 112, the second via opening VO2 exposes the second conductive structure 114, and the third via opening VO3 exposes the third conductive structure 116. The first via opening VO1 has the same width as the first conductive structure 112, and the third via opening VO3 has the same width as the third conductive structure 116, such that the sidewalls of the first via opening VO1 and the third via opening VO3 can align with the edges of the upper surfaces of the first conductive structure 112 and the third conductive structure 116, respectively, and the first via opening VO1 and the third via opening VO3 do not expose the first dielectric layer 102. The second via opening VO2 has a width that is wider than the width of the second conductive structure 114, and thus the second via opening VO2 exposes a portion of the first dielectric layer 102.

[0025] Referring to Figure 6 A polymer layer 130 is formed in the upper surface of the second dielectric layer 124, the first via opening VO1, the second via opening VO2, and the third via opening VO3. Specifically, a gas can be used to deposit the polymer layer 130. In some embodiments, the gas used to deposit the polymer layer 130 includes hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or a combination thereof.

[0026] When the polymer gas is deposited into the first via opening VO1, the second via opening VO2, and the third via opening VO3, the amount of polymer gas deposited in the openings can vary due to the different opening sizes. For example, when the openings are relatively small, such as the first via opening VO1 and the third via opening VO3, the polymer gas can not easily deposit in the openings. As a result, the polymer layer 132 formed in the first via opening VO1 and the third via opening VO3 can be relatively thin. When the openings are relatively large, such as the second via opening VO2, the polymer gas can easily deposit in the openings and can easily accumulate in the corners formed by the sidewalls of the second via opening VO2 and the upper surface of the first dielectric layer 102. As a result, the polymer layer 134 formed in the second via opening VO2 can be thicker than the polymer layer 132 formed in the first via opening VO1 and the third via opening VO3. The width of the second via opening VO2 can also be smaller than the first via opening VO1 and the third via opening VO3. In addition, because the polymer gas can easily accumulate in the corners of the second via opening VO2, the width of the polymer layer 134 can narrow in a direction away from the first dielectric layer 102. As a result, after the polymer layer 130 is formed, the width of the second via opening VO2 can be reduced and an opening can be formed that widens in a direction away from the first dielectric layer 102. When the polymer layer 130 is formed, the polymer layer 134 in the second via opening VO2 can cover the upper surface of the first dielectric layer 102, such that the bottom of the second via opening VO2 can be narrower than the upper surface of the second conductive structure 114.

[0027] Referring to Figure 7 , an etching process is performed to remove the polymer layer 130 on the upper surface of the second dielectric layer 124, the bottom surfaces of the first via opening VO1, the second via opening VO2, and the third via opening VO3, the polymer layer 132 on the sidewalls of the first via opening VO1 and the third via opening VO3, and partially laterally remove the polymer layer 134 on the sidewalls of the second via opening VO2 to form a polymer spacer layer 136 on the sidewalls of the second via opening VO2.

[0028] In particular, Figure 7 The etching process in the second dielectric layer 124 can laterally etch the polymer layer 130 on the sidewalls of the first via opening VO1, the second via opening VO2, and the third via opening VO3. Because the polymer layer 132 on the sidewalls of the first via opening VO1 and the third via opening VO3 is relatively thin, the polymer layer 132 can be laterally etched when the etching process is performed. Figure 7During the etching process in the second via opening V02, the polymer layer 134 is thicker, so the etching process only partially side-etches the polymer layer 134 on the sidewall of the second via opening V02, and forms a polymer spacer layer 136 on the sidewall of the second via opening V02. During the etching process, the polymer spacer layer 136 still covers the upper surface of the first dielectric layer 102, so that the second via opening V02 still only exposes the second conductive structure 114. In this way, the polymer layer 130 can be used to manufacture via openings of different sizes in the same process. In some embodiments, the etching can be performed using a suitable etching gas, such as a gas with a high fluorine ratio, such as carbon tetrafluoride. Because the polymer layer 134 is a polymer layer accumulated on the second via opening V02, the sidewall of the polymer layer 134 and the upper surface of the second conductive structure 114 have an included angle a. In some embodiments, the included angle a is between 65 degrees and 75 degrees.

[0029] Referring to Figure 8 , a metal filling material is filled in the first via opening V01, the second via opening V02, and the third via opening V03 to form a first via 142 in the first via opening V01, a second via 144 in the second via opening V02, and a third via 146 in the third via opening V03.

[0030] In this way, the resulting semiconductor device is as shown in Figure 8The semiconductor device can include the first dielectric layer 102, the first conductive structure 112, the second conductive structure 114, the third conductive structure 116, the first via 142, the second via 144, the third via 146, the polymer liner layer 136, and the second dielectric layer 124. The first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are located in the first dielectric layer 102, and the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 are separated from each other by the first dielectric layer 102. The first via 142, the second via 144, and the third via 146 are located on the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116, respectively. The polymer liner layer 136 laterally surrounds the second via 144. The second dielectric layer 124 laterally surrounds the first via 142, the third via 146, and the polymer liner layer 136. The second dielectric layer 124 contacts the first via 142 and is separated from the second via 144 by the polymer liner layer 136. In some embodiments, the semiconductor device further includes the etch stop layer 122. The etch stop layer 122 is located under the second dielectric layer 124 and on the first dielectric layer 102, and contacts the polymer liner layer 136.

[0031] The polymer liner layer 136 can be used to adjust the width of the via openings. For example, the polymer liner layer 136 can be formed on the sidewalls of the second via opening VO2 such that the polymer liner layer 136 contacts the second conductive structure 114 and the first dielectric layer 102, thereby reducing the width of the second via opening VO2. The resulting widths of the first via 142, the second via 144, and the third via 146 are thus different. For example, the widths of the first via 142 and the third via 146 are greater than the width of the second via 144. The polymer liner layer 136 makes the bottom of the second via opening VO2 narrower than the second conductive structure 114, so the bottom width of the second via 144 is different from the width of the top surface of the second conductive structure 114. The first via opening VO1 and the third via opening VO3 do not have a polymer liner layer, and the sidewalls of the first via opening VO1 and the third via opening VO3 are substantially aligned with the top surface of the first conductive structure 112 and the top surface of the third conductive structure 116, respectively. Thus, the first via 142 and the third via 146 can be substantially aligned with the top surface of the first conductive structure 112 and the top surface of the third conductive structure 116, respectively. In this way, vias with different sizes can be fabricated in the same process, reducing the complexity of the process. The vias with different sizes can be used in different regions of a wafer, providing specific resistance values for specific regions.

[0032] It should be noted that, Figures 1 to 8A process of forming one of the conductive structures and via features in an interconnect structure of a semiconductor device is illustrated. After the process of FIG. 1 is completed, the process of FIG. 2 can be repeated to form the conductive structures and via features on the first via feature 142, the second via feature 144, and the third via feature 146. In this way, the formation of the interconnect structure of the semiconductor device can be completed. Figure 8 Figures 1 to 8 The process of FIG. 2 can be repeated to form the conductive structures and via features on the first via feature 142, the second via feature 144, and the third via feature 146. In this way, the formation of the interconnect structure of the semiconductor device can be completed.

[0033] In summary, the process using the embodiments of the present application can form via features of different sizes in the same process. Specifically, the amount of polymer gas deposited in the openings can vary depending on the size of the openings. For example, the polymer gas can be more readily deposited in wider openings and less readily deposited in narrower openings. Thus, via feature openings of different sizes can be formed in the dielectric layer, and then the polymer gas can be deposited to form a polymer liner layer that adjusts the size of the via feature openings. Then, via features of different sizes can be formed. In this way, via features of different sizes can be formed in the same process, and the complexity of the process can be reduced.

[0034] Although the present application has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof will no depart from the spirit and scope of the present application, which are defined by the following claims. Thus, what is desired to be secured by Letters Patent is the following:

[0035] SYMBOL DESCRIPTION

[0036] 102: first dielectric layer

[0037] 112: first conductive structure

[0038] 114: second conductive structure

[0039] 116: third conductive structure

[0040] 122: etch stop layer

[0041] 124: second dielectric layer

[0042] 130: polymer layer

[0043] 132: polymer layer

[0044] 134: polymer layer

[0045] 136: polymer liner layer

[0046] 142: first via feature

[0047] 144: second via feature

[0048] 146: third via feature ​

[0049] a: angle

[0050] O1: first opening

[0051] O2: second opening

[0052] O3: third opening

[0053] PR: photoresist layer

[0054] VO1: first via opening

[0055] VO2: second via opening

[0056] VO3: third via opening

Claims

1. A semiconductor device, characterized by comprising: comprising: a first dielectric layer; a first conductive structure in the first dielectric layer; a second conductive structure in the first dielectric layer and separated from the first conductive structure; a first via on the first conductive structure; a second via on the second conductive structure; a polymer liner laterally surrounding the second via, the first via having a first dimension in a cross-section, the polymer liner and the second via having a second dimension in the cross-section, the second dimension being greater than the first dimension, and the first via having a width greater than a width of the second via; and a second dielectric layer laterally surrounding the first via and the polymer liner, wherein the second dielectric layer contacts the first via and is separated from the second via by the polymer liner.

2. The semiconductor device of claim 1, wherein the width of the second via is different from the second conductive structure.

3. The semiconductor device of claim 1, wherein a side surface of the polymer liner forms an angle with an upper surface of the second conductive structure, and the angle is between 65 degrees and 75 degrees.

4. The semiconductor device of claim 1, wherein the polymer liner contacts the second conductive structure and the first dielectric layer. comprising:

5. A method of manufacturing a semiconductor device, characterized by, forming a first conductive structure and a second conductive structure in a first dielectric layer; forming an etch stop layer on the first conductive structure, the second conductive structure, and the first dielectric layer; forming a second dielectric layer on the etch stop layer; forming a photoresist layer on the second dielectric layer, wherein the photoresist layer has a first opening and a second opening, the first opening and the second opening are different in size, and the first opening is above the first conductive structure and the second opening is above the second conductive structure; etching the second dielectric layer and the etch stop layer by the photoresist layer to form a first via opening and a second via opening in the second dielectric layer and the etch stop layer, the first via opening exposes the first conductive structure, the second via opening exposes the second conductive structure, and the first via opening has substantially the same width as the first conductive structure and the second via opening has a width wider than a width of the second conductive structure; forming a polymer layer in an upper surface of the second dielectric layer, the first via opening, and the second via opening; performing an etching process to remove the polymer layer on the upper surface of the second dielectric layer, in the first via opening, and on a bottom surface of the second via opening, and partially laterally remove the polymer layer on a sidewall of the second via opening to form a polymer liner layer on the sidewall of the second via opening; and filling a metal material in the first via opening and the second via opening to form a first via in the first via opening and a second via in the second via opening.

6. The method of claim 5, wherein the polymer layer in the second via opening is thicker than the polymer layer in the first via opening when the polymer layer is formed. ​ 7. The method of claim 5, wherein in forming the polymer layer, a gas comprising hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or a combination thereof is used to deposit the polymer layer.

8. The method of claim 5, wherein performing the etching process comprises using a gas having a high fluorine ratio.

9. The method of claim 5, wherein the first via feature and the second via feature are different in width.

Images