Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate; a redistribution layer disposed on the substrate and having a dielectric layer, a conductive plug, and a bonding pad, wherein the dielectric layer is disposed on the substrate, the conductive plug extends within the dielectric layer, and the bonding pad is adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump. Furthermore, a method for fabricating the semiconductor structure is also provided.

Description

[0001] This invention claims priority to U.S. Patent Applications No. 17 / 541,792 and No. 17 / 543,194 (i.e., priority dates of December 3, 2021 and December 6, 2021), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor structure. More particularly, it relates to a semiconductor structure having a bonding pad that is at least partially exposed via a redistribution layer to accommodate an external interconnect structure. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The fabrication of semiconductor components involves sequentially depositing different material layers on a semiconductor substrate, and using photolithography and etching processes to pattern multiple material layers to form multiple microelectronic components on or within the semiconductor substrate. These microelectronic components include transistors, diodes, resistors, and / or capacitors.

[0004] The semiconductor industry continues to increase the integration density of microelectronic components by constantly shrinking the minimum feature size, which allows more components to be integrated into a given area. For example, to further increase the density of semiconductor components, the stacking of two or more components has been investigated. Therefore, there is a desire to develop improvements that address the associated manufacturing challenges.

[0005] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a redistribution layer disposed on the substrate and including a dielectric layer, a conductive plug, and a bonding pad, the dielectric layer being disposed on the substrate, the conductive plug extending within the dielectric layer, the bonding pad being adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

[0007] In some embodiments, a first surface of the conductive plug and a second surface of the bonding pad are exposed via the dielectric layer.

[0008] In some embodiments, the first surface of the conductive plug is substantially coplanar with the second surface of the bonding pad.

[0009] In some embodiments, the first surface of the conductive plug contacts a seed layer of the conductive bump with the second surface of the bonding pad.

[0010] In some embodiments, the first surface of the conductive plug, the second surface of the bonding pad, and a third surface of the dielectric layer are substantially coplanar.

[0011] In some embodiments, the first surface of the conductive plug is completely covered by the conductive bump.

[0012] In some embodiments, a first portion of the second surface of the bonding pad is covered by the conductive bump, a second portion of the second surface is exposed via the dielectric layer and through the conductive bump, and the first portion is substantially smaller than the second portion.

[0013] In some embodiments, one upper cross-section of the bonding pad has an annular shape, a fan shape, or a polygonal shape.

[0014] In some embodiments, the height of the conductive plug is generally greater than the thickness of the bonding pad.

[0015] In some embodiments, the redistribution layer has a conductive component that electrically connects the conductive plug to the substrate.

[0016] In some embodiments, the conductive component is electrically connected to the conductive plug via the conductive plug.

[0017] In some embodiments, the conductive component is electrically connected to the bonding pad via the conductive plug.

[0018] In some embodiments, the conductive bump is electrically connected to an element disposed on the substrate via the conductive component and the conductive plug.

[0019] In some embodiments, the conductive component includes a solder pad portion and a via portion, the solder pad portion extending horizontally within the dielectric layer, and the via portion coupled to the solder pad portion and extending vertically from the solder pad portion.

[0020] In some embodiments, the conductive plug contacts the bonding pad and the solder pad portion.

[0021] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate; and a redistribution layer disposed on the first substrate, and including a dielectric layer, a conductive plug, and a bonding pad. The dielectric layer is disposed on the first substrate, the conductive plug extends within the dielectric layer, and the bonding pad is surrounded by the dielectric layer and contacts the conductive plug; wherein the conductive plug is at least partially surrounded by the bonding pad.

[0022] In some embodiments, the semiconductor structure further includes a conductive bump that covers the conductive plug and partially covers the bonding pad.

[0023] In some embodiments, the width of the conductive plug is generally smaller than the width of the conductive bump.

[0024] In some embodiments, an interface between the conductive plug and the bonding pad is provided under the conductive bump.

[0025] In some embodiments, the conductive bump is disposed on an interconnect structure of a second substrate and engages with the interconnect structure of the second substrate.

[0026] In some embodiments, the bonding pad includes a first bonding pad and a second bonding pad, the second bonding pad being separated from the first bonding pad, and the conductive plug being disposed between the first bonding pad and the second bonding pad.

[0027] In some embodiments, the conductive plug contacts the first joint and the second joint.

[0028] In some embodiments, the semiconductor structure further includes a bonding line disposed on and bonded to the bonding pad.

[0029] In some embodiments, the first substrate includes a plurality of elements disposed thereon and a plurality of insulators that separate the plurality of elements.

[0030] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The fabrication method includes providing a substrate and a redistribution layer disposed on the substrate, wherein the redistribution layer has a dielectric layer and a conductive plug, a grounding layer disposed on the substrate, and the conductive plug extending within the dielectric layer; disposing an etch stop layer on the redistribution layer; disposing a first patterned photoresist on the etch stop layer; removing a portion of the dielectric layer and a portion of the etch stop layer exposed via the first patterned photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and a portion of the dielectric layer exposed via the first patterned photoresist; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed via the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material protruding from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer.

[0031] In some embodiments, the first seed layer disposed on the etch stop layer contacts the conductive plug.

[0032] In some embodiments, the bonding pad includes the first seed layer and the conductive material.

[0033] In some embodiments, after the removal of the second patterned photoresist, the portion of the conductive material protrudes from the etch-stop layer.

[0034] In some embodiments, removal of the portion of the dielectric layer exposed by the first patterned photoresist includes forming an opening to extend into the dielectric layer and disposed adjacent to the conductive plug.

[0035] In some embodiments, after the opening is formed, the conductive plug is at least partially exposed.

[0036] In some embodiments, the opening surrounds the conductive plug.

[0037] In some embodiments, the second patterned photoresist fills a portion of the opening.

[0038] In some embodiments, the second patterned photoresist is at least partially surrounded by the first seed layer.

[0039] In some embodiments, the preparation method further includes: disposing a dielectric material within the opening and on the etch stop layer; and removing a portion of the dielectric material disposed on the etch stop layer.

[0040] In some embodiments, the semiconductor structure further includes: disposing a second seed layer on the bonding pad, the conductive plug, and the dielectric layer; disposing a third patterned photoresist on the second seed layer; and forming a conductive bump on a portion of the second seed layer exposed via the third patterned photoresist.

[0041] In summary, because the bonding pad is located adjacent to the conductive plug in the redistribution layer, it can accommodate an external interconnect structure, such as a wire bond. Furthermore, the bonding pad can be formed in various shapes to accommodate external interconnect structures oriented in the same direction as the portion surrounding the conductive plug. Therefore, a flexible interconnect and wiring configuration for the semiconductor structure can be achieved.

[0042] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0043] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0044] Figure 1 This is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0045] Figure 2 This is a top sectional view, illustrating an embodiment. Figure 1 A semiconductor element along a section line A-A'.

[0046] Figure 3 This is a top sectional view, illustrating an embodiment. Figure 1 A semiconductor element along a section line A-A'.

[0047] Figure 4 This is a top sectional view, illustrating an embodiment. Figure 1 A semiconductor element along a section line A-A'.

[0048] Figure 5 This is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0049] Figure 6 This is a top sectional view, illustrating an embodiment. Figure 5 A semiconductor element along a section line B-B'.

[0050] Figure 7 This is a top sectional view, illustrating an embodiment. Figure 5 A semiconductor element along a section line B-B'.

[0051] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure.

[0052] Figures 9 to 36 This is a cross-sectional schematic diagram illustrating the intermediate stages of preparing a semiconductor structure according to some embodiments of this disclosure.

[0053] The attached figures are labeled as follows:

[0054] 100: Semiconductor Structure

[0055] 101: Base

[0056] 101a: Semiconductor layer

[0057] 101b: Insulator

[0058] 101c: Components

[0059] 101d: Rear side

[0060] 101e: Front

[0061] 102: Redistribution layer

[0062] 102a: Solder pad portion

[0063] 102b: Through-hole section

[0064] 102c: Conductive embolism

[0065] 102d: Joint pad

[0066] 102e: solder pad

[0067] 102f: Seed layer

[0068] 102g: Dielectric layer

[0069] 102h: First surface

[0070] 102i: Second Surface

[0071] 102j: Third surface

[0072] 102k: First bonding pad

[0073] 102m: Second joint pad

[0074] 102n: Part 1

[0075] 102p: Part Two

[0076] 102r: Interface

[0077] 102s: Opening

[0078] 103: Conductive bump

[0079] 103a: Lower bump metal layer

[0080] 103b: Metal layer

[0081] 103c: Barrier layer

[0082] 103d: Solder assembly

[0083] 104: Etching stop layer

[0084] 105: First Patterned Photoresist

[0085] 106: First seed crystal layer

[0086] 107: Second patterned photoresist

[0087] 108: Conductive Materials

[0088] 109: Dielectric Materials

[0089] 110: Second seed crystal layer

[0090] 111: Third Patterned Photoresist

[0091] 112: Joint line

[0092] H1: Height

[0093] H2: Height

[0094] S200: Preparation Method

[0095] S201: Steps

[0096] S202: Steps

[0097] S203: Steps

[0098] S204: Steps

[0099] S205: Steps

[0100] S206: Steps

[0101] S207: Steps

[0102] S208: Steps

[0103] S209: Steps

[0104] S210: Steps

[0105] S211: Steps

[0106] W1: Width

[0107] W2: Width Detailed Implementation

[0108] Embodiments or examples of the present disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0109] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0110] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, the multiple terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0111] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor structure 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 100 is part of a die, a package, or an element. In some embodiments, the semiconductor structure 100 is a flip-chip package. In some embodiments, the semiconductor structure 100 includes a substrate 101, a redistribution layer 102, and a conductive bump 103, wherein the redistribution layer 102 is disposed on the substrate 101, and the conductive bump 103 is disposed on the redistribution layer 102.

[0112] In some embodiments, substrate 101 is part of a wafer. In some embodiments, substrate 101 is cut from a wafer by dicing, cutting, or other suitable operations. In some embodiments, substrate 101 comprises a semiconductor material, such as silicon. In some embodiments, substrate 101 is a silicon substrate. In some embodiments, substrate 101 includes a semiconductor layer 101a, a plurality of insulators 101b, and a plurality of elements 101c, wherein the plurality of elements 101c are disposed on the semiconductor layer 101a and separated by the plurality of insulators 101b.

[0113] In some embodiments, semiconductor layer 101a includes a rear side 101d and a front side 101e, the front side 101e being disposed opposite to the rear side 101d. During the fabrication of semiconductor structure 100, the rear side 101d is disposed on a support substrate. A plurality of elements 101c are formed on the front side 101e and configured to be electrically connected to an external circuit. In some embodiments, the plurality of elements 101c are metal-oxide-semiconductor (MOS) elements. In some embodiments, the plurality of insulators 101b are shallow trench isolation (STI).

[0114] In some embodiments, a redistribution layer 102 is disposed on the front side 101e of a substrate 101. The redistribution layer 102 redewires a path of a circuit from a plurality of elements 101c on the substrate 101 to conductive bumps 103. In some embodiments, the redistribution layer 102 includes a conductive component (102a and 102b), a conductive plug 102c, a bonding pad 102d, and a dielectric layer 102g, wherein the dielectric layer 102g surrounds the conductive component (102a and 102b), the conductive plug 102c, and the bonding pad 102d.

[0115] In some embodiments, a dielectric layer 102g is disposed on the front side 101e of a substrate 101 and covers a plurality of elements 101c. The dielectric layer 102g comprises a dielectric material, such as an oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer, or the like. In some embodiments, the dielectric layer 102g comprises a plurality of dielectric layers stacked thereon. In some embodiments, each dielectric layer comprises a material that is the same as or different from the material of the other dielectric layers.

[0116] In some embodiments, the conductive components (102a and 102b) are an interconnect structure electrically connected to the substrate 101. The conductive components (102a and 102b) are disposed within the dielectric layer 102g. In some embodiments, the conductive components (102a and 102b) comprise a conductive material, such as gold, silver, copper, nickel, aluminum, or the like. In some embodiments, the conductive components (102a and 102b) include a solder pad portion 102a and a via portion 102b, the solder pad portion 102a extending horizontally within the dielectric layer 102g, and the via portion 102b coupled to the solder pad portion 102a and extending vertically within the dielectric layer 102g and away from the solder pad portion 102a.

[0117] In some embodiments, the conductive plug 102c extends vertically within the dielectric layer 102g and toward the conductive components (102a and 102b). In some embodiments, the conductive plug 102c is disposed on the pad portion 102a. The conductive plug 102c is electrically connected to the substrate 101 via the conductive components (102a and 102b). In some embodiments, the conductive plug 102c is surrounded by the dielectric layer 102g. In some embodiments, a first surface 102h of the conductive plug 102c is exposed via the dielectric layer 102g. In some embodiments, the conductive plug 102c comprises a conductive material, such as gold, silver, copper, nickel, aluminum, or the like.

[0118] In some embodiments, a bonding pad 102d is disposed adjacent to a conductive plug 102c and surrounded by a dielectric layer 102g. In some embodiments, the bonding pad 102d at least partially contacts the conductive plug 102c. The bonding pad 102d is electrically connected to the conductive plug 102c. In some embodiments, a sidewall of the bonding pad 102d contacts a sidewall of the conductive plug 102c. In some embodiments, the bonding pad 102d is electrically connected to conductive components (102a and 102b) via the conductive plug 102c. In some embodiments, the bonding pad 102d comprises a conductive material, such as gold, silver, copper, nickel, aluminum, or the like.

[0119] In some embodiments, bonding pad 102d includes a seed layer 102e and a solder pad 102f, with the solder pad 102f surrounded by the seed layer 102e. In some embodiments, the seed layer 102e contacts a conductive plug 102c. In some embodiments, the seed layer 102e is surrounded by a dielectric layer 102g and a conductive plug 102c. In some embodiments, the seed layer 102e is a single layer or a composite stack and comprises a material such as copper, aluminum, tungsten, or a combination thereof. In some embodiments, the solder pad 102f contacts and is completely surrounded by the seed layer 102e. In some embodiments, the solder pad 102f comprises a conductive material such as copper, silver, gold, or the like.

[0120] In some embodiments, the conductive plug 102c is at least partially surrounded by the engagement pad 102d. In some embodiments, the engagement pad 102d is along... Figure 1 The upper section of section line A-A' can be of any different shape. In some embodiments, the upper section of the mating pad 102d is a polygonal shape. For example, such as Figure 2 As shown, the upper cross-section of the mating pad 102d is a fan shape. For example, as... Figure 3 and Figure 4 As shown, the upper cross section of the bonding pad 102d is a quarter-ring shape or a semi-ring shape.

[0121] In some embodiments, the engagement pad 102d is along... Figure 5 The upper section of section line B-B' is as follows Figure 6 The ring shape shown. In some embodiments, such as Figure 5 and Figure 7 As shown, the bonding pad 102d includes a first bonding pad 102k and a second bonding pad 102m, with the second bonding pad 102m being spaced apart from the first bonding pad 102k. A conductive plug 102c is disposed between the first bonding pad 102k and the second bonding pad 102m. In some embodiments, the conductive plug 102c contacts the first bonding pad 102k and the second bonding pad 102m. In some embodiments, an upper cross-section of the first bonding pad 102k and an upper cross-section of the second bonding pad 102m are both fan-shaped.

[0122] Please refer back to this page. Figure 1 In some embodiments, the bonding pad 102d includes a second surface 102i exposed via the dielectric layer 102g. In some embodiments, the second surface 102i of the bonding pad 102d is substantially coplanar with the first surface 102h of the conductive plug 102c. In some embodiments, the second surface 102i includes an upper surface of the seed layer 102e and an upper surface of the solder pad 102f.

[0123] In some embodiments, the conductive plug 102c has a height H1 that is substantially greater than a height H2 of the bonding pad 102d. The height H1 of the conductive plug 102c extends from the first surface 102h to the bonding pad portion 102a. The height H2 of the bonding pad 102d extends from the second surface 102i to the front side 101e of the substrate 101.

[0124] In some embodiments, the dielectric layer 102g includes a third surface 102j disposed opposite to the front side 101e of the substrate 101. In some embodiments, the first surface 102h of the conductive plug 102c, the second surface 102i of the bonding pad 102d, and the third surface 102j of the dielectric layer 102g are substantially coplanar.

[0125] In some embodiments, conductive bumps 103 are disposed on conductive plugs 102c. In some embodiments, conductive bumps 103 are disposed on a portion of the bonding pads 102d and dielectric layer 102g of redistribution layer 102. In some embodiments, bonding pads 102d at least partially contact conductive plugs 102c and conductive bumps 103. In some embodiments, conductive components (102a and 102b) are electrically connected to conductive bumps 103 via conductive plugs 102c. In some embodiments, conductive bumps 103 are electrically connected to element 101c disposed on substrate 101. In some embodiments, a first surface 102h of conductive plug 102c and a second surface 102i of bonding pad 102d contact conductive bumps 103.

[0126] In some embodiments, an interface 102r is provided under the conductive bump 103 between the conductive plug 102c and the bonding pad 102d. In some embodiments, the conductive bump 103 is provided on an interconnect structure of another substrate (not shown) and engages with the interconnect structure of the other substrate. For example, because the semiconductor structure 100 is a flip-chip package, therefore... Figure 1 The semiconductor structure 100 shown is flipped upside down, and conductive bumps 103 are disposed on and bonded to an interconnect structure, which is, for example, a bonding pad disposed on another substrate under the semiconductor structure 100.

[0127] In some embodiments, the first surface 102h is completely covered by and in contact with the conductive bump 103. In some embodiments, a first portion 102n of the second surface 102i covered by the conductive bump 103 is substantially smaller than a second portion 102p of the second surface 102i exposed via the dielectric layer 102g and via the conductive bump 103. In some embodiments, the second portion 102p of the second surface 102i of the bonding pad 102d is configured to receive a bonding wire, thereby electrically connecting the semiconductor structure 100 to other semiconductor structures or other substrates. Because the bonding pad 102d can be formed into various desired shapes and sizes, it can accommodate external interconnect structures, such as bonding wires with different orientations around conductive plugs. Therefore, a flexible interconnect and wiring of the semiconductor structure 100 can be achieved.

[0128] In some embodiments, the conductive bump 103 comprises a conductive material, such as lead, tin, copper, gold, nickel, or the like. In some embodiments, the conductive bump 103 is a ball grid array (BGA) solder ball, a controlled collapse chip connection (C4) bump, a microbump, a pillar, or the like. In some embodiments, the conductive plug 102c has a width W1, which is substantially smaller than a width W2 of the conductive bump 103.

[0129] In some embodiments, the conductive bump 103 includes a lower bump metal (UBM) layer 103a, a metal layer 103b, a barrier layer 103c, and a solder assembly 103d. In some embodiments, the lower bump metal layer 103a is disposed on the conductive plug 102c and the dielectric layer 102g. The lower bump metal layer 103a contacts a first surface 102h and a third surface 102j. In some embodiments, the lower bump metal layer 103a covers the first surface 102h and partially covers the second surface 102i. In some embodiments, the lower bump metal layer 103a is a seed layer or an adhesive layer for accommodating the conductive bump 103 of the metal layer 103b. In some embodiments, the lower bump metal layer 103a contacts the first surface of the conductive plug 102c and the second surface 102i of the bonding pad 102d. In some embodiments, the lower bump metal layer 103a includes titanium, copper, gold, or the like. In some embodiments, the lower bump metal layer 103a includes at least two conductive materials.

[0130] In some embodiments, a metal layer 103b is disposed on the lower bump metal layer 103a and the conductive plug 102c. In some embodiments, the metal layer 103b comprises a conductive material, such as copper, silver, gold, or the like. In some embodiments, a barrier layer 103c is disposed on the metal layer 103b, the lower bump metal layer 103a, and the conductive plug 102c. In some embodiments, the barrier layer 103c is configured to prevent the metal layer 103b from diffusing into the solder assembly 103d. In some embodiments, the barrier layer 103c comprises titanium, titanium nitride, tantalum, tantalum nitride, nickel, or the like.

[0131] In some embodiments, solder assembly 103d is disposed on barrier layer 103c, metal layer 103b, and lower bump metal layer 103a. In some embodiments, solder assembly 103d includes reflowable material. In some embodiments, solder assembly 103d includes tin, lead, silver, copper, nickel, or the like. In some embodiments, solder assembly 103d is configured to bond an interconnect structure of another substrate to semiconductor structure 100, such as a bonding pad.

[0132] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure, S200, according to some embodiments of the present disclosure. Figures 9 to 36 This is a cross-sectional schematic diagram illustrating the intermediate stages of fabricating the semiconductor structure 100 according to some embodiments of the present disclosure.

[0133] like Figures 9 to 36 The stages shown are also illustrated in... Figure 8 In the flowchart. In the following discussion, as Figures 9 to 36 References for each manufacturing stage are shown below. Figure 8The processing steps shown are discussed. Preparation method S200 includes many steps, and the description and explanation are not intended to be considered as a limitation on the order of the multiple steps. Preparation method S200 includes many steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, S210, S211).

[0134] Please refer to Figure 9 ,in accordance with Figure 8 In step S201, a substrate 101 and a redistribution layer 102 disposed on the substrate 101 are provided. In some embodiments, the redistribution layer 102 includes a dielectric layer 102g and a conductive plug 102c, the dielectric layer 102g being disposed on the substrate 101 and the conductive plug 102c extending within the dielectric layer 102g. In some embodiments, the fabrication technique of the redistribution layer 102 includes disposing a dielectric material on the substrate 101; removing a portion of the dielectric material; and disposing a conductive material to form the conductive plug 102c and a conductive component (102a and 102b).

[0135] Please refer to Figure 10 According to Figure 10 In step S202, an etch stop layer 104 is disposed on the redistribution layer 102. The etch stop layer 104 is disposed on the dielectric layer 102g and the conductive plug 102c. In some embodiments, the etch stop layer 104 comprises a dielectric material having an etch selectivity different from that of adjacent materials. In some embodiments, the etch stop layer 104 comprises a nitride, silicon nitride, or the like. In some embodiments, the etch stop layer 104 is deposited by chemical vapor deposition (CVD) or any other suitable process.

[0136] Please refer to Figure 11 ,in accordance with Figure 8 In step S203, a first patterned photoresist 105 is disposed on the etch stop layer 104. In some embodiments, the fabrication technique of the first patterned photoresist 105 includes disposing a photoresist material on the etch stop layer 104; covering some portions of the photoresist material; and then removing the exposed portions of the photoresist material to pattern the photoresist material, thereby forming the first patterned photoresist 105. In some embodiments, a portion of the etch stop layer 104 is exposed via the first patterned photoresist 105. In some embodiments, a plurality of portions of the etch stop layer 104 are exposed via, for example, Figure 12 The first patterned photoresist 105 is exposed as shown. In some embodiments, a plurality of exposed portions of the photoresist material are configured to form a ring field having an annular shape. In some embodiments, the photoresist material is set by spin coating or any other suitable process.

[0137] Please refer to Figure 13 ,in accordance with Figure 8 In step S204, portions of the dielectric layer 102g and the etch stop layer 104 exposed via the first patterned photoresist 105 are removed. In some embodiments, portions of the dielectric layer 102g and the etch stop layer 104 exposed via the first patterned photoresist 105 are removed simultaneously or sequentially. The portions of the dielectric layer 102g and the etch stop layer 104 exposed via the first patterned photoresist 105 are removed by an etching process, such as dry etching or other suitable etching processes. In some embodiments, an opening 102s is formed. In some embodiments, the removal of multiple portions of the dielectric layer 102g exposed via the first patterned photoresist 105 includes forming an opening 102s that extends into the dielectric layer 102g and is located adjacent to the conductive plug 102c. In some embodiments, after the opening 102s is formed, at least partially exposed conductive plug 102c is exposed. In some embodiments, as shown in the figure... Figure 14 A plurality of openings 102s are shown. In some embodiments, the openings 102s surround the conductive plug 102c. In some embodiments, at least a portion of the conductive plug 102c is exposed via the openings 102s.

[0138] Please refer to Figure 15 or Figure 16 ,in accordance with Figure 8 In step S205, the first patterned photoresist 105 is removed. In some embodiments, the first patterned photoresist 105 is removed by etching, stripping, or any suitable process.

[0139] Please refer to Figure 17 ,in accordance with Figure 8 In step S206, a first seed layer 106 is disposed on the etch stop layer 1404 and on a portion of the dielectric layer 102g exposed via the etch stop layer 104. In some embodiments, the first seed layer 106 is conformally disposed with the etch stop layer 104 and the opening 102s. In some embodiments, the first seed layer 106 is conformally disposed with, for example, the etch stop layer 104 and the opening 102s. Figure 18 A plurality of openings 102s are conformally arranged. In some embodiments, at least a portion of the first seed layer 106 contacts the portion of the conductive plug 102c exposed via the openings 102s. In some embodiments, the first seed layer 106 is a monolayer or a composite stack, and comprises materials such as copper, titanium, tungsten, or combinations thereof. In some embodiments, the first seed layer 106 is formed by deposition, physical vapor deposition (PVD), or any other suitable process.

[0140] Please refer to Figure 19 ,in accordance with Figure 8In step S207, a second patterned photoresist 107 is disposed on the first seed layer 106. In some embodiments, the fabrication technique for the second patterned photoresist 107 includes disposing a photoresist material on the first seed layer 106; covering a portion of the photoresist material; and then removing the exposed portion of the photoresist material to pattern the photoresist material, thereby forming the second patterned photoresist 107. In some embodiments, a portion of the first seed layer 106 is exposed via the second patterned photoresist 107. In some embodiments, the photoresist material is disposed by spin coating or other suitable processes. In some embodiments, a portion of the first seed layer 106 is... Figure 20 The second patterned photoresist 107 is shown as covering the opening 102s. The second patterned photoresist 107 fills the opening 102s. In some embodiments, the second patterned photoresist 107 is at least partially surrounded by the first seed layer 106.

[0141] Please refer to Figure 21 or Figure 22 ,in accordance with Figure 8 In step S208, a conductive material is disposed on the portion of the first seed layer 106 exposed via the second patterned photoresist 107. In some embodiments, the conductive material 108 contacts the first seed layer 106 and fills the opening 102s. In some embodiments, the conductive material 108 includes copper, silver, gold, or the like. In some embodiments, the conductive material 108 is disposed by electroplating or any other suitable process.

[0142] Please refer to Figure 23 ,in accordance with Figure 8 In step S209, the second patterned photoresist 107 is removed. In some embodiments, the second patterned photoresist 107 is removed by etching, stripping, or any other suitable process. In some embodiments, in such... Figure 24 After the second patterned photoresist shown is removed, the opening is exposed for 102 seconds.

[0143] In some embodiments, such as Figure 23 After the second patterned photoresist 107 is removed, as shown Figure 25 As shown, a portion of the conductive material 108 protruding from the etch stop layer 104 is removed. In some embodiments, this portion of the conductive material 108 protruding from the etch stop layer 104 is removed by etching, planarization, chemical mechanical polishing (CMP), or any other suitable process.

[0144] In some embodiments, such as Figure 24 After the second patterned photoresist 107 is removed, as shown Figure 26As shown, an additional dielectric material 109 is disposed on the etch stop layer 104. In some embodiments, the additional dielectric material 109 fills the opening 102s. In some embodiments, the additional dielectric material 109 surrounds a portion of the conductive material 108. In some embodiments, as Figure 27 As shown, the additional dielectric material 109 and conductive material 108 protruding from the etch stop layer 104 are removed. In some embodiments, the additional dielectric material 109 and conductive material 108 protruding from the etch stop layer 104 are removed by etching, chemical mechanical polishing (CMP), or any other suitable process.

[0145] Please refer to Figure 28 or Figure 29 ,in accordance with Figure 8 In step S210, the etch stop layer 104 is removed. In some embodiments, the etch stop layer 104 is removed by etching or any other suitable process.

[0146] In some embodiments, such as Figure 28 As shown, after the etch stop layer 104 is removed, a portion of the first seed layer 106 and a portion of the conductive material 108 protrude from the dielectric layer 102g. In some embodiments, such as Figure 29 As shown, after the etch stop layer 104 is removed, a portion of the first seed layer 106, a portion of the conductive material 108, and a portion of the additional dielectric material 109 are removed.

[0147] Please refer to Figure 30 or Figure 31 ,in accordance with Figure 8 In step S211, the portion of conductive material 108 protruding from dielectric layer 102g is removed to form a bonding pad 102d adjacent to conductive plug 102c and surrounded by dielectric layer 102g. In some embodiments, the portions of conductive material 108 and first seed layer 106 protruding from dielectric layer 102g are removed by etching, planarization, CMP, or any other suitable process. In some embodiments, bonding pad 102d is formed including a seed layer 102e and a bonding pad 102f. Bonding pad 102d contacts conductive plug 102c. In some embodiments, as Figure 31 As shown, the portion of the additional dielectric material 109 protruding from the dielectric layer 102g is removed; as a result, a remaining portion of the additional dielectric material 109 is bonded to the dielectric layer 102g.

[0148] In some embodiments, after the bonding pad 102d is formed, as Figure 32As shown, a second seed layer 110 is disposed on the bonding pad 102d, the conductive plug 102c, and the dielectric layer 102g. In some embodiments, the second seed layer 110 is a single layer or a composite stack, comprising materials such as copper, titanium, tungsten, or combinations thereof. In some embodiments, the second seed layer 110 is formed by deposition, PVD, or any other suitable process.

[0149] In some embodiments, after the second seed layer 110 is deposited, such as Figure 33 As shown, a third patterned photoresist 111 is disposed on the second seed layer 110. In some embodiments, the fabrication technique of the third patterned photoresist 111 includes disposing a photoresist material on the second seed layer 110; covering a portion of the photoresist material; and then removing a plurality of exposed portions of the photoresist material to pattern the photoresist material, thereby forming the third patterned photoresist 111. In some embodiments, a portion of the second seed layer 110 is exposed via the third patterned photoresist 111. In some embodiments, the photoresist material is disposed by spin coating or any other suitable process.

[0150] In some embodiments, such as Figure 34 and Figure 35 As shown, a conductive bump 103 is formed on the portion of the second seed layer 110 exposed via the third patterned photoresist 111. In some embodiments, such as Figure 34 As shown, a metal layer 103b, a barrier layer 103c, and a solder assembly 103d are sequentially disposed on the portion of the second seed layer 110 exposed by the third patterned photoresist 111. In some embodiments, the metal layer 103b and the barrier layer 103c are formed by electroplating, sputtering, deposition, or any other suitable process.

[0151] In some embodiments, the metal layer 103b comprises a conductive material, such as copper, silver, gold, or the like. In some embodiments, the barrier layer 103c comprises titanium, titanium nitride, tantalum, tantalum nitride, nickel, or the like. In some embodiments, the solder assembly 103d is fabricated using techniques including pasting, deposition, or any suitable process. In some embodiments, the solder assembly 103d comprises tin, lead, silver, copper, nickel, or the like. In some embodiments, the solder assembly 103d undergoes a single-pass soldering process to become dome-shaped.

[0152] In some embodiments, after the metal layer 103b, the barrier layer 103c, and the solder assembly 103d are disposed, as... Figure 35 As shown, the third patterned photoresist 111 is removed. In some embodiments, the third patterned photoresist 111 is removed by etching, stripping, or any suitable process.

[0153] In some embodiments, a portion of the second seed layer 110 exposed through the metal layer 103b, barrier layer 103c, and solder assembly 103d is removed to form a lower bump metal layer 103a. In some embodiments, this portion of the second seed layer 110 exposed through the metal layer 103b, barrier layer 103c, and solder assembly 103d is removed by etching or any suitable process. In some embodiments, a conductive bump 103 is formed including the lower bump metal layer 103a, metal layer 103b, barrier layer 103c, and solder assembly 103d. In some embodiments, such as Figure 36 As shown, a bonding wire 112 is disposed and bonded to a bonding pad 102d. The bonding wire 112 electrically connects the semiconductor structure 100 to an external circuit via the bonding pad 102d.

[0154] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a redistribution layer disposed on the substrate and including a dielectric layer, a conductive plug, and a bonding pad, the dielectric layer being disposed on the substrate, the conductive plug extending within the dielectric layer, the bonding pad being adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed on the conductive plug; wherein the bonding pad at least partially contacts the conductive plug and the conductive bump.

[0155] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate; and a redistribution layer disposed on the first substrate, and including a dielectric layer, a conductive plug, and a bonding pad. The dielectric layer is disposed on the first substrate, the conductive plug extends within the dielectric layer, and the bonding pad is surrounded by the dielectric layer and contacts the conductive plug; wherein the conductive plug is at least partially surrounded by the bonding pad.

[0156] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The fabrication method includes providing a substrate and a redistribution layer disposed on the substrate, wherein the redistribution layer has a dielectric layer and a conductive plug, a grounding layer disposed on the substrate, and the conductive plug extending within the dielectric layer; disposing an etch stop layer on the redistribution layer; disposing a first patterned photoresist on the etch stop layer; removing a portion of the dielectric layer and a portion of the etch stop layer exposed via the first patterned photoresist; removing the first patterned photoresist; disposing a first seed layer on the etch stop layer and a portion of the dielectric layer exposed via the first patterned photoresist; disposing a second patterned photoresist on the first seed layer; disposing a conductive material on a portion of the first seed layer exposed via the second patterned photoresist; removing the second patterned photoresist; removing the etch stop layer; and removing a portion of the conductive material protruding from the dielectric layer to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer.

[0157] In summary, because the bonding pad is located adjacent to the conductive plug in the redistribution layer, it can accommodate an external interconnect structure, such as a wire bond. Furthermore, the bonding pad can be formed in various shapes to accommodate external interconnect structures oriented in the same direction as the portion surrounding the conductive plug. Therefore, a flexible interconnect and wiring configuration for the semiconductor structure can be achieved.

[0158] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0159] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor structure, comprising: One base; A redistribution layer is disposed on the substrate and includes a dielectric layer, a conductive plug, and a bonding pad. The dielectric layer is disposed on the substrate, the conductive plug extends within the dielectric layer, and the bonding pad is adjacent to the conductive plug and surrounded by the dielectric layer. A conductive bump is provided on the conductive plug; The bonding pad at least partially contacts the conductive plug and the conductive bump; A first portion of a second surface of the bonding pad is covered by the conductive bump, a second portion of the second surface is exposed via the dielectric layer and through the conductive bump, and the first portion is smaller than the second portion; It also includes a bonding line disposed on the second portion of the bonding pad and bonded to the bonding pad.

2. The semiconductor structure of claim 1, wherein a first surface of the conductive plug and the second surface of the bonding pad are exposed via the dielectric layer.

3. The semiconductor structure of claim 2, wherein the first surface of the conductive plug and the second surface of the bonding pad are coplanar.

4. The semiconductor structure of claim 2, wherein the first surface of the conductive plug and the second surface of the bonding pad contact a seed layer of the conductive bump.

5. The semiconductor structure of claim 2, wherein the first surface of the conductive plug, the second surface of the bonding pad, and a third surface of the dielectric layer are coplanar.

6. The semiconductor structure of claim 2, wherein the first surface of the conductive plug is completely covered by the conductive bump.

7. The semiconductor structure of claim 1, wherein an upper cross-section of the bonding pad has an annular shape, a fan shape, or a polygonal shape.

8. The semiconductor structure of claim 1, wherein the height of the conductive plug is greater than the thickness of the bonding pad.

9. The semiconductor structure of claim 1, wherein the redistribution layer has a conductive component electrically connecting the conductive plug to the substrate.

10. The semiconductor structure of claim 9, wherein the conductive component is electrically connected to the conductive bump via the conductive plug.

11. The semiconductor structure of claim 9, wherein the conductive component is electrically connected to the bonding pad via the conductive plug.

12. A semiconductor structure, comprising: A first base; as well as A redistribution layer is disposed on the first substrate and includes a dielectric layer, a conductive plug and a bonding pad. The dielectric layer is disposed on the first substrate, the conductive plug extends within the dielectric layer, and the bonding pad is surrounded by the dielectric layer and contacts the conductive plug. The conductive plug is at least partially surrounded by the bonding pad; The bonding pad includes a first bonding pad and a second bonding pad, the second bonding pad being separated from the first bonding pad, and the conductive plug being disposed between the first bonding pad and the second bonding pad. It also includes a conductive bump that covers the conductive plug and partially covers the bonding pad; It also includes a bonding line disposed on the bonding pad and engaged with the bonding pad.

13. The semiconductor structure of claim 12, wherein the width of the conductive plug is smaller than the width of the conductive bump.

14. The semiconductor structure of claim 12, wherein an interface between the conductive plug and the bonding pad is disposed under the conductive bump.

15. The semiconductor structure of claim 12, wherein the conductive bump is disposed on an interconnect structure of a second substrate and is engaged with the interconnect structure of the second substrate.

16. The semiconductor structure of claim 12, wherein the first substrate includes a plurality of elements disposed thereon and a plurality of insulators separating the plurality of elements.

17. A method for fabricating a semiconductor structure, comprising: A substrate and a redistribution layer are provided, the redistribution layer being disposed on the substrate, wherein the redistribution layer has a dielectric layer and a conductive plug, the dielectric layer being disposed on the substrate and the conductive plug extending within the dielectric layer; An etch stop layer is provided on the redistribution layer; A first patterned photoresist is applied on the etch stop layer; Remove a portion of the dielectric layer and a portion of the etch stop layer exposed via the first patterned photoresist; Remove the first patterned photoresist; A first seed layer is disposed on the etch stop layer and on a portion of the dielectric layer exposed via the first patterned photoresist; A second patterned photoresist is applied to the first seed layer; A conductive material is disposed on a portion of the first seed layer exposed via the second patterned photoresist; Remove the second patterned photoresist; Remove the etch stop layer; as well as A portion of the conductive material protruding from the dielectric layer is removed to form a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; The bonding pad includes a first bonding pad and a second bonding pad, the second bonding pad being separated from the first bonding pad, and the conductive plug being disposed between the first bonding pad and the second bonding pad. Also includes: A second seed layer is disposed on the bonding pad, the conductive plug, and the dielectric layer; A third patterned photoresist is disposed on the second seed layer; and A conductive bump is formed on a portion of the second seed layer exposed via the third patterned photoresist.

18. The method for fabricating a semiconductor structure as claimed in claim 17, wherein the first seed layer disposed on the etch stop layer contacts the conductive plug.

19. The method for fabricating a semiconductor structure as claimed in claim 17, wherein the bonding pad comprises the first seed layer and the conductive material.

20. The method of fabricating a semiconductor structure as claimed in claim 17, wherein after the removal of the second patterned photoresist, the portion of the conductive material protrudes from the etch-stop layer.

21. The method of fabricating a semiconductor structure as claimed in claim 17, wherein removing the portion of the dielectric layer exposed via the first patterned photoresist includes forming an opening to extend into the dielectric layer and disposed adjacent to the conductive plug.

22. The method of fabricating a semiconductor structure as claimed in claim 21, wherein after the opening is formed, the conductive plug is at least partially exposed.

23. The method of fabricating a semiconductor structure as claimed in claim 21, wherein the opening surrounds the conductive plug.

24. The method for fabricating a semiconductor structure as claimed in claim 23, wherein the second patterned photoresist fills a portion of the opening.

25. The method for fabricating a semiconductor structure as claimed in claim 23, wherein the second patterned photoresist is at least partially surrounded by the first seed layer.

26. The method for preparing the semiconductor structure as described in claim 23, further comprising: A dielectric material is disposed within the opening and on the etch stop layer; as well as Remove a portion of the dielectric material that is disposed on the etch stop layer.

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