Battery formation and grading reference generation, data review equipment and review method

Abstract

The application discloses a battery formation and rationing reference generation and data back-checking equipment, which comprises a basic circuit and an acquisition circuit, the basic circuit comprises a first digital-to-analog converter, a second digital-to-analog converter, a first resistor, a second resistor and an operational amplifier, the acquisition circuit comprises an analog-to-digital converter, a multi-channel analog switch and an MCU processor, battery channels are divided into multiple groups, each group of battery channels corresponds to a set of multi-channel analog switches, each battery channel is electrically connected with a corresponding channel detection port of the analog-to-digital converter through the set of multi-channel analog switches, and a signal output end of the analog-to-digital converter is electrically connected with a signal input end of the MCU processor through an SPI bus; the application further comprises a back-checking method, which comprises the following steps: establishing an output reference; realizing independent calibration of each battery channel; acquiring battery data and performing numerical operation. The application has the beneficial effects of simple hardware, low cost, batch application in occasions with more channels of single equipment and cost reduction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery production, and particularly relates to a battery formation and capacity grading reference generation, data back-checking equipment and back-checking method. BACKGROUND

[0002] In the production process of lithium battery cells, a formation and capacity grading equipment is needed to perform formation and capacity grading treatment on the lithium battery cells. Formation refers to a process of activating the internal positive and negative materials of the lithium battery through certain charging and discharging methods, and improving the charging and discharging performance and comprehensive performance such as self-discharge and storage of the lithium battery. Capacity grading refers to charging and discharging the activated battery, and classifying the battery according to the size of the cell capacity. As a formation and capacity grading detection equipment, especially a capacity grading equipment, a very high control and acquisition precision is often required, and the industry generally requires a current and voltage precision of not less than 1 / 10,000. In order to improve the production efficiency, one equipment often performs formation and capacity grading on up to 400 channels of batteries at a time. In order to meet the control precision, the industry currently designs a 16-bit digital-to-analog converter as the voltage and current reference of the charging and discharging controller for each channel, and uses an analog-to-digital converter with more than 16 effective bits for each channel for terminal acquisition. This not only needs to increase the back-checking equipment, but also the high-precision digital-to-analog converter and analog-to-digital converter are relatively expensive, which makes the cost of the battery formation and capacity grading reference generation and data back-checking very high, and is not conducive to expanding production. SUMMARY

[0003] In order to solve the above problems, the present application provides a low-cost battery formation and capacity grading reference generation and data back-checking method, which adopts a combination of a common first-level 12-bit digital-to-analog converter and a battery channel independent 10-bit low-precision second-level digital-to-analog converter to provide a control reference, and uses a high-precision 16-bit analog-to-digital converter to acquire voltage and current data. Different battery channels adopt an analog switch control switching mode, effectively reducing the number of back-checking equipment and greatly reducing the electrical cost of the equipment.

[0004] The application discloses a battery formation and component content reference generation and data back-checking device, which is characterized by comprising a basic circuit and a collection circuit.

[0005] Preferably, the first-stage digital-to-analog converter is a 12-bit first-stage digital-to-analog converter, and the second-stage digital-to-analog converter is a 10-bit digital-to-analog converter.

[0006] Preferably, the analog switches are 8-channel analog switches.

[0007] The application further discloses a battery formation and component content reference generation and data back-checking method.

[0008] Step 1: establishing an output reference of high-precision battery formation and component content by the basic circuit, including a current reference and a voltage reference, wherein a calculation formula of the control reference voltage is as follows:

[0009] V = α * V1 - β * V2 (1);

[0010] V is the control reference voltage of the operational amplifier, V1 is an actual output voltage of the first-stage digital-to-analog converter, V2 is an actual voltage output value of the second-stage digital-to-analog converter, α is an amplification multiple of the first-stage digital-to-analog converter, and β is an amplification multiple of the second-stage digital-to-analog converter.

[0011] Step 2: establishing a calibration model by a linear calibration compensation algorithm, and calculating K and B in the calibration model by a sending value, an actual measurement value and a collection value at a calibration moment, wherein K is a proportional coefficient of the linear calibration compensation, B is a direct current bias, independent calibration of each battery channel is realized, in order to further improve the precision, quantization error of the first-stage digital-to-analog converter is compensated into the second-stage digital-to-analog converter, so as to eliminate error caused by device drift or temperature drift, and a formula of the calibration model is as follows:

[0012] V = K (V1 + VM V2)+B (2);

[0013] V1=V+V M (3)

[0014]

[0015] In the formula, V is the actual output value of the system after calibration, i.e. the expected value; V1 is the actual output voltage of the first-stage digital-to-analog converter; V2 is the actual voltage output value of the second-stage digital-to-analog converter; V is the median value of the output of the second-stage digital-to-analog converter, used to realize positive and negative offset calibration of the voltage; K is dimensionless, a proportional coefficient, and other units are mV. M

[0016] Step 3, collect the battery data of each battery channel, and transmit the battery data to the MCU processor for numerical operation, wherein the collection of the battery data of each battery channel is performed according to the following process:

[0017] (a) divide the N battery channels into multiple groups;

[0018] (b) use the analog-to-digital converter in the acquisition circuit to collect the battery data of each battery channel in the first group;

[0019] (c) switch to each battery channel of the next group through the multi-channel analog switch in the acquisition circuit, and sequentially complete the data collection of all battery channels;

[0020] (d) the MCU processor reads the battery voltage and current values collected by the analog-to-digital converter through the SPI bus.

[0021] Preferably, the analog-to-digital converter in step 3 is an 8-channel 16-bit analog-to-digital converter.

[0022] The beneficial effects of the present application are: by using a 12-bit first-stage digital-to-analog converter and a 10-bit second-stage digital-to-analog converter, a high-precision battery formation and grading reference is established, and through a software linear calibration compensation algorithm, independent calibration of the battery channel is realized. For battery sampling and rechecking, the battery data collection is realized through the multi-channel analog switch switching mode. This scheme has simple hardware and low cost, and is suitable for batch application in occasions with more channels in a single device, which can greatly reduce the cost while meeting the functional performance requirements of customers. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic diagram of the basic circuit of the present application.

[0024] Figure 2 is a schematic diagram of the sampling circuit of the present application. DETAILED DESCRIPTION ​

[0025] The specific implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiments of the present application, and is not used to limit the embodiments of the present application.

[0026] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0027] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0028] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0029] In the present application, unless otherwise specifically defined and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected or in communication with each other; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0030] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature can be "above", "over" and "on" the second feature, which can be that the first feature is directly above or obliquely above the second feature, or only means that the first feature is horizontally higher than the second feature. The first feature can be "below", "under" and "under" the second feature, which can be that the first feature is directly below or obliquely below the second feature, or only means that the first feature is horizontally lower than the second feature.

[0031] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0032] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with exemplary embodiments.

[0033] As shown in Figure 1 , 2 , a battery formation and data review equipment according to the present application includes a basic circuit and a collection circuit. The basic circuit includes a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a first resistor R1, a second resistor R2 and an operational amplifier U1. Each channel corresponds to a second digital-to-analog converter DAC2. The output end of the first digital-to-analog converter DAC1 is connected in series with the inverting input end 6 of the operational amplifier U1, and the second resistor R2 is connected in parallel between the inverting input end 6 and the output end 7 of the operational amplifier U1. The second digital-to-analog converter DAC2 is electrically connected to the non-inverting input end 5 of the operational amplifier U1, and the output end of the operational amplifier U1 is electrically connected to the voltage input end of the charge and discharge controller. The collection circuit includes an analog-to-digital converter ADC, a multi-channel analog switch 2 and an MCU processor 4. The analog-to-digital converter ADC is a multi-channel analog-to-digital converter. N battery channels are divided into multiple groups, and each group of battery channels corresponds to a set of multi-channel analog switches 2. Each battery channel in each group is electrically connected to the corresponding channel detection port of the analog-to-digital converter ADC through a set of multi-channel analog switches 2. The signal output end of the analog-to-digital converter ADC is electrically connected to the signal input end of the MCU processor 4 through the SPI bus 3.

[0034] The battery formation and component distribution reference generation and data review method comprises the following steps:

[0035] Step 1: an output reference of high-precision battery formation and component distribution is established by using a basic circuit, including a current reference and a voltage reference;

[0036] The basic circuit comprises a 12-bit first digital-to-analog converter DAC1, a plurality of 10-bit second digital-to-analog converters DAC2, a first resistor R1, a second resistor R2, and an operational amplifier U1, each channel corresponds to a second digital-to-analog converter, the first resistor R1 is connected in series between the output end of the first digital-to-analog converter DAC1 and the inverting input end 6 of the operational amplifier U1, and the second resistor R2 is connected in parallel between the inverting input end 6 and the output end 7 of the operational amplifier U1; the second digital-to-analog converter DAC2 is electrically connected with the non-inverting input end 5 of the operational amplifier U1, and the control reference voltage output from the output end 7 of the operational amplifier U1 is used as the reference voltage V of the charge-discharge controller, wherein the calculation formula of the control reference voltage V is:

[0037] V = α * V1 - β * V2 (1);

[0038] V is the control reference voltage of the operational amplifier; V1 is the actual output voltage of the first digital-to-analog converter; V2 is the actual voltage output value of the second digital-to-analog converter; α is the amplification multiple of the first digital-to-analog converter; and β is the amplification multiple of the second digital-to-analog converter;

[0039] Step 2: a calibration model is established by using a linear calibration compensation algorithm, and K and B in the calibration model are calculated by using the sending value, the actual measurement value, and the collection value at the calibration time, wherein the K value is the proportional coefficient of the linear calibration compensation, and B is the direct current bias, so as to realize independent calibration of each battery channel, in order to further improve the precision, the quantization error of the first digital-to-analog converter is compensated into the second digital-to-analog converter, so as to eliminate the error caused by the device drift or temperature drift, and the formula of the calibration model is:

[0040] V = K (V1 + V M -V2) + B (2);

[0041] V1 = V + V M (3)

[0042]

[0043] In the formula, V is the output control reference voltage of the operational amplifier, that is, the actual voltage output value of the operational amplifier; V1 is the actual output voltage of the first digital-to-analog converter; V2 is the actual voltage output value of the second digital-to-analog converter; V MThe median value of the output of the second digital-to-analog converter is used to realize positive and negative bias calibration of the voltage; K and B are dimensionless, proportional coefficients, and other units are mV.

[0044] Step 3, collect the battery data of each battery channel, and transmit the battery data to the MCU processor for numerical operation, wherein the collection of the battery data of each battery channel is performed according to the following process:

[0045] (a) divide the N battery channels into multiple groups;

[0046] (b) use the analog-to-digital converter ADC in the acquisition circuit to collect the battery data of each battery channel in the first group;

[0047] (c) switch to each battery channel of the next group through the multi-channel analog switch 2 in the acquisition circuit, and sequentially complete the data acquisition of all battery channels, and then repeat from the beginning;

[0048] (d) the MCU processor 3 reads the battery values collected by the analog-to-digital converter through the SPI bus 4.

[0049] In some embodiments of the application, the analog-to-digital converter in step 3 is an 8-channel 16-bit analog-to-digital converter.

[0050] As Figure 1 The basic circuit shown in the figure, R2 and R1 are the control proportional resistors of the first DAC and the second DAC, and the configuration of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can be adjusted by changing the resistance ratio of R1 and R2 to achieve the accuracy requirement of the reference. Too large coefficient will affect the overall output accuracy, and too small coefficient will affect the correction range of the system. Taking voltage output as an example, the amplification factor of the first digital-to-analog converter DAC1 is alpha = 201 / 200, and the amplification factor of the second digital-to-analog converter DAC2 is beta = 1 / 200, that is, R1 is 300K and R2 is 1.5K. According to formula (1), the output control reference voltage V' of the operational amplifier is V' = 201 / 200*V1-1 / 200*V2. As can be seen from the formula, the actual voltage output value V2 of the single-channel independent 10-bit second digital-to-analog converter DAC2 combined with the proportional reduction of 1 / 200 can theoretically realize the control requirement of 16-bit reference voltage V', and the voltage V' and the current formula are the same. Only the voltage needs to be converted into the corresponding current, which is not described here.

[0051] In some embodiments of the application, the first digital-to-analog converter is a 12-bit first digital-to-analog converter; and the second digital-to-analog converter is a 10-bit digital-to-analog converter.

[0052] In some embodiments of the present application, the analog-to-digital converters are each an 8-channel 16-bit analog-to-digital converter, and the analog switch is an 8-channel analog switch.

[0053] In the present application, the control reference voltage V' is distributed in two parts: the actual output voltage V1 output by the primary digital-to-analog converter DAC1 and the actual output voltage V2 output by the secondary digital-to-analog converter DAC2, wherein the primary digital-to-analog converter DAC1 is commonly shared by the entire device, and the secondary digital-to-analog converter DAC2 is independently configured for each battery channel.

[0054] Since V1 is the actual output voltage of the primary digital-to-analog converter DAC1 of the entire device, its value is always expected to be the actual output value V, plus the median offset V M Therefore, the actual voltage output value of the primary digital-to-analog converter DAC1 is V1 = V + V M offset V, so that the actual voltage output value of the secondary digital-to-analog converter DAC2 can be obtained as Since the 10-bit precision of the primary digital-to-analog converter DAC1 is large, it will bring in a large quantization error, so it is necessary to compensate the quantization error of the primary DAC into the secondary digital-to-analog converter DAC2.

[0055] Each battery channel needs to collect voltage and current values, and at least 2*N (N is the number of battery channels) analog quantities need to be collected for a device. In order to reduce the number of analog-to-digital converters ADC, the present application uses a single device with an 8-channel 16-bit analog-to-digital converter, i.e. the battery channels are divided into multiple groups, and each group of battery channels is connected to a set of multi-channel analog switches. In this way, the analog-to-digital converter completes the sampling of the data of 4 battery channels at a time, and then controls the corresponding multi-channel analog switch to switch to the next group of 4 battery channels, and the data collection of all battery channels is completed in turn, and then the process is repeated from the beginning. The MCU processor reads the values collected by the ADC digital-to-analog converter through the SPI bus.

[0056] Although embodiments of the present application have been shown and described above, it should be understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and those of ordinary skill in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A battery formation and capacity reference generation and data verification device, characterized in that: The system includes a basic circuit and a data acquisition circuit. The basic circuit includes a first-stage digital-to-analog converter (DAC), a second-stage DAC, a first resistor, a second resistor, and an operational amplifier. Each channel corresponds to a second-stage DAC. The first-stage DAC is electrically connected to the inverting input of the operational amplifier, and the second-stage DAC is electrically connected to the non-inverting input of the operational amplifier. The output of the operational amplifier is electrically connected to the voltage input of the charge / discharge controller. The control reference voltage output by the operational amplifier serves as the reference voltage for the charge / discharge controller. The data acquisition circuit includes an analog-to-digital converter (ADC), a multi-channel analog switch, and an MCU processor. The ADC is a multi-channel ADC, with the battery channels divided into multiple groups. Each group of battery channels corresponds to a set of multi-channel analog switches, and each battery channel in each group is electrically connected to the corresponding channel detection port of the ADC through a set of multi-channel analog switches. The signal output of the ADC is electrically connected to the signal input of the MCU processor via an SPI bus.

2. The battery formation and capacity reference generation and data verification equipment as described in claim 1, characterized in that: The first-level digital-to-analog converter is a 12-bit digital-to-analog converter; the second-level digital-to-analog converter is a 10-bit digital-to-analog converter.

3. The battery formation and capacity reference generation and data verification equipment as described in claim 2, characterized in that: The analog-to-digital converters are all 8-channel 16-bit analog-to-digital converters, and the analog switches are 8-channel analog switches.

4. A method for generating battery composition and capacity references and for re-verifying data, characterized in that, Includes the following steps: Step 1: Establish a high-precision battery classification and capacity setting output reference using basic circuitry. This output reference includes a current reference and a voltage reference. The formula for calculating the control reference voltage is as follows: V=α*V1-β*V2 (1); V is the control reference voltage of the operational amplifier; V1 is the actual output voltage of the first-stage digital-to-analog converter. V2 is the actual voltage output value of the second-stage digital-to-analog converter; α is the amplification factor of the first-stage digital-to-analog converter; β is the amplification factor of the two-stage digital-to-analog converter; Step 2 establishes a calibration model using a linear calibration compensation algorithm. K and B in the calibration model are calculated using the transmitted, measured, and acquired values ​​at the calibration time. K is the proportional coefficient for linear calibration compensation, and B is the DC bias, enabling independent calibration of each battery channel. To further improve accuracy, the quantization error of the first-stage digital-to-analog converter is compensated for in the second-stage digital-to-analog converter to eliminate errors caused by device drift or temperature drift. The formula for the calibration model is: V=K(V1+V M -V2)+B (2); V1=V+V M (3) In the formula, V is the actual output value after system calibration, i.e., the expected value; V1 is the actual output voltage of the first-stage digital-to-analog converter. V2 is the actual voltage output value of the two-stage digital-to-analog converter; V M The median value of the output of the two-stage digital-to-analog converter is used to achieve positive and negative bias calibration of the voltage; K is dimensionless, a proportionality coefficient, and other units are in mV; Step 3: Collect battery data from each battery channel and transmit the battery data to the MCU processor for numerical calculation. The collection of battery data from each battery channel is performed according to the following process: (a) Divide the N battery channels into multiple groups; (b) Use the analog-to-digital converter in the acquisition circuit to acquire battery data for each battery channel in the first group; (c) Switch to each battery channel of the next group by using the multi-channel analog switch in the acquisition circuit, and complete the data acquisition of all battery channels in turn. Then repeat from the beginning until all battery data of all battery channels have been acquired. (d) The MCU processor reads the battery values ​​collected by the analog-to-digital converter via the SPI bus.

5. The battery formation and capacity reference generation and data verification method as described in claim 4, characterized in that: The analog-to-digital converter in step 3 is an 8-channel 16-bit analog-to-digital converter.

Images