Logic hardware power-on and power-off monitoring and protection circuit

Abstract

This invention discloses a logic hardware power-on and power-off monitoring and protection circuit, comprising M levels of hardware protection units. When M is greater than 2, each level of hardware protection unit conforms to a preset design rule. The preset design rule is as follows: when the number of design levels of the hardware protection unit to be designed is ≥2 and <M, an AND logic relationship is formed between the power undervoltage alarm monitoring signals of all preceding hardware protection units and the overall system fault monitoring signal to output the intermediate output signal of the hardware protection unit to be designed. Conversely, an OR logic relationship is formed between the intermediate output signal of the hardware protection unit to be designed and the overall system fault monitoring signal to output the output signal of the hardware protection unit to be designed. This invention uses a fully hardware logic circuit and a clever and rigorous logic link to achieve logic locking under power-on and power-off conditions, resulting in low cost, high reliability, and easy expansion.

Description

Technical Field

[0001] This invention relates to the field of automation control technology, and in particular to a logic hardware power-on and power-off monitoring and protection circuit. Background Technology

[0002] Industrial products frequently encounter abnormal power outages during use, such as power grid tripping, abnormal short circuits, and power supply failures. For high-precision products with strict internal power supply timing requirements, such as the circuit modules used in lasers, abnormal power outages can cause the control chip to enter an I / O uncontrolled state, leading to timing disorders and even product damage. This is particularly prominent in certain precision laser products with high precision requirements, urgently requiring a reliable all-hardware power-down protection solution that can still maintain normal logic locking until complete shutdown even when the main control chip loses its logic lock after an abnormal power outage.

[0003] In existing applications, only power-down logic can be addressed. The two most common methods for handling power-down timing logic are: one is to use a supercapacitor to power the entire system, maintaining power after an abnormal power outage while the main chip shuts down the logic; the other is to use a UPS to power the entire system, with a similar mechanism to the supercapacitor solution. Both of these solutions require an external independent power distribution module, increasing system complexity, cost, size, and weight. Furthermore, manually maintaining power to the protected product after an abnormal power outage is not suitable in certain special circumstances, causing the product to remain operational for a period after the external power supply is cut off, violating the product's inherent characteristics. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that the existing methods for solving power-down timing logic only support logical power-down and cannot support logical power-up at the same time. In addition, they require an external independent power distribution module, which increases the complexity, cost, size and weight of the system. At the same time, the reliability is low and it is not easy to expand and use.

[0005] To solve the above-mentioned technical problems, the present invention provides a logic hardware power-on and power-off monitoring and protection circuit, including M-level hardware protection units. When M is greater than 2, each level of hardware protection unit conforms to a preset design rule.

[0006] The preset design rules are as follows:

[0007] When the number of design levels of the hardware protection unit to be designed is ≥2 and <M, an AND logic relationship is formed between the power undervoltage alarm monitoring signals of all hardware protection units before the hardware protection unit to be designed and the total system fault monitoring signal, so as to output the intermediate output signal of the hardware protection unit to be designed. An OR logic relationship is formed between the intermediate output signal of the hardware protection unit to be designed and the power undervoltage alarm monitoring signal of the next level hardware protection unit to be designed, so as to output the output signal of the hardware protection unit to be designed.

[0008] When the number of design levels of the hardware protection unit to be designed is 1, an OR logic relationship is formed between the power undervoltage alarm monitoring signal of the secondary hardware protection unit and the system fault total monitoring signal to output the output signal of the primary hardware protection unit.

[0009] When the number of design levels of the hardware protection unit to be designed is M, an AND logic relationship is formed between the power undervoltage alarm monitoring signal of the M-1 level hardware protection unit and the power undervoltage alarm monitoring signal of the M-2 level hardware protection unit to output the intermediate output signal of the M level hardware protection unit. An AND logic relationship is also formed between the intermediate output signal of the M level hardware protection unit and the system fault total monitoring signal to output the output signal of the M level hardware protection unit.

[0010] Preferably, the AND logic relationship in the preset design rule is implemented by connecting a single multi-input pin AND gate, and the OR logic relationship is implemented by an OR gate.

[0011] Preferably, the AND logic relationship in the preset design rule is implemented by sequentially connecting multiple AND gates, and the OR logic relationship is implemented by an OR gate.

[0012] Preferably, when M equals 2, the logic hardware power-on and power-off monitoring and protection circuit includes a primary hardware protection unit and a secondary hardware protection unit;

[0013] The first-level hardware protection unit includes a first logic OR gate. The power undervoltage alarm monitoring signal of the second-level hardware protection unit and the system fault total monitoring signal are connected by the first logic OR gate to form an OR logic relationship, so as to output the output signal of the first-level hardware protection unit.

[0014] The secondary hardware protection unit includes a first AND gate. The power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault total monitoring signal are connected by the first AND gate to form an AND logic relationship, so as to output the output signal of the secondary hardware protection unit.

[0015] Preferably, when M is 3, the logic hardware power-on and power-off monitoring and protection circuit includes a first-level hardware protection unit, a second-level hardware protection unit, and a third-level hardware protection unit.

[0016] The primary hardware protection unit includes a second logic OR gate. The power undervoltage alarm monitoring signal of the secondary hardware protection unit and the system fault total monitoring signal are connected by the second logic OR gate to form an OR logic relationship, so as to output the output signal of the primary hardware protection unit.

[0017] The secondary hardware protection unit includes a second AND gate and a third OR gate. The power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault total monitoring signal are connected by an AND logic relationship through the second AND gate to output the intermediate output signal of the secondary hardware protection unit. The intermediate output signal of the secondary hardware protection unit and the power undervoltage alarm monitoring signal of the tertiary hardware protection unit are connected by an OR logic relationship through the third OR gate to output the output signal of the secondary hardware protection unit.

[0018] The three-level hardware protection unit includes a third AND gate and a fourth AND gate. The power undervoltage alarm monitoring signal of the first-level hardware protection unit and the power undervoltage alarm monitoring signal of the second-level hardware protection unit are ANDed through the third AND gate to output the intermediate output signal of the three-level hardware protection unit. The intermediate output signal of the three-level hardware protection unit is ANDed with the system fault total monitoring signal through the fourth AND gate to output the output signal of the three-level hardware protection unit.

[0019] Preferably, the logic hardware power-on and power-off monitoring and protection circuit further includes multiple system fault monitoring signal acquisition units, and all the system fault monitoring signal acquisition units form an AND logic relationship to output the total system fault monitoring signal.

[0020] Preferably, each of the system fault monitoring signal acquisition units includes at least one of a watchdog monitoring signal, a system lock monitoring signal, a system alarm monitoring signal, and a machine switch monitoring signal, and the monitoring signals in the system fault monitoring signal acquisition unit are connected by an AND logic relationship.

[0021] Preferably, each power undervoltage alarm monitoring signal input terminal of each hardware protection unit is connected to a comparator;

[0022] The input signal terminal of the comparator is connected to the original acquired power undervoltage alarm monitoring signal of the corresponding power supply undervoltage alarm monitoring signal. The reference signal input terminal of the comparator is connected to the undervoltage protection point voltage. The output terminal of the comparator outputs the corresponding power undervoltage alarm monitoring signal.

[0023] Preferably, the undervoltage protection point voltage is 90% of the normal operating voltage of the corresponding power supply undervoltage alarm monitoring signal.

[0024] Preferably, the output of each hardware protection unit is further connected to an operational amplifier and an NMOS transistor. The positive input of the operational amplifier is connected to the output signal of the hardware protection unit at that stage, the inverting input of the operational amplifier is grounded, the output of the operational amplifier is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the power supply terminal, and the source of the NMOS transistor outputs a control signal to control the power supply of the corresponding stage to be turned on or off.

[0025] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0026] The logic hardware power-on and power-off monitoring and protection circuit provided in this embodiment of the invention uses a fully hardware logic circuit and a clever and rigorous logic link to achieve logic locking in the event of a power failure, with virtually no additional cost, while simultaneously achieving highly reliable power-on and power-off logic protection functions. Furthermore, by reasonably configuring multi-level hardware protection units of the logic circuit, power-off protection logic can be implemented while also taking into account power-on protection logic functions. When a system fault occurs, it can be quickly identified and an emergency shutdown can be achieved, solving the problems of existing power-off methods being bulky, redundant, unreliable, and difficult to expand.

[0027] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit according to Embodiment 1 of the present invention.

[0030] Figure 2 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit when M is 2 in Embodiment 1 of the present invention.

[0031] Figure 3 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit when M is 3 in Embodiment 1 of the present invention.

[0032] Figure 4 A schematic diagram of a circuit structure for a single system fault monitoring signal acquisition unit in Embodiment 1 of the present invention is shown. Detailed Implementation

[0033] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in the various embodiments of the present invention can be combined with each other, and the resulting technical solutions are all within the protection scope of the present invention.

[0034] Existing methods for handling power-down timing logic only address the power-down logic itself. The two most common approaches are: one uses a supercapacitor to power the entire system, maintaining power after an abnormal power outage while the main chip shuts down the logic; the other uses a UPS to power the entire system, with a similar mechanism to the supercapacitor solution. Both solutions require an external, independent power distribution module, increasing system complexity, cost, size, and weight. Furthermore, artificially maintaining power to the protected product after an abnormal power outage is not suitable in certain special circumstances, causing the product to remain operational for a period after external power is cut off, violating the product's inherent characteristics. Moreover, the added supercapacitors and UPS are not common industrial materials, increasing uncontrollable risks to system reliability.

[0035] Example 1

[0036] To address the technical problems existing in the prior art, embodiments of the present invention provide a logic hardware power-on and power-off monitoring and protection circuit.

[0037] Figure 1 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit according to Embodiment 1 of the present invention; see reference. Figure 1 As shown, the power-on and power-off monitoring and protection circuit of the logic hardware in this embodiment of the invention includes multiple hardware protection units. The number of hardware protection units is set to M, then M must be greater than or equal to M, and M is a positive integer.

[0038] Figure 2 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit when M is 2 in Embodiment 1 of the present invention; see reference. Figure 2 As shown, when M equals 2, the logic hardware power-on and power-off monitoring and protection circuit includes a primary hardware protection unit and a secondary hardware protection unit.

[0039] The first-level hardware protection unit includes a first logic OR gate OR1. The design of the first-level hardware protection unit is as follows: the power undervoltage alarm monitoring signal of the second-level hardware protection unit and the system fault total monitoring signal are connected by an OR logic relationship through the first logic OR gate OR1 to output the output signal of the first-level hardware protection unit.

[0040] The secondary hardware protection unit includes a first logic AND gate A1. The secondary hardware protection unit is designed such that the power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault monitoring signal are connected by an AND logic relationship through the first logic AND gate A1 to output the output signal of the secondary hardware protection unit.

[0041] Table 1 is the truth table of the logic hardware power-on and power-off monitoring and protection circuit when M equals 2. Referring to Table 1, the operating mode of each level of hardware protection unit in the current logic hardware power-on and power-off monitoring and protection circuit is as follows:

[0042] When the current structural logic hardware power-on and power-off monitoring and protection circuit is powered on in a fault-free state:

[0043] When the system is powered on, the system fault monitoring signal is at a high level, the first logic OR gate OR1 outputs a high-level signal, and the output signal voltage of the first-level hardware protection unit begins to rise. When the output signal of the first-level hardware protection unit is in a state where the voltage is not undervoltage, the first logic AND gate A1 outputs a high-level signal, and the output signal voltage of the second-level hardware protection unit begins to rise. When the output signal of the second-level hardware protection unit is in a state where the voltage is not undervoltage, the current structure logic hardware power-on and power-off monitoring and protection circuits work normally.

[0044] When a system fault occurs in the power-on and power-off monitoring and protection circuit of the current structural logic hardware, the system fault total monitoring signal will trigger a system total input power supply undervoltage alarm, at which point the system fault total monitoring signal will be deactivated.

[0045] When the system loses power, the overall system fault monitoring signal is in an undervoltage alarm state. The first logic AND gate A1 outputs a low level, and the second-level hardware protection unit is turned off. The second-level hardware protection unit is in an undervoltage alarm state. Since the overall system fault monitoring signal is also in an undervoltage alarm state, the first logic OR gate OR1 also outputs a low level signal, and the first-level hardware protection unit is turned off. At this point, all levels of hardware protection units have been turned off.

[0046]

[0047] Table 1

[0048] When M is greater than 2, each hardware protection unit in the logic hardware power-on and power-off monitoring and protection circuit conforms to the preset design rules.

[0049] The further preset design rules are as follows: when the number of design levels of the hardware protection unit to be designed is ≥2 and <M, an AND logic relationship is formed between the power undervoltage alarm monitoring signals of all hardware protection units before the hardware protection unit to be designed and the system fault total monitoring signal, so as to output the intermediate output signal of the hardware protection unit to be designed; and an OR logic relationship is formed between the intermediate output signal of the hardware protection unit to be designed and the power undervoltage alarm monitoring signal of the next level hardware protection unit to be designed, so as to output the output signal of the hardware protection unit to be designed.

[0050] When the number of design levels of the hardware protection unit to be designed is 1, an OR logic relationship is formed between the power undervoltage alarm monitoring signal of the secondary hardware protection unit and the system fault total monitoring signal to output the output signal of the primary hardware protection unit.

[0051] When the number of design levels of the hardware protection unit to be designed is M, an AND logic relationship is formed between the power undervoltage alarm monitoring signal of the M-1 level hardware protection unit and the power undervoltage alarm monitoring signal of the M-2 level hardware protection unit to output the intermediate output signal of the M level hardware protection unit. An AND logic relationship is also formed between the intermediate output signal of the M level hardware protection unit and the system fault total monitoring signal to output the output signal of the M level hardware protection unit.

[0052] It should be noted that the AND logic relationship in the preset design rules can be implemented not only by connecting a single multi-input pin AND gate, but also by connecting multiple AND gates sequentially. Meanwhile, the OR logic relationship is implemented by an OR gate.

[0053] To provide a detailed explanation of the design rules for each level of hardware protection unit in the above-mentioned logic hardware power-on and power-off monitoring and protection circuit, the following explanation uses the structure of each level of hardware protection unit in the logic hardware power-on and power-off monitoring and protection circuit when M equals 3 as an example.

[0054] Figure 3 This diagram illustrates the structure of the logic hardware power-on and power-off monitoring and protection circuit when M is 3 in Embodiment 1 of the present invention; see reference. Figure 3 As shown, when M equals 3, the logic hardware power-on and power-off monitoring and protection circuit includes a first-level hardware protection unit, a second-level hardware protection unit, and a third-level hardware protection unit.

[0055] The first-level hardware protection unit includes a second logic OR gate OR2. The power undervoltage alarm monitoring signal of the second-level hardware protection unit and the system fault total monitoring signal are connected by an OR logic relationship through the second logic OR gate OR2 to output the output signal of the first-level hardware protection unit.

[0056] The secondary hardware protection unit includes a second logic AND gate A2 and a third logic OR gate OR3. The power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault total monitoring signal are connected by an AND logic relationship through the second logic AND gate A2 to output the intermediate output signal of the secondary hardware protection unit. The intermediate output signal of the secondary hardware protection unit is connected by an OR logic relationship with the power undervoltage alarm monitoring signal of the tertiary hardware protection unit through the third logic OR gate OR3 to output the output signal of the secondary hardware protection unit.

[0057] The three-level hardware protection unit includes a third AND gate A3 and a fourth AND gate A4. The power undervoltage alarm monitoring signal of the first-level hardware protection unit and the power undervoltage alarm monitoring signal of the second-level hardware protection unit are ANDed by the third AND gate A3 to output the intermediate output signal of the three-level hardware protection unit. The intermediate output signal of the three-level hardware protection unit is ANDed by the system fault monitoring signal by the fourth AND gate A4 to output the output signal of the three-level hardware protection unit.

[0058] Table 2 is the truth table of the logic hardware power-on and power-off monitoring and protection circuit when M equals 3. Referring to Table 2, the operating mode of each level of hardware protection unit in the current logic hardware power-on and power-off monitoring and protection circuit is as follows:

[0059] When the current structural logic hardware power-on and power-off monitoring and protection circuit is powered on in a fault-free state:

[0060] When the system is powered on, the system fault monitoring signal is at a high level, the second logic OR gate OR2 outputs a high level signal, the first-level hardware protection unit outputs an output signal, and the first-level hardware protection unit is enabled.

[0061] When the output signal voltage of the primary hardware protection unit rises and the system fault monitoring signal is at a high level, the second logic AND gate A2 outputs a high-level signal, the third logic OR gate OR3 outputs a high-level signal, the secondary hardware protection unit outputs an output signal, and the secondary hardware protection unit is enabled.

[0062] When the output signal voltage of the secondary hardware protection unit rises and it is detected that the output signal voltage of the secondary hardware protection unit is not undervoltage, the third logic AND gate A3 outputs a high-level signal because the primary hardware protection unit outputs a high-level signal, and the fourth logic AND gate A4 outputs a high-level signal because the system fault monitoring signal is at a high level. The tertiary hardware protection unit outputs an output signal and the tertiary hardware protection unit is activated.

[0063] When a system fault occurs in the power-on and power-off monitoring and protection circuit of the current structural logic hardware, the system fault total monitoring signal will trigger a system total input power supply undervoltage alarm, at which point the system fault total monitoring signal will be deactivated.

[0064] When the system loses power, the system fault monitoring signal is at a low level, the fourth logic AND gate A4 outputs a low level signal, and the three-level hardware protection unit is turned off.

[0065] The third-level hardware protection unit is in an undervoltage alarm state. Since the system fault monitoring signal is also in an undervoltage alarm state, the second logic AND gate A2 outputs a low level, the third logic OR gate OR3 outputs a low level, and the second-level hardware protection unit is turned off.

[0066] The secondary hardware protection unit is in an undervoltage alarm state. Since the system fault monitoring signal is also in an undervoltage alarm state, the second logic OR gate OR2 outputs a low level, the primary hardware protection unit is turned off, and all levels of hardware protection units are turned off.

[0067]

[0068] Table 2

[0069] Similarly, the composition structure of each hardware protection unit in the logic hardware power-on and power-off monitoring and protection circuit can be designed when M equals other values. The corresponding working principle is also similar to the above process, and will not be listed and explained one by one here.

[0070] Furthermore, each power undervoltage alarm monitoring signal input terminal of each hardware protection unit is connected to a comparator, and the output terminal of each hardware protection unit is sequentially connected to an operational amplifier and an NMOS transistor. The input signal terminal of each comparator is connected to the original acquired power undervoltage alarm monitoring signal of its corresponding channel, the reference signal input terminal of each comparator is connected to the corresponding undervoltage protection point voltage, and the output terminal of each comparator outputs the corresponding power undervoltage alarm monitoring signal.

[0071] The undervoltage protection point voltage at each level needs to be set according to the actual operating conditions. For example, if the operating voltage requirement of a certain hardware protection unit is 4V, but the actual power supply requires 5V, then the undervoltage protection point can be set to 4.5V to achieve temporary system stability during the protection logic operation. According to actual testing, the logic operation time is around 50µs, which is much shorter than the discharge instability time of the power supply capacitors at each level. Testing has shown that it can achieve effective logic protection. Therefore, the undervoltage protection point voltage can usually be designed to be 90% of the normal operating voltage of the corresponding power supply undervoltage alarm monitoring signal.

[0072] The operational amplifier and NMOS transistor connected after the output of each hardware protection unit are as follows: the positive input of the operational amplifier is connected to the output signal of the hardware protection unit of that stage, the inverting input of the operational amplifier is grounded, the output of the operational amplifier is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the power supply, and the source of the NMOS transistor outputs a control signal to control the power supply of the corresponding stage to be turned on or off.

[0073] The logic hardware power-on and power-off monitoring and protection circuit also includes multiple system fault monitoring signal acquisition units. These units are interconnected via multiple AND gates to output a total system fault monitoring signal. Furthermore, each system fault monitoring signal acquisition unit includes at least one of the following: watchdog monitoring signal, system lock monitoring signal, system alarm monitoring signal, and machine on / off monitoring signal. The monitoring signals within each unit are interconnected via AND logic. Figure 4 The diagram illustrates a circuit structure of a single system fault monitoring signal acquisition unit according to Embodiment 1 of the present invention. The watchdog monitoring signal, system lock monitoring signal, system alarm monitoring signal, and machine switch monitoring signal are respectively connected by AND logic gates A5, A6, and A7.

[0074] It should be noted that the components used in the power-on and power-off monitoring and protection circuits of the logic hardware in this embodiment of the invention can all be selected from industrial-grade materials, capable of withstanding all certification tests such as high and low temperatures, thermal shock, vibration shock, and anti-static properties. The power-on and power-off monitoring and protection circuits of this embodiment of the invention can achieve the above functions with minimal cost increase. They can be promoted as the preferred solution for precision instruments and meters with power-off and power-on timing requirements. After high integration into the system, the power-off logic protection circuit can also serve as the direct execution unit for fault actions, ensuring that fault protection actions are still performed within the scope of hardware logic protection.

[0075] The logic hardware power-on and power-off monitoring and protection circuit provided in this embodiment of the invention uses a fully hardware logic circuit and a clever and rigorous logic link to achieve logic locking in the event of power failure, with virtually no additional cost, while achieving highly reliable power-on and power-off logic protection functions. Furthermore, by reasonably configuring multi-level hardware protection units of the logic circuit, power-off protection logic can be implemented while also taking into account power-on protection logic functions. When a system fault occurs, it can be quickly identified and an emergency shutdown can be achieved. This solves the problems of existing power-off methods being bulky, redundant, unreliable, and difficult to expand, and can be used in the circuit modules inside lasers.

[0076] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0077] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A logic hardware power-on and power-off monitoring and protection circuit, characterized in that, It includes M-level hardware protection units. When M is greater than 2, each level of hardware protection unit conforms to the preset design rules. The preset design rules are as follows: When the number of design levels of the hardware protection unit to be designed is ≥2 and <M, an AND logic relationship is formed between the power undervoltage alarm monitoring signals of all hardware protection units before the hardware protection unit to be designed and the total system fault monitoring signal, so as to output the intermediate output signal of the hardware protection unit to be designed. An OR logic relationship is formed between the intermediate output signal of the hardware protection unit to be designed and the power undervoltage alarm monitoring signal of the next level hardware protection unit to be designed, so as to output the output signal of the hardware protection unit to be designed. When the number of design levels of the hardware protection unit to be designed is 1, an OR logic relationship is formed between the power undervoltage alarm monitoring signal of the secondary hardware protection unit and the total system fault monitoring signal, so as to output the output signal of the primary hardware protection unit. When the number of design levels of the hardware protection unit to be designed is M, an AND logic relationship is formed between the power undervoltage alarm monitoring signal of the M-1 level hardware protection unit and the power undervoltage alarm monitoring signal of the M-2 level hardware protection unit to output the intermediate output signal of the M level hardware protection unit. An AND logic relationship is also formed between the intermediate output signal of the M level hardware protection unit and the system fault total monitoring signal to output the output signal of the M level hardware protection unit.

2. The protection circuit according to claim 1, characterized in that, The AND logic relationship in the preset design rules is implemented by connecting a single multi-input pin AND gate, and the OR logic relationship is implemented by an OR gate.

3. The protection circuit according to claim 1, characterized in that, The AND logic relationship in the preset design rules is implemented by sequentially connecting multiple AND gates, and the OR logic relationship is implemented by an OR gate.

4. The protection circuit according to claim 1, characterized in that, When M equals 2, the logic hardware power-on and power-off monitoring and protection circuit includes a primary hardware protection unit and a secondary hardware protection unit. The first-level hardware protection unit includes a first logic OR gate. The power undervoltage alarm monitoring signal of the second-level hardware protection unit and the system fault total monitoring signal are connected by the first logic OR gate to form an OR logic relationship, so as to output the output signal of the first-level hardware protection unit. The secondary hardware protection unit includes a first AND gate. The power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault total monitoring signal are connected by the first AND gate to form an AND logic relationship, so as to output the output signal of the secondary hardware protection unit.

5. The protection circuit according to claim 1, characterized in that, When M is 3, the logic hardware power-on and power-off monitoring and protection circuit includes a first-level hardware protection unit, a second-level hardware protection unit and a third-level hardware protection unit. The primary hardware protection unit includes a second logic OR gate. The power undervoltage alarm monitoring signal of the secondary hardware protection unit and the system fault total monitoring signal are connected by the second logic OR gate to form an OR logic relationship, so as to output the output signal of the primary hardware protection unit. The secondary hardware protection unit includes a second AND gate and a third OR gate. The power undervoltage alarm monitoring signal of the primary hardware protection unit and the system fault total monitoring signal are connected by an AND logic relationship through the second AND gate to output the intermediate output signal of the secondary hardware protection unit. The intermediate output signal of the secondary hardware protection unit and the power undervoltage alarm monitoring signal of the tertiary hardware protection unit are connected by an OR logic relationship through the third OR gate to output the output signal of the secondary hardware protection unit. The three-level hardware protection unit includes a third AND gate and a fourth AND gate. The power undervoltage alarm monitoring signal of the first-level hardware protection unit and the power undervoltage alarm monitoring signal of the second-level hardware protection unit are ANDed through the third AND gate to output the intermediate output signal of the three-level hardware protection unit. The intermediate output signal of the three-level hardware protection unit is ANDed with the system fault total monitoring signal through the fourth AND gate to output the output signal of the three-level hardware protection unit.

6. The protection circuit according to claim 1, characterized in that, It also includes multiple system fault monitoring signal acquisition units, and all of the system fault monitoring signal acquisition units form an AND logic relationship to output the total system fault monitoring signal.

7. The protection circuit according to claim 6, characterized in that, Each of the system fault monitoring signal acquisition units includes at least one of a watchdog monitoring signal, a system lock monitoring signal, a system alarm monitoring signal, and a machine switch monitoring signal. The monitoring signals in the system fault monitoring signal acquisition unit are connected by an AND logic relationship.

8. The protection circuit according to claim 1, characterized in that, Each power supply undervoltage alarm monitoring signal input terminal of each hardware protection unit is connected to a comparator; The input signal terminal of the comparator is connected to the original acquired power undervoltage alarm monitoring signal of the corresponding power supply undervoltage alarm monitoring signal. The reference signal input terminal of the comparator is connected to the undervoltage protection point voltage. The output terminal of the comparator outputs the corresponding power undervoltage alarm monitoring signal.

9. The protection circuit according to claim 8, characterized in that, The voltage at the undervoltage protection point is 90% of the normal operating voltage of the corresponding power supply undervoltage alarm monitoring signal.

10. The protection circuit according to claim 8, characterized in that, Each hardware protection unit's output is also connected to an operational amplifier and an NMOS transistor. The positive input of the operational amplifier is connected to the output signal of that hardware protection unit, the negative input of the operational amplifier is grounded, the output of the operational amplifier is connected to the gate of the NMOS transistor, the drain of the NMOS transistor is connected to the power supply, and the source of the NMOS transistor outputs a control signal to control the power supply of the corresponding stage to be turned on or off.

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