A communication model for optimizing phase jitter in the main circuit of offshore wind turbine converters

Abstract

The application provides a communication model for optimizing phase jitter of a main loop of a marine wind power converter, comprising a main node and a plurality of auxiliary nodes; a sub-module is regarded as an auxiliary node; the main node is connected with three phases of the converter; the main node and the auxiliary nodes both comprise a transmitting end clock domain and a receiving end clock domain; the transmitting end clock domain of the main node transmits a first control signal to the receiving end clock domain of the auxiliary node; the receiving end clock domain of the main node receives a second control signal transmitted by the transmitting end clock domain of the auxiliary node; the second control signal is the first control signal after synchronization processing; the auxiliary node comprises an integral phase discriminator, an AND gate, a digital frequency divider and a phase jitter optimization unit. Compared with the prior art, the communication model is divided into the main node and the plurality of auxiliary nodes, and the clock domains of the main node and the auxiliary nodes are divided respectively, so that the problem of low running efficiency of the sub-modules caused by synchronization based on only the clock domains of the sub-modules is avoided, and the running performance of the whole converter is improved.

Description

Technical Field

[0001] The present invention relates to the field of power transformation technology, and in particular to a communication model for optimizing phase jitter of a main circuit of an offshore wind power converter. Background Art

[0002] To meet the massive use of new energy and the power supply needs of users for different types of loads, DC power grids are widely used in today's power systems. They cooperate with existing AC power grids to form AC / DC hybrid distribution networks. At the same time, high-power electronics need to be introduced to convert electrical energy.

[0003] Modular multilevel converters (MMCs) are widely used in AC / DC hybrid power distribution networks, particularly in offshore wind power applications, due to their voltage-adjustable characteristics, highly modular structure, and high portability. However, in actual use, MMCs require a large number of submodules to operate in coordination, and each submodule requires a control link to obtain the trigger pulse signal for its corresponding IGBT switch. Therefore, control signals may not arrive simultaneously, resulting in the MMC being unable to operate stably within the desired state, which in turn affects the MMC's operational performance. Prior art addresses this issue by primarily using a WRN-based MMC synchronous communication model to reduce phase errors between submodules. However, existing communication models and synchronization methods are based solely on the clock domain of the submodule end. This approach results in a complex submodule communication structure that affects the controlled link, resulting in reduced submodule operational efficiency and an inability to reduce volume, thus affecting the overall operational performance and cost of the converter. Summary of the Invention

[0004] The present invention provides a communication model for optimizing the phase jitter of the main circuit of an offshore wind power converter, so as to solve the technical problem of low sub-module operating efficiency caused by synchronization based only on the sub-module end clock domain in the existing technology, thereby improving the overall operating performance of the converter.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a communication model for optimizing phase jitter of the main circuit of an offshore wind power converter, comprising a main node and several auxiliary nodes; wherein the submodules of the communication model are regarded as the auxiliary nodes;

[0006] The master node is connected to three phases of the modular multilevel converter; the master node and each of the auxiliary nodes include a transmitting end clock domain and a receiving end clock domain;

[0007] The transmitting end clock domain of the master node is used to transmit a first control signal to the receiving end clock domain of each of the auxiliary nodes respectively; the receiving end clock domain of the master node is used to receive a second control signal sent by the transmitting end clock domain of each of the auxiliary nodes; wherein the second control signal is the first control signal that has undergone synchronization processing;

[0008] Each auxiliary node includes an integral phase detector, an AND gate, a digital frequency divider and a phase jitter optimization unit; the input end of the integral phase detector is connected to the receiving end clock domain of the auxiliary node, and the output end of the integral phase detector is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the digital frequency divider; the output end of the digital frequency divider is connected to the input end of the phase jitter optimization unit; the output end of the phase jitter optimization unit is connected to the transmitting end clock domain of the auxiliary node and the input end of the AND gate.

[0009] As a preferred solution, the synchronization process includes:

[0010] Performing zero extraction on the first control signal and inputting the signal into an integrating phase detector;

[0011] Comparing the phase of the first control signal with the phase of the frequency-divided output signal of the modular multilevel converter through the integral phase detector, and issuing a pulse according to the comparison result;

[0012] The pulse is phase synchronized by the digital frequency divider, the phase synchronization result is input into the integral phase detector and the phase jitter optimization unit, and the second control signal is obtained by the phase jitter optimization unit.

[0013] As a preferred solution, the transmitting end clock domain and the receiving end clock domain of the master node, as well as the transmitting end clock domain and the receiving end clock domain of the auxiliary node are divided according to the functions of the first control signal; the functions of the first control signal include receiving function and transmitting function.

[0014] As a preferred solution, the pulse is sent according to the comparison result, specifically:

[0015] When the phase of the output signal is ahead of the phase of the first control signal, a pulse reduction signal is issued; when the phase of the output signal is behind the phase of the first control signal, a pulse increase signal is issued.

[0016] As a preferred solution, the phase jitter optimization unit is used to periodically detect the phase synchronization result. When it is detected that there is a phase error in the phase synchronization result, the phase synchronization result is phase adjusted; when it is detected that there is no phase error in the phase synchronization result, the phase synchronization result is phase locked.

[0017] As a preferred solution, the auxiliary node further comprises a digital oscillator; an output end of the digital oscillator is connected with the digital frequency divider;

[0018] The digital frequency divider is used for phase synchronizing the pulse, specifically:

[0019] The digital frequency divider is used for phase synchronizing the pulse based on a reference clock; the reference clock is generated by the digital oscillator.

[0020] As a preferred solution, the auxiliary node further comprises a loop filter;

[0021] An output end of the integral phase detector is connected with an input end of the AND gate, specifically:

[0022] The output end of the integral phase detector is connected with the input end of the AND gate through the loop filter;

[0023] The loop filter is used for filtering the phase synchronization result before the phase synchronization result is input to the integral phase detector and the phase jitter optimization unit.

[0024] As a preferred solution, the communication model comprises an alternating current port and a direct current port; the alternating current port and the direct current port are both connected with an alternating current-direct current power distribution network.

[0025] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0026] An embodiment of the present invention provides a communication model for optimizing the phase jitter of the main circuit of an offshore wind power converter, comprising a main node and several auxiliary nodes; wherein the submodules of the communication model are regarded as the auxiliary nodes; the main node is connected to the three phases of a modular multilevel converter; the main node and each of the auxiliary nodes include a transmitting end clock domain and a receiving end clock domain; the transmitting end clock domain of the main node is used to transmit a first control signal to the receiving end clock domain of each of the auxiliary nodes respectively; the receiving end clock domain of the main node is used to receive a second control signal sent by the transmitting end clock domain of each of the auxiliary nodes; wherein In the embodiment of the present invention, the second control signal is the first control signal that has undergone synchronization processing; each auxiliary node includes an integral phase detector, an AND gate, a digital frequency divider, and a phase jitter optimization unit; the input end of the integral phase detector is connected to the receiving end clock domain of the auxiliary node, and the output end of the integral phase detector is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the digital frequency divider; the output end of the digital frequency divider is connected to the input end of the phase jitter optimization unit; the output end of the phase jitter optimization unit is connected to the transmitting end clock domain of the auxiliary node and the input end of the AND gate. Compared with the prior art, the embodiment of the present invention divides the communication model into a main node and several auxiliary nodes, and divides the clock domain of the main node and each auxiliary node separately, avoiding the problem of low submodule (auxiliary node) operation efficiency caused by synchronization based only on the submodule end (auxiliary node) clock domain, while reducing the size and cost of the submodule and reducing the occupied space; in addition, the synchronization links and processes of the signal can be designed in different clock domains to improve the overall operation performance of the converter.

[0027] Furthermore, the present invention also provides a synchronization processing method, which uses an integral phase detector to identify and compare the phase of the first control signal and the phase of the output signal after frequency division of the modular multilevel converter, sends a pulse based on the comparison result, and then synchronizes the phase of the pulse through a digital divider, which can further reduce the phase error.

[0028] Furthermore, the phase jitter optimization unit is used to periodically detect the phase synchronization result and adjust its phase when an error is detected; when no error is detected, the phase synchronization result is locked so that the output signal and the input signal are error-free. At the same time, the implementation of the present invention can ensure that the control signals of each auxiliary node can arrive at the same time when there are a large number of auxiliary nodes, making the control link and operation state of the modular multilevel converter more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 : A schematic diagram of the principles of an embodiment of a communication model for optimizing the phase jitter of the main circuit of an offshore wind power converter provided by the present invention.

[0030] Figure 2 : Schematic diagram of the phase voltage waveform on the AC side when the single-phase modular multi-level converter provided by the present invention has signal delay.

[0031] Figure 3 : Schematic diagram of the phase voltage waveform on the AC side of the single-phase modular multi-level converter provided by the present invention after correction.

[0032] Figure 4 : Schematic diagram of the current waveform of the lower bridge arm when the single-phase modular multi-level converter provided by the present invention has a signal delay.

[0033] Figure 5 : Schematic diagram of the current waveform of the lower bridge arm after correction of the single-phase modular multi-level converter provided by the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] Embodiment one:

[0036] Please refer to Figure 1 , Figure 1 A communication model for optimizing the phase jitter of the main circuit of an offshore wind power converter provided by an embodiment of the present invention includes a main (main) node and several auxiliary nodes ( Figure 1 It is only a schematic diagram. For the sake of simplicity, only the interaction process and principle between the main node and one of the auxiliary nodes are shown); wherein, the submodule of the communication model is regarded as the auxiliary node; the converter in this embodiment is a modular multilevel converter.

[0037] The master node is connected to three phases of the modular multilevel converter; the master node and each of the auxiliary nodes include a transmitting end clock domain and a receiving end clock domain;

[0038] The transmitting clock domain of the master node is configured to transmit a first control signal to the receiving clock domain of each of the auxiliary nodes; the receiving clock domain of the master node is configured to receive a second control signal transmitted by the transmitting clock domain of each of the auxiliary nodes; wherein the second control signal is a synchronized first control signal. It should be noted that each first control signal corresponds to a single auxiliary node and is a signal to be synchronized, and the synchronization is performed via the auxiliary node's clock domain.

[0039] Each auxiliary node includes an integral phase detector, an AND gate, a digital frequency divider and a phase jitter optimization unit; the input end of the integral phase detector is connected to the receiving end clock domain of the auxiliary node, and the output end of the integral phase detector is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the digital frequency divider; the output end of the digital frequency divider is connected to the input end of the phase jitter optimization unit; the output end of the phase jitter optimization unit is connected to the transmitting end clock domain of the auxiliary node and the input end of the AND gate.

[0040] In this embodiment, the communication model for optimizing the phase jitter of the main circuit of the offshore wind power converter provided by the embodiment of the present invention is divided into a main node and several auxiliary nodes. The three phases A, B, and C of the modular multilevel converter use the same communication main node Np. Each submodule of the modular multilevel converter is regarded as an auxiliary node Nsmi, where s refers to the three phases A, B, and C, and i is the number of the auxiliary node. For example, when the number is i, it refers to the i-th auxiliary node, and the total number of auxiliary nodes is N, that is, i = 1, 2, 3...N. Control signal clk p The signal is sent by the master node and synchronized through the synchronization structure of the auxiliary node (in this embodiment, each auxiliary node includes a synchronization structure).

[0041] Furthermore, since each auxiliary node has its corresponding function / role (which may be the same or different), the functions corresponding to the control signals of each auxiliary node may also be different. Taking this situation into consideration, this embodiment divides the functions of the control signal into two categories: receiving functions and transmitting functions. The transmitting end clock domain and the receiving end clock domain of the main node, as well as the transmitting end clock domain and the receiving end clock domain of the auxiliary node are divided according to the function of the first control signal.

[0042] Specifically, the clock domain link of the main node can be divided into the transmitting end clock domain TX and the receiving end clock domain RX of the main node according to the transmitting / receiving function of the signal. Similarly, the clock domain on the auxiliary node side can be divided into the transmitting end clock domain TX and the receiving end clock domain RX of the auxiliary node according to the transmitting / receiving function of the signal.

[0043] In the prior art, each submodule (auxiliary node) needs to obtain the trigger pulse signal of the IGBT switch it is responsible for from its corresponding control link. In order to ensure that the control signals of each submodule (auxiliary node) arrive at the same time, the synchronization process includes:

[0044] Performing zero extraction on the first control signal and inputting the signal into an integrating phase detector;

[0045] Comparing the phase of the first control signal with the phase of the frequency-divided output signal of the modular multilevel converter through the integral phase detector, and issuing a pulse according to the comparison result;

[0046] The pulses are phase-synchronized by the digital frequency divider, and the phase synchronization result is input into the integral phase detector and the phase jitter optimization unit to form a closed loop. The second control signal is then obtained by the phase jitter optimization unit. The synchronization processing method provided in this embodiment compares the phases of the first control signal and the output signal after MMC frequency division by the integral phase detector. When the phase of the output signal is ahead of the phase of the first control signal, a pulse reduction signal is issued; when the phase of the output signal is behind the phase of the first control signal, a pulse increase signal is issued. A phase anti-jitter link (phase jitter optimization unit) is added after synchronization. This phase anti-jitter link can effectively reduce the phase error and phase jitter of the output (second) control signal, further improving the operating performance of the converter.

[0047] In this embodiment, the phase jitter optimization unit is configured to periodically detect the phase synchronization result. When a phase error is detected in the phase synchronization result, the phase synchronization result is phase adjusted; when no phase error is detected in the phase synchronization result, the phase synchronization result is phase locked. The auxiliary node further includes a loop filter; the output of the integral phase detector is connected to the input of the AND gate, specifically: the output of the integral phase detector is connected to the input of the AND gate via the loop filter; the loop filter is configured to filter the phase synchronization result before inputting it into the integral phase detector and the phase jitter optimization unit to further reduce the phase error. The phase error of the control signal is reduced by the integral phase detector of the embodiment of the present application, and then further reduced by loop filtering and digital frequency division. Finally, the phase error is detected by the phase jitter optimization unit, so that the output signal and input signal of the auxiliary node are error-free. Especially when there are a large number of auxiliary nodes, the control signal of each auxiliary node can arrive at the same time, the control link and operating state of the modular multilevel converter are more stable, and while the structure of its communication model is more streamlined, its efficiency and operating performance can also be further improved.

[0048] As a further preferred embodiment, the auxiliary node further includes a digital oscillator DCO; the output end of the digital oscillator DCO is connected to the digital frequency divider; the pulse is phase-synchronized by the digital frequency divider, specifically: the digital frequency divider performs phase synchronization on the pulse based on a reference clock; the reference clock is generated by the digital oscillator. The signal generated by each digital frequency divider (the signal corresponding to the reference clock) is respectively injected into each auxiliary node of the communication model to control the auxiliary node. Furthermore, one or more digital frequency dividers can be set outside the auxiliary node to generate a signal to be injected into each auxiliary node to achieve synchronous injection of the auxiliary node.

[0049] Furthermore, the communication model includes an AC port and a DC port, both of which are connected to an AC / DC power distribution network, thereby enabling non-delayed input of control signals of the modular multilevel converter to further reduce errors.

[0050] In order to verify the effectiveness of the topological structure and the control method thereof according to the embodiment of the present application, the communication model is simulated and verified in a single-phase modular multi-level converter. The simulation parameters can be referred to in Table 1.

[0051] Table 1 Simulation parameters of modular multilevel converter topology

[0052] parameter Numerical parameter Numerical AC port voltage / kV 25 DC port voltage / kV 50 AC port load resistance / Ω 1000 Number of bridge arm submodules 10 Submodule capacitance value / μF 3000 Submodule capacitor voltage / kV 5

[0053] The communication model is simulated and verified based on the parameters in Table 1. The simulation results can be found in Figures 2 to 5 .in Figure 2 is the AC side phase voltage waveform when there is signal delay, Figure 3 To correct the AC side phase voltage waveform after signal delay, the voltage is a multi-level waveform. Figure 4 This is the current waveform of the lower bridge arm with signal delay. Figure 5 The waveform of the lower-arm current after correcting the signal delay is consistent with the theoretical results. Simulation waveforms of the communication model with a phase jitter optimization unit (phase anti-jitter) in a single-phase modular multilevel converter demonstrate that this communication model effectively reduces the phase delay of submodule (auxiliary node) control signals, verifying the effectiveness and feasibility of this embodiment's communication model.

[0054] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0055] An embodiment of the present invention provides a communication model for optimizing the phase jitter of the main circuit of an offshore wind power converter, comprising a main node and several auxiliary nodes; wherein the submodules of the communication model are regarded as the auxiliary nodes; the main node is connected to the three phases of a modular multilevel converter; the main node and each of the auxiliary nodes include a transmitting end clock domain and a receiving end clock domain; the transmitting end clock domain of the main node is used to transmit a first control signal to the receiving end clock domain of each of the auxiliary nodes respectively; the receiving end clock domain of the main node is used to receive a second control signal sent by the transmitting end clock domain of each of the auxiliary nodes; wherein In the embodiment, the second control signal is the first control signal that has been synchronized; each of the auxiliary nodes includes an integral phase detector, an AND gate, a digital frequency divider and a phase jitter optimization unit; the input end of the integral phase detector is connected to the receiving end clock domain of the auxiliary node, and the output end of the integral phase detector is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the digital frequency divider; the output end of the digital frequency divider is connected to the input end of the phase jitter optimization unit; the output end of the phase jitter optimization unit is connected to the transmitting end clock domain of the auxiliary node and the input end of the AND gate. Compared with the prior art, the embodiment of the present invention divides the communication model into a main node and several auxiliary nodes, and divides the clock domain of the main node and each auxiliary node separately, thereby avoiding the problem of low operating efficiency of the sub-module (auxiliary node) caused by synchronization based only on the clock domain of the sub-module end (auxiliary node). At the same time, it can streamline the communication structure of the sub-module (auxiliary node), reduce the size and cost of the sub-module (auxiliary node), and reduce the occupied space; in addition, the synchronization links and processes of the signal can be designed in different clock domains to improve the overall operating performance of the converter.

[0056] Furthermore, the present invention also provides a synchronization processing method, which uses an integral phase detector to identify and compare the phase of the first control signal and the phase of the output signal after frequency division of the modular multilevel converter, sends a pulse based on the comparison result, and then synchronizes the phase of the pulse through a digital divider, which can further reduce the phase error.

[0057] Furthermore, the phase jitter optimization unit is used to periodically detect the phase synchronization result and adjust its phase when an error is detected; when no error is detected, the phase synchronization result is locked so that the output signal and the input signal are error-free. At the same time, the implementation of the present invention can ensure that the control signals of each auxiliary node can arrive at the same time when there are a large number of auxiliary nodes, making the control link and operation state of the modular multilevel converter more stable.

[0058] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A communication model for optimizing phase jitter in the main circuit of an offshore wind turbine converter, characterized in that: It includes a main node and several auxiliary nodes; wherein the submodules of the communication model are regarded as the auxiliary nodes; The master node is connected to three phases of the modular multilevel converter; the master node and each of the auxiliary nodes include a transmitting end clock domain and a receiving end clock domain; The transmitting end clock domain of the master node is used to transmit a first control signal to the receiving end clock domain of each of the auxiliary nodes respectively; the receiving end clock domain of the master node is used to receive a second control signal sent by the transmitting end clock domain of each of the auxiliary nodes; wherein the second control signal is the first control signal that has undergone synchronization processing; Each auxiliary node includes an integral phase detector, an AND gate, a digital frequency divider, and a phase jitter optimization unit; the input end of the integral phase detector is connected to the receiving end clock domain of the auxiliary node, the output end of the integral phase detector is connected to the input end of the AND gate; the output end of the AND gate is connected to the input end of the digital frequency divider; the output end of the digital frequency divider is connected to the input end of the phase jitter optimization unit; the output end of the phase jitter optimization unit is connected to the transmitting end clock domain of the auxiliary node and the input end of the AND gate; The synchronization process includes: Performing zero extraction on the first control signal and inputting the signal into an integrating phase detector; Comparing the phase of the first control signal with the phase of the frequency-divided output signal of the modular multilevel converter through the integral phase detector, and issuing a pulse according to the comparison result; performing phase synchronization on the pulses through the digital frequency divider, inputting the phase synchronization result into the integral phase detector and the phase jitter optimization unit, and obtaining the second control signal through the phase jitter optimization unit; The transmitting end clock domain and the receiving end clock domain of the master node, as well as the transmitting end clock domain and the receiving end clock domain of the auxiliary node are divided according to the functions of the first control signal; the functions of the first control signal include receiving function and transmitting function.

2. A communication model for optimizing phase jitter in the main circuit of an offshore wind power converter according to claim 1, characterized in that: The pulse is sent according to the comparison result, specifically: When the phase of the output signal is ahead of the phase of the first control signal, a pulse reduction signal is issued; when the phase of the output signal is behind the phase of the first control signal, a pulse increase signal is issued.

3. The communication model for optimizing phase jitter of the main circuit of an offshore wind power converter according to claim 2, characterized in that: The phase jitter optimization unit is used to periodically detect the phase synchronization result, and when a phase error is detected in the phase synchronization result, perform phase adjustment on the phase synchronization result; When it is detected that there is no phase error in the phase synchronization result, phase locking is performed on the phase synchronization result.

4. The communication model for optimizing phase jitter of the main circuit of an offshore wind power converter according to claim 3, characterized in that: The auxiliary node further comprises a digital oscillator; the output end of the digital oscillator is connected to the digital frequency divider; The pulses are phase synchronized by the digital frequency divider, specifically: The digital frequency divider performs phase synchronization on the pulses based on a reference clock; the reference clock is generated by the digital oscillator.

5. The communication model for optimizing phase jitter of the main circuit of an offshore wind power converter according to claim 4, characterized in that: The auxiliary node further includes a loop filter; The output end of the integral phase detector is connected to the input end of the AND gate, specifically: The output end of the integral phase detector is connected to the input end of the AND gate through the loop filter; The loop filter is used to filter the phase synchronization result before inputting the phase synchronization result into the integral phase detector and the phase jitter optimization unit.

6. A communication model for optimizing phase jitter in the main circuit of an offshore wind power converter according to any one of claims 1 to 5, characterized in that: The communication model includes an AC port and a DC port, and both the AC port and the DC port are connected to an AC / DC power distribution network.

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