A parity-time symmetry coreless constant-voltage system and a control method thereof

Abstract

The application discloses a parity-time symmetry ironless constant-voltage system and a control method thereof, which comprises a parity-time symmetry ironless transformer, a non-controlled rectification module, an output filter capacitor, a load, a zero-crossing comparison circuit, a driving circuit, an embedded controller, a current sampling circuit and a voltage sampling circuit; a sampling output voltage is subtracted from an instruction voltage to obtain an error value, and an operation in a PI compensator is completed; an output of the PI compensator is used as a phase-shifting angle; a transformer primary side current is sampled, and a current frequency is obtained through a zero-crossing comparison circuit and a frequency detection module; a PWM generator outputs a PWM signal according to the phase-shifting angle and the frequency to control an output of a nonlinear saturated controlled voltage source, so as to stabilize the output voltage. The application can realize efficient output of the ironless transformer in the constant-voltage system, and solves the problem of low working efficiency of the traditional ironless transformer.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and in particular to a parity-time symmetric coreless constant voltage system and its control method. Background Technology

[0002] The iron core is the basic component of a transformer. It increases the magnetic coupling between the primary and secondary windings, reduces the excitation current, and thus achieves higher efficiency and power factor. With the in-depth research of power electronics technology, the application of coreless transformers has become a highly attractive goal, offering the following advantages:

[0003] 1. There is no iron loss caused by hysteresis and eddy currents;

[0004] 2. It avoids the saturation phenomenon of the magnetic core and the permeability will not be affected by temperature;

[0005] 3. There will be no magnetic flux imbalance and no core vibration noise;

[0006] 4. There is no need to consider the insulation issues of the iron core and windings;

[0007] 5. Lightweight, low cost, and further improved power density;

[0008] Despite the advantages mentioned above, the disadvantages of low coupling and weak inductance make coreless transformers impractical. This is because transformers require a large excitation current to establish a magnetic field, and a large excitation current will increase the primary current, thereby increasing the on-state losses of the primary winding.

[0009] In recent years, parity-time symmetry theory has been widely applied in the research of wireless power transfer. Wireless power transfer based on parity-time symmetry theory can achieve strong anti-offset characteristics and constant output voltage. This theory also greatly improves the efficient and practical operation of coreless transformers in charging systems. However, parity-time symmetric transformers can exhibit a broken state when the load resistance increases, i.e., when the output power decreases. At this time, the input-output voltage ratio is greater than 1, which does not meet the characteristics of a transformer. Therefore, it is necessary to propose a method that enables parity-time symmetric transformers to achieve a constant voltage ratio output across the entire load range. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings and deficiencies of the prior art and to propose a parity-time symmetric coreless constant voltage system and its control method, which can realize the high-efficiency output of the coreless transformer in the constant voltage system and solve the problem of low working efficiency of traditional coreless transformers.

[0011] To achieve the above objectives, the technical solution provided by the present invention is as follows: a parity-time symmetric coreless constant voltage system, comprising a parity-time symmetric coreless transformer, an uncontrolled rectifier module, an output filter capacitor, a load, a zero-crossing comparator circuit, a drive circuit, an embedded controller, a current sampling circuit, and a voltage sampling circuit;

[0012] The parity-time symmetric coreless transformer includes a primary circuit and a secondary circuit. The primary circuit includes a nonlinear saturated controlled voltage source, a primary leakage inductance, a primary series compensation capacitor, a primary winding stray resistance, a magnetizing inductor, and a primary winding. The secondary circuit includes a secondary winding, a secondary leakage inductance, a secondary series compensation capacitor, and a secondary winding stray resistance. The nonlinear saturated controlled voltage source is controlled by a signal from a drive circuit. The positive output of the nonlinear saturated controlled voltage source is connected to one end of the primary series compensation capacitor. The other end of the primary series compensation capacitor is connected to one end of the primary leakage inductance. The other end of the primary leakage inductance is connected to both the magnetizing inductor and one end of the primary winding. The other end of the magnetizing inductor is connected to the other end of the primary winding and one end of the primary winding stray resistance, respectively. The other end of the primary winding stray resistance is connected to the negative output terminal of the nonlinear saturated controlled voltage source. One end of the secondary winding is connected to one end of the secondary leakage inductance. The other end of the secondary leakage inductance is connected to one end of the secondary series compensation capacitor. The other end of the secondary series compensation capacitor is connected to one input of the uncontrolled rectifier module. The other input of the uncontrolled rectifier module is connected to one end of the secondary winding stray resistance, and the other end of the secondary winding stray resistance is connected to the other end of the secondary winding. The output of the uncontrolled rectifier module is connected to the output filter capacitor and the load, respectively.

[0013] The voltage sampling circuit samples the voltage signal u across the load. o The voltage signal u o Input to the embedded controller;

[0014] The current sampling circuit samples the primary current i of the parity-time symmetric coreless transformer. p , will current i p The signal is input to the zero-crossing comparator circuit, and the signal is obtained by the zero-crossing comparator circuit with i. p A square wave signal with the same frequency and phase is input to the embedded controller;

[0015] The input to the drive circuit is the PWM signal output by the embedded controller, and the output drive signal of the drive circuit controls the nonlinear saturated controlled voltage source.

[0016] Furthermore, the embedded controller includes a frequency detection module, a PWM generator, a PI compensator, and an error calculation module. The error calculation module calculates the input voltage signal u. oWith command voltage u ref Subtraction yields the error value u err The error value u err The input is fed into a PI compensator, which performs compensation calculations and outputs a phase shift angle θ. The frequency detection module detects the frequency of the square wave signal input to the zero-crossing comparator circuit to obtain the primary current i. p frequency f s The phase shift angle θ and frequency f s The signal is input to a PWM generator, which outputs a PWM signal.

[0017] Furthermore, the resonant frequency of the primary side loop is The resonant frequency of the secondary circuit is Define ω0 as the system frequency, then the resonant frequencies ω of the primary and secondary circuits are... p =ω s =ω0; where, C p C is the capacitance value of the primary-side series compensation capacitor. s L is the capacitance value of the secondary-side series compensation capacitor. kp L is the inductance value of the primary leakage inductance. ks L is the inductance value of the secondary leakage inductance. m Let n be the inductance of the magnetizing inductor, and the turns ratio of the primary and secondary windings be n. p :n s To achieve a parity-time symmetric coreless constant-voltage system, the following must be satisfied:

[0018]

[0019] In the formula, R s R is the resistance value of the stray resistance of the secondary winding. p Z is the resistance value of the stray resistance of the primary winding. N The equivalent negative impedance of a nonlinear saturated controlled voltage source is expressed as: in The output voltage u of the nonlinear saturated controlled voltage source L phasors, For the primary current i of a parity-time symmetric coreless transformer p The phasor; when θ = 0, the negative impedance Z N Equivalent to a negative resistance R N ;R L The equivalent load resistance is expressed as R o is the resistance value of the load; k is the coupling coefficient between the primary and secondary windings.

[0020] This invention also provides a control method for the above-mentioned parity-time symmetric coreless constant voltage system, as detailed below:

[0021] When the coreless constant voltage system operates under parity-time symmetry, the phase shift angle θ equals 0, and the embedded controller determines the phase shift angle based on the input current i. p frequency f s The output PWM signal of the same frequency is used to control the output of the nonlinear saturated controlled voltage source with the same current i through the drive circuit. p Voltages u with the same phase and frequency L To achieve a constant voltage ratio; when the coreless constant voltage system does not satisfy parity-time symmetry in its operating state, the phase shift angle θ>0, and the embedded controller adjusts the input current i p frequency f s The phase shift angle θ outputs a PWM signal, which, through the drive circuit, controls the output of a nonlinear saturated controlled voltage source and the current i. p Voltages u with the same frequency and a phase difference of θ / 2 L To stabilize the output voltage.

[0022] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0023] 1. The application of coreless transformers in constant voltage systems has been realized. Compared with the application of traditional iron core transformers, the parity-time symmetric coreless transformer of this invention does not require an iron core, resulting in lower cost. It also eliminates iron loss, avoids core saturation, and its permeability is unaffected by temperature. Furthermore, it is lightweight, low-cost, and its weight power density is further improved.

[0024] 2. Compared with traditional coreless transformers, coreless transformers based on the parity symmetry principle have high-efficiency output characteristics under a wide power range. Attached Figure Description

[0025] Figure 1 This is a block diagram of a parity-time symmetric coreless constant-pressure system.

[0026] Figure 2 This is a circuit diagram of a nonlinear saturated controlled voltage source.

[0027] Figure 3 This is a schematic diagram of the output voltage and current of a nonlinear saturated controlled voltage source.

[0028] Figure 4 This invention is fully loaded with (100% P) o Waveforms of primary winding current and secondary winding current under operating conditions.

[0029] Figure 5 This invention is extremely lightweight (10% P) o Waveforms of primary winding current and secondary winding current under operating conditions.

[0030] Figure 6This is the dynamic waveform of the output voltage when switching from extremely light load to full load in this invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0032] like Figure 1 As shown, this embodiment discloses a parity-time symmetric coreless constant voltage system, including a parity-time symmetric coreless transformer 101, an uncontrolled rectifier module, and an output filter capacitor C. o '、Load R o ', zero-crossing comparator circuit, drive circuit, embedded controller 102, current sampling circuit and voltage sampling circuit;

[0033] The parity-time symmetric coreless transformer 101 includes a primary circuit and a secondary circuit, wherein the primary circuit contains a nonlinear saturated controlled voltage source V(f s ,θ), primary leakage inductance L kp ', Primary-side series compensation capacitor C p primary winding stray resistance R p Magnetizing inductance L m 'and primary winding; the secondary circuit includes secondary winding, secondary leakage inductance L ks Secondary-side series compensation capacitor C s 'and secondary winding stray resistance R s The nonlinear saturated controlled voltage source V(f) s The nonlinear saturated controlled voltage source V(f) is controlled by a signal from the driving circuit. s The positive terminal of the output of θ is connected in series with a compensation capacitor C on the primary side. p One end of the primary side is connected to the secondary side, and the primary side is connected in series with the compensation capacitor C. p The other end of ' is related to the original edge leakage L' kp One end of ' is connected, the original leakage inductance L kp The other end is connected to the magnetizing inductor L. m The excitation inductor L is connected to one end of the primary winding. m The other end of ' is connected to the other end of the primary winding and the stray resistance R of the primary winding, respectively. p One end of the primary winding is connected to the secondary winding stray resistance R. p The other end of ' is connected to the nonlinear saturated controlled voltage source V(f) s The output negative terminal of the secondary winding is connected to the secondary leakage inductance L. ks One end of ' is connected, the secondary leakage inductance L ks The other end of the capacitor is connected in series with the secondary side, and a compensation capacitor C is connected in series. sOne end of the capacitor is connected to the secondary side, and a series compensation capacitor C is connected to it. s The other end of the ' is connected to one input of the uncontrolled rectifier module, and the other input of the uncontrolled rectifier module is connected to the stray resistance R of the secondary winding. s One end is connected, and the stray resistance R of the secondary winding is... s The other end is connected to the other end of the secondary winding; the output of the uncontrolled rectifier module is connected to the output filter capacitor C. o 'and load R o 'Connected;

[0034] The voltage sampling circuit samples the load R. o 'Voltage signal u at both ends o The voltage signal u o Input to embedded controller 102;

[0035] The current sampling circuit samples the primary current i of the parity-time symmetric coreless transformer 101. p , will current i p The signal is input to the zero-crossing comparator circuit, and the signal is obtained by the zero-crossing comparator circuit with i. p A square wave signal with the same frequency and phase is input to the embedded controller 102.

[0036] The input to the drive circuit is the PWM signal output by the embedded controller 102, and the drive circuit outputs a drive signal to control the nonlinear saturated controlled voltage source V(f s ,θ).

[0037] The embedded controller 102 includes a frequency detection module 102-1, a PWM generator 102-2, a PI compensator 102-3, and an error calculation module 102-4. The error calculation module 102-4 processes the input voltage signal u. o With command voltage u ref Subtraction yields the error value u err The error value u err The input is fed into the PI compensator 102-3, which performs compensation calculations and outputs a phase shift angle θ. The frequency detection module 102-1 detects the frequency of the square wave signal input to the zero-crossing comparator circuit to obtain the primary current i. p frequency f s The phase shift angle θ and frequency f s The signal is input to the PWM generator 102-2, which outputs a PWM signal.

[0038] The resonant frequency of the primary loop is The resonant frequency of the secondary circuit is Define ω0 as the system frequency, then the resonant frequencies ω of the primary and secondary circuits are... p =ω s =ω0; where, C p The primary-side series compensation capacitor C p The capacitance value, C s For the secondary side series compensation capacitor C s The capacitance value of ', L kp For the original edge leakage inductance L kp The inductance value of ', L ks For secondary side leakage inductance L ks The inductance value of ', L m For the magnetizing inductor L m The inductance is ', and the turns ratio of the primary and secondary windings is n. p :n s To achieve a parity-time symmetric coreless constant-voltage system, the following must be satisfied:

[0039]

[0040] In the formula, R s The stray resistance R of the secondary winding s The resistance value of ', R p stray resistance R of the primary winding p The resistance value of Z N A nonlinear saturated controlled voltage source V(f) s The equivalent negative impedance of θ is expressed as in A nonlinear saturated controlled voltage source V(f) s Output voltage u, θ) L phasors, For the primary current i of the parity-time symmetric coreless transformer 101 p The phasor; when θ = 0, the negative impedance Z N Equivalent to a negative resistance R N ;R L The equivalent load resistance is expressed as R o For load R o The resistance value of '; k is the coupling coefficient between the primary and secondary windings.

[0041] When the coreless constant voltage system operates under parity-time symmetry, the phase shift angle θ equals 0, and the embedded controller 102 determines the phase shift angle based on the input current i. p frequency f s Output a PWM signal of the same frequency, which controls the nonlinear saturated controlled voltage source V(f) through the drive circuit. s ,θ) Output and current i p Voltages u with the same phase and frequency LThis is to achieve a constant voltage ratio.

[0042] When the coreless constant voltage system does not satisfy parity-time symmetry in its operating state, and the phase shift angle θ > 0, the embedded controller 102 determines the phase shift angle based on the input current i. p frequency f s The phase shift angle θ outputs a PWM signal, which controls the nonlinear saturated controlled voltage source V(f) through the drive circuit. s ,θ) Output and current i p Voltages u with the same frequency and a phase difference of θ / 2 L To stabilize the output voltage.

[0043] Define the characteristic impedance Z of the primary winding. p The characteristic impedance Z of the secondary winding s Quality factor Q of the primary winding p Quality factor Q of the secondary winding s The following are examples:

[0044]

[0045] Define ω0 as the system frequency, and the natural frequencies of the primary and secondary loops in equation (1) satisfy ω p =ω s =ω0, θ / 2 are the input voltage and current i of the nonlinear saturated controlled voltage source. p Phase; R L The equivalent load resistance can be expressed as: R o The resistance value of the load is n, and the turns ratio of the primary and secondary windings is n. p :n s Z N The equivalent negative impedance of a nonlinear saturated controlled voltage source can be expressed as: in The output voltage u of the nonlinear saturated controlled voltage source L phasors, Let i be the primary current of the transformer. p phasor; C p C is the capacitance value of the primary-side series compensation capacitor. s L is the capacitance value of the secondary-side series compensation capacitor. kp L is the inductance value of the primary leakage inductance. ks R is the inductance value of the secondary leakage inductance. s R is the resistance value of the stray resistance of the secondary winding. p L is the resistance value of the stray resistance of the primary winding. m Let be the inductance of the magnetizing inductor, and k be the coupling coefficient between the primary and secondary windings;

[0046] The circuit expression for the primary and secondary coupled windings satisfies the following equation:

[0047]

[0048] Substituting equation (1) into equation (2) and simplifying, we get:

[0049]

[0050] In the above equation, ω is the angular frequency of the output voltage of the nonlinear saturated controlled voltage source, which can be expressed as ω=2πfs. The system of two homogeneous linear equations with two variables (3) has a non-zero solution, that is, the determinant of the matrix is ​​zero, and we have:

[0051]

[0052] Define Q0 as the system quality factor, which is satisfied when the parameters of the primary and secondary loops meet the parity-time symmetry condition, i.e.:

[0053]

[0054] In the above equation, separating the real and imaginary parts of equation (4), the real frequency solution when the real part equals 0 is as follows:

[0055]

[0056] When the parameters of the primary and secondary circuits satisfy the parity-time symmetry condition, the saturation voltage value U of the nonlinear saturated controlled voltage source is... dc and the system's output voltage U o Satisfy the following formula:

[0057]

[0058] Combining equation (7), it can be seen that the input and output voltages satisfy the turns ratio relationship of a traditional cored transformer, that is, the parity-time symmetrical coreless constant voltage system can achieve the characteristic of a constant voltage ratio; when the load becomes lighter, the system does not satisfy equation (5), and the constant voltage system is based on the input current i p frequency f s The phase shift angle θ is adjusted to stabilize the output voltage of the nonlinear saturated controlled voltage source, at which point the nonlinear saturated controlled voltage source exhibits a negative impedance form.

[0059] The efficiency η of the constant pressure system under the two operating conditions of θ=0 and θ>0 can be calculated as follows:

[0060]

[0061] When the phase shift angle θ>0, let The effective output value U of the nonlinear saturated controlled voltage source L It can be represented as U dcThis is the nonlinear saturation voltage value. Its voltage gain... The relationship between the phase shift angle θ and the angular frequency ω can be expressed as:

[0062]

[0063] In equation (11), U o X is the output voltage; p The primary reactance can be expressed as: Xs is the secondary reactance, which can be expressed as The angular frequency ω and the phase shift angle θ satisfy the following equation, as shown below:

[0064]

[0065] To further illustrate the benefits and feasibility of the present invention, an embodiment is designed for illustration, with the following parameters:

[0066] primary winding leakage inductance L kp =20uH, primary-side series capacitor C p =50nF, winding stray resistance R p =150mΩ; secondary winding leakage inductance L ks =20uH, secondary series capacitor C s =50nF, winding stray resistance R s =150mΩ; the turns ratio of the primary and secondary windings is n p :n s =30:30, primary magnetizing inductance is L m =20uH, primary and secondary winding coupling coefficient is 0.5; output voltage is U o =96V, rated power P o =1800W;

[0067] Negative impedance is used Figure 2 The nonlinear saturated controlled voltage source shown, U dc =110V;

[0068] Optionally, the nonlinear saturated controlled voltage source in this embodiment is as follows: Figure 2 As shown, the structure consists of an inverter circuit composed of a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4, with an input voltage of DC U. dc Specifically, the DC voltage source U dc The positive terminal of the DC voltage source U is connected to the first switch S1 and the second switch S2. dcThe negative terminal is connected to the third switch S3 and the fourth switch S4, the first switch S1 is connected to the third switch S3, and the second switch S2 is connected to the fourth switch S4; the two output terminals of the full-bridge inverter module generate high-frequency square wave AC power; the nonlinear saturated controlled voltage source is not limited to the above structure.

[0069] Figure 3 This is a schematic diagram of the output voltage and current of a nonlinear saturated controlled voltage source, with a phase difference of θ / 2 between the output voltage and current. Let... The effective input value of the nonlinear saturated controlled voltage source can then be expressed as:

[0070] Figure 4 and Figure 5 In this embodiment, the load resistance R is respectively o =5Ω(100%P) o ) and R o =50Ω(10%P) o When R..., the waveforms of the primary winding current and the secondary winding current are shown. o When R = 5Ω, the system operates in a parity-time symmetric state, at which point θ = 0, there is no reactive circulating current, and the stable output voltage is 96V; when R o When the Ω is 50Ω, to ensure output voltage stability, the input current i is used as follows: p frequency f s The output voltage is stabilized at 96V by adjusting the phase shift angle θ. Figure 6 This invention provides a dynamic waveform for switching from extremely light load to full load. Due to the control function, the output voltage remains constant.

[0071] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A parity-time symmetric coreless constant-voltage system, characterized in that: Includes a parity-time symmetric coreless transformer (101), an uncontrolled rectifier module, and an output filter capacitor (C). o '), Load (R) o '), zero-crossing comparator circuit, drive circuit, embedded controller (102), current sampling circuit and voltage sampling circuit; The parity-time symmetric coreless transformer (101) includes a primary circuit and a secondary circuit, wherein the primary circuit contains a nonlinear saturated controlled voltage source (V(f)). s ,θ)), primary leakage inductance (L kp '), Primary-side series compensation capacitor (C) p '), primary winding stray resistance (R) p '), Magnetizing inductance (L m The secondary circuit includes a secondary winding and a secondary leakage inductance (L) and a primary winding; the secondary circuit includes a secondary winding and a secondary leakage inductance (L) and a primary winding. ks '), secondary-side series compensation capacitor (C) s ') and secondary winding stray resistance (R s '); The nonlinear saturated controlled voltage source (V(f) s The nonlinear saturated controlled voltage source (V(f)) is controlled by a signal from the driving circuit. s The positive terminal of the output of θ) is connected in series with a compensation capacitor (C) on the primary side. p One end of the primary side is connected to the series compensation capacitor (C). p The other end of ') is connected to the original edge leakage sensation (L) kp One end of the original edge leakage inductance (L) is connected to the other end of the original edge leakage inductance (L). kp The other end of ') is connected to the magnetizing inductor (L) respectively. m The magnetizing inductor (L) is connected to one end of the primary winding and the primary winding. m The other end of the winding is connected to the other end of the primary winding and the stray resistance (R) of the primary winding, respectively. p One end of the primary winding is connected to the stray resistance (R) of the primary winding. p The other end of ') is connected to a nonlinear saturated controlled voltage source (V(f)). s The output negative terminal of the secondary winding is connected to the secondary leakage inductance (L). ks One end of the secondary leakage inductance (L) is connected to the other end of the secondary leakage inductance (L). ks The other end of the capacitor is connected in series with the secondary side by a compensation capacitor (C). s One end of the secondary side is connected to the other end, and the secondary side is connected in series with a compensation capacitor (C). s The other end of the uncontrolled rectifier module is connected to one input of the uncontrolled rectifier module, and the other input of the uncontrolled rectifier module is connected to the stray resistance (R) of the secondary winding. s One end is connected to the secondary winding stray resistance (R). s The other end is connected to the other end of the secondary winding; the output of the uncontrolled rectifier module is connected to the output filter capacitor (C) respectively. o ') and load (R) o ') connected; The voltage sampling circuit samples the load (R) o The voltage signal u at both ends o The voltage signal u o Input to the embedded controller (102); The current sampling circuit samples the primary current i of the parity-time symmetric coreless transformer (101). p , the primary current i p The signal is input to the zero-crossing comparator circuit, and the signal is obtained by the zero-crossing comparator circuit with i. p A square wave signal with the same frequency and phase is input to the embedded controller (102); The input to the drive circuit is the PWM signal output by the embedded controller (102), and the drive circuit outputs a drive signal to control the nonlinear saturated controlled voltage source (V(f)). s ,θ)).

2. The parity-time symmetric coreless constant voltage system according to claim 1, characterized in that: The embedded controller (102) includes a frequency detection module (102-1), a PWM generator (102-2), a PI compensator (102-3), and an error calculation module (102-4). The error calculation module (102-4) calculates the input voltage signal u. o With command voltage u ref Subtraction yields the error value u err The error value u err The input is fed to the PI compensator (102-3), which completes the compensation calculation and outputs a phase shift angle θ; the frequency detection module (102-1) detects the frequency of the square wave signal input to the zero-crossing comparator circuit to obtain the primary current i. p frequency f s The phase shift angle θ and frequency f s The signal is input to the PWM generator (102-2), which outputs a PWM signal.

3. The parity-time symmetric coreless constant voltage system according to claim 2, characterized in that: The resonant frequency of the primary loop is The resonant frequency of the secondary circuit is Define ω0 as the system frequency, then the resonant frequencies ω of the primary and secondary circuits are... p =ω s =ω0; Among them, C p For the primary side series compensation capacitor (C) p The capacitance value of C') s For secondary-side series compensation capacitor (C) s The capacitance value of L') kp For the original edge leakage inductance (L) kp The inductance value of L') ks For secondary side leakage inductance (L) ks The inductance value of L') m For the magnetizing inductor (L m The inductance is '), and the turns ratio of the primary and secondary windings is n. p :n s To achieve a parity-time symmetric coreless constant-voltage system, the following must be satisfied: In the formula, R s The stray resistance of the secondary winding (R) s The resistance value of ') R p stray resistance of the primary winding (R) p The resistance value of Z') N Nonlinear saturated controlled voltage source (V(f)) s The equivalent negative impedance of θ) is expressed as in Nonlinear saturated controlled voltage source (V(f)) s Output voltage u L phasors, For the primary current i of a parity-time symmetric coreless transformer (101) p The phasor; when θ = 0, the negative impedance Z N Equivalent to a negative resistance R N ;R L The equivalent load resistance is expressed as R o For load (R) o The resistance value of '); k is the coupling coefficient between the primary and secondary windings.

4. The control method for the parity-time symmetric coreless constant-pressure system as described in claim 2 or 3, characterized in that: When the coreless constant voltage system operates under parity-time symmetry, the phase shift angle θ equals 0, and the embedded controller (102) determines the phase shift angle based on the input primary current i. p frequency f s Output a PWM signal of the same frequency, which controls the nonlinear saturated controlled voltage source (V(f)) through the drive circuit. s ,θ)) Output and primary current i p Voltages u with the same phase and frequency L To achieve a constant voltage ratio; when the coreless constant voltage system does not satisfy parity-time symmetry, the phase shift angle θ>0, and the embedded controller (102) adjusts the input primary current i p frequency f s The phase shift angle θ outputs a PWM signal, which controls the nonlinear saturated controlled voltage source (V(f)) through the drive circuit. s ,θ)) Output and primary current i p Voltages u with the same frequency and a phase difference of θ / 2 L To stabilize the output voltage.

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