An active clamp flyback converter

Abstract

This invention discloses an active clamp flyback converter, comprising: a first capacitor; a second capacitor and a first resistor; a first switch, a second switch, and a second resistor; a transformer, including a leakage inductance, a primary winding, a secondary winding, and an auxiliary winding; a first diode and a fourth capacitor; a second diode and a third capacitor; a third resistor and a fourth resistor; and a control circuit, including a drive module and a bus voltage sampling module. The bus voltage sampling module utilizes the characteristic that the voltage value of the auxiliary winding is linearly correlated with the bus voltage when the voltage is negative, and clamps the connection point of the third and fourth resistors, which are connected in series across the auxiliary winding, to -200mV. This converts the auxiliary winding voltage into an IVS current sampled and stored internally in the chip. Combined with the switching timing, the IVS current information is converted into voltage information stored on the capacitor. This invention shifts the sampling of the bus voltage to the lower-voltage auxiliary winding, thereby reducing the resistance value of the voltage divider resistor under the same quiescent current.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and more specifically to an active clamp flyback converter. Background Technology

[0002] With the continuous innovation of electronic products worldwide, especially the AC-DC converters used in USB PD fast charging, high demands are placed on power density and converter efficiency. Currently, most AC-DC converters adopt flyback topology. Compared with traditional flyback converters, active clamp flyback converters improve the utilization of leakage inductance energy and can achieve soft turn-on of power transistors, thus effectively improving efficiency.

[0003] The input to a conventional flyback topology system is AC mains power, which is the bus voltage (V) after full-bridge rectification and filtering by a voltage regulator capacitor. BULK This is the input of the active clamp flyback converter. When the bus voltage is too low, the flyback converter should stop working. The traditional method of bus voltage detection is to use a resistor divider. Because the bus voltage can be as high as 400V, a large resistor value is required to reduce static power consumption, which brings additional external component costs.

[0004] Therefore, it is necessary to provide an improved bus voltage sampling technology to overcome the shortcomings of the existing technology. Summary of the Invention

[0005] The purpose of this invention is to provide a universal bus voltage sampling circuit suitable for active clamp flyback converters. By utilizing the characteristic that the absolute value of the voltage across the auxiliary winding of the transformer is linearly related to the bus voltage within a specific time period, the sampling of the bus voltage is shifted from the traditional high voltage domain of several hundred volts to the low voltage domain of negative tens of volts, thereby reducing the required voltage divider resistor value.

[0006] The technical solution of this invention is as follows:

[0007] An active flyback converter includes a transformer, a first switching transistor, a second switching transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first diode, a second diode, a leakage inductor, and a control circuit.

[0008] The transformer has a primary winding, a secondary winding, and an auxiliary winding. The same-name terminal of the primary winding is connected to the bus voltage through the leakage inductance. One end of the first capacitor is connected to the bus voltage, and the other end of the first capacitor is grounded.

[0009] The drain of the first switching transistor is connected to the bus voltage through a circuit formed by the first resistor and the second capacitor in parallel. The gate and source of the first switching transistor are connected to the control circuit. The source of the first switching transistor is also connected to the drain of the second switching transistor and the opposite terminal of the primary winding.

[0010] The gate and source of the second switch are connected to the control circuit, and the source of the second switch is also grounded through the second resistor.

[0011] The opposite-named terminal of the auxiliary winding is connected to the anode of the second diode, the cathode of the second diode is connected to the control circuit and one end of the third capacitor, and the same-named terminal of the auxiliary winding, one end of the fourth resistor and the other end of the third capacitor are grounded.

[0012] The opposite end of the auxiliary winding is connected to one end of the third resistor, and the other end of the third resistor is connected to the control circuit and the other end of the fourth resistor.

[0013] The opposite-named terminal of the secondary winding is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the fourth capacitor, and the same-named terminal of the secondary winding and the other end of the fourth capacitor are grounded.

[0014] The control circuit includes a drive module and a bus voltage sampling module; wherein the drive module is connected to the gate and source of the first switch and the gate and source of the second switch; the drive module is an essential circuit module in a traditional active clamp flyback converter, and this invention has not improved it, so unnecessary descriptions of this part are omitted here.

[0015] The technical solution of the bus voltage sampling module is as follows: Figure 3 As shown, it includes a first bias current, a second bias current, a first low-voltage NMOS transistor, a second low-voltage NMOS transistor, a third low-voltage NMOS transistor, a first high-voltage NMOS transistor, a first low-voltage PMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first buffer, a first AND gate, a first inverter, a first transmission gate, a second transmission gate, and a first operational amplifier;

[0016] The current formed by the parallel connection of the first bias current and the second bias current is connected to the gate terminal of the first low-voltage NMOS transistor and one end of the eighth resistor; the other end of the eighth resistor is connected to the drain terminal of the first low-voltage NMOS transistor, the drain terminal of the first low-voltage PMOS transistor, and the gate terminal of the second low-voltage NMOS transistor; the source terminal of the first low-voltage NMOS transistor is grounded.

[0017] One end of the fifth resistor is connected to one end of the sixth resistor, the gate of the first high-voltage NMOS transistor, one end of the fifth capacitor, and one end of the sixth capacitor; the other end of the fifth resistor is connected to the source of the first low-voltage PMOS transistor; the gate of the first low-voltage PMOS transistor is connected to the other end of the sixth resistor, the drain of the second low-voltage NMOS transistor, the source of the third low-voltage NMOS transistor, and the input of the first transmission gate;

[0018] The cathode (VDD) of the second diode is connected to the drain of the first high-voltage NMOS transistor; the source of the first high-voltage NMOS transistor is connected to one end of the seventh resistor; the other end of the seventh resistor is connected to the drain of the third low-voltage NMOS transistor; and the gate of the third low-voltage NMOS transistor is connected to the first input bias voltage.

[0019] The source terminal of the second low-voltage NMOS transistor is connected to the other end (VS) of the third resistor after passing through the ninth resistor; the output of the first transmission gate is connected to the other end of the fifth capacitor and the input of the second transmission gate; the non-inverting control terminal of the first transmission gate is connected to the output of the first AND gate, the input of the first inverter, and the inverting control terminal of the second transmission gate; the inverting control terminal of the first transmission gate is connected to the output of the first inverter and the non-inverting control terminal of the second transmission gate.

[0020] The output of the second transmission gate is connected to the other end of the sixth capacitor and the positive input of the first operational amplifier; the negative input of the first operational amplifier is connected to the output of the first operational amplifier; the input of the first buffer is connected to the control signal Vgs_Q2 of the second switch (Vgs_Q2 = VG2 - VS2); the output of the first buffer is connected to the first input of the first AND gate and one end of the tenth resistor; the other end of the tenth resistor is connected to one end of the seventh capacitor and the second input of the first AND gate; the other end of the seventh capacitor is grounded.

[0021] The beneficial effects of the present invention include at least the following:

[0022] The bus voltage sampling module in the active clamp flyback converter of this invention utilizes the existing auxiliary winding of the flyback converter and takes advantage of the linear relationship between the voltage across the auxiliary winding and the bus voltage over a specific time period. This shifts the sampling of the bus voltage from a high-voltage domain of several hundred volts to a lower voltage domain of tens of negative volts where the auxiliary winding is located. The module also has a negative voltage clamping function, which clamps the voltage of the VS pin of the chip associated with the auxiliary winding to -200mV when the voltage across the auxiliary winding is negative, preventing negative voltage from damaging the chip. Attached Figure Description

[0023] Figure 1 This diagram illustrates the circuit structure of a flyback converter provided in an embodiment of the present invention.

[0024] Figure 2 Show Figure 1 The timing waveform diagram of the active clamp flyback converter is shown below;

[0025] Figure 3 Show Figure 1 A schematic diagram of the circuit structure of the bus voltage sampling module in the diagram; Detailed Implementation

[0026] To facilitate understanding of the present invention, a more comprehensive description of the present invention will be given below with reference to the accompanying drawings, which illustrate some embodiments of the present invention. It should be noted that the present invention can be implemented in different forms and is not limited to the specific embodiments described herein. The purpose of providing these embodiments is to better illustrate the present invention and to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0027] Figure 1 This invention illustrates the circuit structure of a flyback converter provided in an embodiment of the present invention. The power supply system in this embodiment includes: an AC power supply 1, a rectifier circuit 2, and a first capacitor C. BULK 3. Flyback converter 3, wherein flyback converter 3 includes, but is not limited to, an active clamp flyback converter.

[0028] Rectifier circuit 2 rectifies AC power supply 1 into a second voltage signal V. BULK It serves as the input to flyback converter 3. Optionally, rectifier circuit 2 can be a half-bridge rectifier or a full-bridge rectifier circuit.

[0029] In this embodiment of the invention, the flyback converter 3 is an active clamp flyback converter, which includes: a second capacitor C2, a third capacitor C3, a fourth capacitor Co, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first switch Q1, a second switch Q2, a first rectifier diode D1, a second rectifier diode D2, a control circuit 31 including a drive module and a bus voltage sampling module 312, and a primary winding Np, a secondary winding Ns, an auxiliary winding Na, and a leakage inductance L. K Transformer 32.

[0030] In this embodiment of the invention, the second voltage signal V BULK The second capacitor C2 and the first resistor R1 are connected in parallel to the drain terminal of the first switching transistor Q1. The gate and source terminals of the first switching transistor are connected to the control circuit 31. The source terminal of the first switching transistor is also connected to the third voltage signal V. SW Second voltage signal V BULK Also through the series leakage inductance L K The primary winding Np is connected to the third voltage signal V. SW The gate and source terminals of the second switching transistor are connected to the control circuit 31, and the source terminal of the second switching transistor is connected to the primary reference ground through the second resistor R2.

[0031] During the same switching cycle of the flyback converter 3, the first switch Q1 and the second switch Q2 are turned on in a time-sharing manner to realize the transfer of the second voltage signal V. BULK Energy is obtained from the primary winding Np and transferred to the secondary side of the flyback converter 3 to output Vo. Optionally, the first switch Q1 and the second switch Q2 can be NMOS transistors or N-type GaN transistors.

[0032] The secondary side of the flyback converter 3 includes a secondary winding Ns, a first rectifier diode D1, and a fourth capacitor Co. The anode of the first rectifier diode D1 is connected to the opposite-named terminal of the secondary winding Ns, and the cathode of the first rectifier diode D1 is connected to the output Vo of the flyback converter 3. The anode of the fourth capacitor Co is connected to the output Vo of the flyback converter 3, and the cathode of the fourth capacitor Co is connected to the secondary reference ground. The same-named terminal of the secondary winding is connected to the secondary reference ground. In one possible embodiment, the output Vo of the flyback converter 3 is connected to a load, and the load receives a second voltage signal V from the flyback converter 5. BULK The power is obtained from the load and transmitted to the output of the flyback converter. In one possible embodiment, the output of the flyback converter 5 is connected to the load through a BUS switch controlled by the PD fast charging chip, thereby controlling the power of the power received by the load. Optionally, the BUS switch can be an NMOS transistor or an N-type GaN transistor.

[0033] The auxiliary winding Na of transformer 32 has its same-name terminal connected to the primary reference ground and its opposite-name terminal connected to the anode of the second diode. The cathode of the second diode is connected to the anode of the third capacitor. The primary side of the lower plate of the third capacitor is connected to the reference ground. After the chip is started, the auxiliary winding Na is responsible for supplying power to the chip's power rail VDD.

[0034] The third resistor R3 and the fourth resistor R4 are connected in series between the opposite terminal of the auxiliary winding Na and the primary reference ground. The connection point of the third resistor R3 and the fourth resistor R4 is connected to the VS pin of the bus voltage sampling module 312.

[0035] The control circuit 31 generates control signals Vgs_Q1 and Vgs_Q2 for the first switch Q1 and the second switch Q2, and uses the drive module 311 to drive Q1 and Q2 to control their switching states, where Vgs_Q1 = VG1 - VS1 and Vgs_Q2 = VG2 - VS2.

[0036] The control circuit 31 also includes a bus voltage sampling module 312, which is connected to the VS pin of the chip. When the auxiliary winding is at a negative voltage, this module clamps the VS pin to -200mV and receives the bus voltage V from the VS pin. BULK Current I that exhibits a linear relationship VS This information is converted into voltage information and stored inside the module for use by the chip.

[0037] refer to Figure 2 , Figure 1 The working principle of the active clamp flyback converter shown is as follows:

[0038] At time t0, the control signal Vgs_Q2 of transistor Q2 goes high, and transistor Q2 is turned on.

[0039] During the time period t0-t1, the control signal Vgs_Q1 for transistor Q1 is low, and the control signal Vgs_Q2 for transistor Q2 is high; transistor Q1 is off, and transistor Q2 is on. During this time period, the active clamp flyback converter draws voltage from the bus voltage V... BULK Energy is acquired and transmitted through leakage sensing L. k Magnetizing inductance L M The circuit consisting of transistor Q2 and resistor R2 excites transformer TR1, with an excitation current I. LM Leakage inductance L increases linearly from zero. K And excitation inductance L M Energy is stored, and the secondary rectifier diode D1 is reverse-biased and therefore does not supply power to the output Vo during this stage.

[0040] Furthermore, during the time interval t0-t1, V SW The voltage V across the primary winding is low. Np Equal to bus voltage V BULK The voltage V across the auxiliary winding Naux equal in To adjust the turns ratio of the auxiliary winding and the primary winding, VS is clamped to -200mV, and the current I flowing out of the VS pin... VS It can be represented as:

[0041]

[0042] In a common implementation, The voltage is in the tens of volts, while the bus voltage can usually reach several hundred volts. Therefore, compared with the traditional method of directly connecting a resistor to the bus voltage to divide it for detection, the resistance values ​​of R3 and R4 can be reduced by an order of magnitude while consuming the same static current, thus saving the cost of external components. The values ​​of R3 and R4 are on the same order of magnitude, and in equation (1) The absolute value is much greater than The absolute value of , and equation (1) In molecules It is also much greater than -200mV, therefore equation (1) can be approximately expressed as:

[0043]

[0044] That is, Ivs and bus voltage V BULLK Linear correlation.

[0045] At time t1, the control signal Vgs_Q2 of transistor Q2 goes low, and transistor Q2 is turned off.

[0046] During the time interval t1-t2, both transistors Q1 and Q2 are turned off; this period is the first dead time. Therefore, the leakage inductance L... KMagnetizing inductance L M The drain-source capacitors of transistors Q1 and Q2 will resonate, transferring energy from the leakage inductance Lk and magnetizing inductance Lm to the drain-source capacitors of transistors Q1 and Q2, thus increasing V. SW Increase; when V SW Rise to When D1 is turned on, the active flyback converter supplies power to the output, where V represents the turns ratio of the primary and secondary transformers. D1 This is the forward voltage drop of the secondary rectifier diode D1.

[0047] At time t2, the control signal Vgs_Q1 of transistor Q1 goes high, and transistor Q1 is turned on.

[0048] During the time period t2-t3, transistor Q1 is on, transistor Q2 is off, the secondary rectifier diode D1 is forward-biased, and the magnetizing inductor L... M The energy is transferred to the secondary side output Vo, and the voltage V across the primary winding is... Np clamped to in I is the turns ratio of the primary winding and the secondary winding. LM The voltage V across the auxiliary winding decreases linearly. Naux equal in The turns ratio of the auxiliary winding and the secondary winding is VS equal to When I LM When the voltage drops to zero, the secondary rectifier diode D1 turns off, and the magnetizing inductor L... M The voltage across the two ends is no longer affected by V. O Clamped, at this time the leakage inductance L K Magnetizing inductance L M and clamping capacitor C CLAMP Resonance occurs, causing the excitation current I LM Resonance in the negative direction.

[0049] At time t3, the control signal Vgs_Q1 for transistor Q1 goes low, and transistor Q1 is turned off.

[0050] During the time interval t3-t4, both transistors Q1 and Q2 are turned off. This period is the second dead time because the negative magnetizing current I... LM To continue the flow, therefore leakage inductance L K Magnetizing inductance L M The drain-source capacitances of transistors Q1 and Q2 will resonate, and the drain-source capacitance and leakage inductance L of transistor Q1 will also resonate. K And excitation inductance L M The energy is transferred to the drain-source capacitor of transistor Q2, making V SW reduce.

[0051] It should be noted that V during the first dead zone time SW The increase is due to the excitation current I at time t1, the beginning of the first dead time. LM The initial current direction is positive, i.e., I LM To V SW Node flow; V during the second dead time SW The decrease is due to the excitation current I at the beginning of the second dead time, t3. LM The initial current direction is negative, i.e., I LM From V SW Node outflow;

[0052] At time t4, V SW When the voltage drops to zero, the control signal Vgs_Q2 for transistor Q2 goes high, achieving zero-voltage turn-on for transistor Q2. This completes one switching cycle of the active clamp flyback converter, which will then repeat the same control logic and operating process.

[0053] Figure 3 The specific circuit structure of the bus voltage sampling module 312 is shown, where VDD is the power rail of the control circuit 31 powered by the auxiliary winding Na, VDDL is the low-voltage power rail generated inside the control circuit 31, Vbias is the input bias voltage, I1 and I2 are the input bias currents, where I2 is a positive temperature coefficient current, and the temperature coefficient of the sum of the currents I1 and I2 is also a positive temperature coefficient, TG1 is the first transmission gate, TG2 is the second transmission gate, and OP1 is the first operational amplifier.

[0054] Combination Figure 2 , Figure 3 The working principle of the bus voltage sampling module 312 shown is as follows:

[0055] At time t0, Vgs_Q2 goes high, the output of Buffer1 goes high, and the first input of AND1 goes high. However, due to the limited output capability of Buffer1, the low-pass filter formed by R10 and C6 prevents the second input of AND1 from going high, and the output of AND1 remains low. TG1 is turned off and TG2 is turned on. At this time, the voltage across C4 and C5 stores the bus voltage information sampled in the previous switching cycle and outputs it through OP1 buffer.

[0056] From t0 to t0+t delay During the time period, Vgs_Q2 is high, Buffer1 charges the upper plate of the sixth capacitor, and the output of AND1 remains low. MN1 and MN2 are matched MOSFETs, meaning they have the same width-to-length ratio but different parallel connections. MN2 has a larger parallel connection, which clamps VS. The Vgs of MN1 and MN2 are approximately equal. R9 is a small resistor. Without considering the changes in R9 and the threshold voltage, VS can be approximately expressed as:

[0057] VS=0V-(I1+I2)*R8………………………………………………………………(3),

[0058] In one possible implementation, VS is clamped to -200mV.

[0059] The bus voltage sampling module circuit has a negative feedback loop, which contains a nested positive feedback loop. Specifically, in the negative feedback loop, when the source voltage of MN2 decreases, MN2, acting as a common-gate amplifier, causes its drain (denoted as V1) to decrease. MP1, acting as a common-source amplifier with resistor (R5) negative feedback, causes the gate voltage of MN2 to rise. MN2, acting as a source follower amplifier, then causes its source voltage to rise, thus forming voltage negative feedback. This reduces the source impedance of MN2, improving the accuracy of the negative voltage clamping. In the nested positive feedback loop, when V1 decreases, MP1, acting as a common-source amplifier with resistor (R5) negative feedback, causes the gate voltage of MN2 to rise. MN2, acting as a common-source amplifier, causes V1 to decrease, thus forming positive feedback. To ensure loop stability, the gain of the positive feedback needs to be less than 1, i.e., satisfying the following condition:

[0060]

[0061] In the formula, G m2 For MN2 as the equivalent transconductance of a common-source amplifier with resistive negative feedback, g m1 It represents the transconductance of MN1.

[0062] From t0 to t0+t delay During the time interval, if I vs flows through R6, V1 can be represented as:

[0063]

[0064] This converts the current information carried by Ivs, which is related to the bus voltage, into voltage information V1. When Ivs is too large, i.e., the bus voltage V... BULK If the value is too high, it will cause V1 to be too low. When V1 < V bias -V TH_MN3 When, where V TH_MN3 The threshold voltage of MN3 is set. When MN3 is turned on, it clamps V1 to prevent it from decreasing further, thus ensuring that V1 does not drop too low and cause MN2 to enter the linear region, losing its clamping ability on VS. Simultaneously, even if the bus voltage V... BULK As Ivs increases further, V1 is clamped by MN3. The current flowing through R6 remains unchanged. That is, the current with the further increase in Ivs flows through MN3 and is drawn from VDD, which limits the upper limit of the current flowing through R6 and reduces the design difficulty of the maximum load capacity of the internal power rail VDDL of the chip.

[0065] Furthermore, MN1 and MN2 operate in the saturation region, and the channel current I in the NMOS transistor saturation region is... DS It can be represented as:

[0066]

[0067] In the formula, β is a constant related to the MOSFET, and the error of VS clamping is compared with that in formula (1). It is much smaller, therefore we can consider I for MN2 DS If the temperature coefficient of Vth remains constant, it will linearly add to Vgs. At room temperature, Vth can be considered to decrease with increasing temperature, causing Vgs of MN2 to decrease. To maintain the source voltage of MN2 and thus obtain better VS clamping accuracy, the gate voltage of MN2 needs to be reduced simultaneously, i.e., the gate voltage of MN2 needs to have a negative temperature coefficient. Although the gate voltage of MN1 also has a negative temperature coefficient, the temperature coefficients of their threshold voltages do not match because the source voltages of MN1 and MN2 are different. To compensate for this difference, this invention introduces an additional negative temperature coefficient on the voltage drop across R8. The design goal is:

[0068]

[0069] At t0+t delay At a certain moment, V2 flips high, V3 flips low, TG1 turns on, TG2 turns off, and the voltage information on IVS begins to be transmitted to the voltage across C4. To ensure that the current information of IVS can be correctly stored on the voltage across C4, the time constant R6*C4 of the low-pass filter formed by R6 and C4 needs to be less than the minimum switching period of the flyback converter multiplied by the minimum duty cycle and then subtracted from t. delay That is, it must satisfy:

[0070] R6*C6<MIN(T)*MIN(D)-t dealy .......................................(8),

[0071] In the formula, MIN(T) is the minimum switching period of the flyback converter, and MNI(D) is the minimum duty cycle of the flyback converter.

[0072] The delay t of AND1 flipping up, which is composed of Buffer1, R10, C6, and AND1. delay This is to match the delay t between the Q2 control signal Vgs_Q2 from the chip turning high and the power transistor turning on in practical applications. delay_Q2 , t delay It needs to be greater than t delay_Q2 .

[0073] At t0+tdelay During the time interval t1, the information of Ivs, which carries the magnitude of the bus voltage, is gradually transferred to the voltage across C4. After reaching a steady state, V1 can be expressed as equation (5).

[0074] At time t1, Vgs_Q2 goes low, V2 goes low, V3 goes high, TG1 is turned off, TG2 is turned on, and C4 and C5 share charge. The capacitance of C4 needs to be much larger than that of C5, so that after reaching steady state, the voltage of the lower plates of C4 and C5 is approximately equal to equation (5), and is output to the output VOUT of the bus voltage sampling module through OP1 connected as a buffer. VOUT can be expressed as:

[0075]

[0076] This enables the sampling and storage of bus voltage.

[0077] In summary, the bus voltage sampling module clamps VS to -200mV when VS is negative. During the time interval t0 to t1 within each switching cycle, the module outputs the bus voltage sampled in the previous switching cycle; at t0+t... delay The bus voltage is sampled during the time period t1 and stored in C4; during the time period from t1 to t4, the module outputs the bus voltage sampled in this switching cycle.

[0078] In summary, the bus voltage sampling module of this invention employs a negative feedback loop to reduce output impedance and introduces negative temperature coefficient compensation to achieve higher clamping accuracy in negative voltage clamping. For bus voltage sampling, a negative voltage clamping function is designed, and the linear correlation between the auxiliary winding voltage and the bus voltage within a specific switching cycle is utilized to convert the auxiliary winding voltage into current information, which is then converted back into voltage information using a resistor. Regarding the storage of sampled bus voltage information, a sampling and storage system consisting of two sets of capacitors is designed based on the switching sequence of the power transistors, ensuring that bus voltage information is available for subsequent circuits at all times. Compared to the traditional method of directly sampling bus voltage using voltage divider resistors, the bus voltage sampling module of this invention shifts the sampling of bus voltage to a lower voltage domain, thus allowing the use of smaller resistors and reducing the overhead of external components.

[0079] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An active flyback converter comprising a transformer, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first diode, a second diode, a leakage inductance and a control circuit; the transformer has a primary winding, a secondary winding and an auxiliary winding, wherein the same name end of the primary winding is connected to a bus voltage through the leakage inductance; one end of the first capacitor is connected to the bus voltage, and the other end of the first capacitor is connected to the ground; the drain of the first switch tube is connected to the bus voltage through a circuit composed of the first resistor and the second capacitor in parallel, the gate and the source of the first switch tube are connected to the control circuit, and the source of the first switch tube is also connected to the drain of the second switch tube and the different name end of the primary winding; the gate and the source of the second switch tube are connected to the control circuit, and the source of the second switch tube is also connected to the ground through the second resistor; the different name end of the auxiliary winding is connected to the anode of the second diode, the cathode of the second diode is connected to the control circuit and one end of the third capacitor, and the same name end of the auxiliary winding, one end of the fourth resistor and the other end of the third capacitor are connected to the ground; the different name end of the auxiliary winding is connected to one end of the third resistor, and the other end of the third resistor is connected to the control circuit and the other end of the fourth resistor; the different name end of the secondary winding is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the fourth capacitor, and the same name end of the secondary winding and the other end of the fourth capacitor are connected to the ground; characterized in that the control circuit comprises a driving module and a bus voltage sampling module; wherein the driving module is connected to the gate and the source of the first switch tube, and the gate and the source of the second switch tube; the bus voltage sampling module comprises a first bias current, a second bias current, a first low-voltage NMOS tube, a second low-voltage NMOS tube, a third low-voltage NMOS tube, a first high-voltage NMOS tube, a first low-voltage PMOS tube, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first buffer, a first AND gate, a first inverter, a first transmission gate, a second transmission gate and a first operational amplifier; wherein the first bias current and the second bias current form a parallel circuit, and the output current of the parallel circuit is connected to the gate end of the first low-voltage NMOS tube and one end of the eighth resistor; the other end of the eighth resistor is connected to the drain end of the first low-voltage NMOS tube, the drain end of the first low-voltage PMOS tube and the gate end of the second low-voltage NMOS tube; the source end of the first low-voltage NMOS tube is connected to the ground; one end of the fifth resistor is connected to one end of the sixth resistor, the gate end of the first high-voltage NMOS tube, one end of the fifth capacitor and one end of the sixth capacitor; the other end of the fifth resistor is connected to the source end of the first low-voltage PMOS tube; the gate end of the first low-voltage PMOS tube is connected to the other end of the sixth resistor, the drain end of the second low-voltage NMOS tube, the source end of the third low-voltage NMOS tube and the input of the first transmission gate; the cathode of the second diode is connected to the drain end of the first high-voltage NMOS tube; the source end of the first high-voltage NMOS tube is connected to one end of the seventh resistor; the other end of the seventh resistor is connected to the drain end of the third low-voltage NMOS tube; the gate end of the third low-voltage NMOS tube is connected to the first input bias voltage; The source end of the second low-voltage NMOS tube is connected to the other end of the third resistor through the ninth resistor; the output of the first transmission gate is connected to the other end of the fifth capacitor and the input of the second transmission gate; the non-inverted control end of the first transmission gate is connected to the output of the first AND gate, the input of the first inverter and the inverted control end of the second transmission gate; the inverted control end of the first transmission gate is connected to the output of the first inverter and the non-inverted control end of the second transmission gate; The output of the second transmission gate is connected to the other end of the sixth capacitor and the positive input end of the first operational amplifier; the negative input end of the first operational amplifier is connected to the output of the first operational amplifier; the input of the first buffer is connected to the control signal Vgs_Q2 of the second switch tube, Vgs_Q2=VG2-VS2, the output of the first buffer is connected to the first input of the first AND gate and one end of the tenth resistor; the other end of the tenth resistor is connected to one end of the seventh capacitor and the second input of the first AND gate; the other end of the seventh capacitor is connected to the ground.

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