A high code rate narrow correlator generation method and apparatus
By applying a non-integer clock delay to the local code sequence using a fractional delay filter, leading, instantaneous, and lagging code sequences are generated. This solves the problem of accurate delay processing of narrow correlators under high code rates and low system sampling rates, improves the tracking accuracy of microwave signals, and achieves picosecond-level time synchronization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF RADIO METROLOGY & MEASUREMENT
- Filing Date
- 2022-12-30
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies struggle to achieve precise delay processing for narrow correlators at high code rates and low system sampling rates, especially in microwave networking between moving platforms where nanosecond-level errors caused by multipath signal errors cannot be effectively overcome.
A fractional delay filter is used to precisely delay the local code sequence with a non-integer clock. Leading, instantaneous, and lagging code sequences are generated through level transformation and fractional clock delay to achieve a correlation spacing of 0.1 chips.
It achieves precise delay processing of narrow correlators under high code rates and low system sampling rates, improves the accuracy of microwave signal tracking loops, and achieves picosecond-level time synchronization.
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Figure CN116232306B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-precision microwave bidirectional time synchronization, and in particular to a method and apparatus for generating a high code rate narrow correlator. Background Technology
[0002] Two-way time comparison is currently recognized internationally as the most accurate time comparison method, widely used for remote comparison of high-precision time and frequency values, and its position in time and frequency transmission and tracing methods is irreplaceable. Two-way time comparison utilizes spread spectrum modulation technology to perform high-precision spread spectrum modulation and transmission of relevant information of timing signals. The signals are transmitted via satellite, microwave, or fiber optic links. Remote comparison stations rapidly acquire, precisely track, and accurately calculate the signal propagation delay. By exchanging propagation delay data, the time difference information between comparison stations can be accurately obtained, achieving nanosecond-level time synchronization. The two-way method is widely used in various fields such as satellite navigation, deep space exploration, and UAV formation.
[0003] Currently, the time comparison requirements for microwave networking between mobile platforms are becoming increasingly stringent, with some specific scenarios requiring picosecond (ps) speeds, or 1×10⁻⁶ seconds per second. -12 Seconds. Dynamic platforms often operate in densely populated environments such as urban buildings and buildings, and multipath signals are a significant error term in microwave two-way time comparisons, often reaching the nanosecond (ns) level, or 1 × 10⁻⁶. -9 The time difference of a single second places extremely stringent requirements on the tracking loop of the microwave signal. To ensure system performance, system design and optimization are generally carried out in two aspects. On the one hand, to overcome the influence of multipath effects, a narrow correlator tracking method is adopted, where the lead-lag correlation interval is much smaller than the duration of a single chip, sometimes even as small as 0.01 chips. On the other hand, to improve bidirectional time comparison performance, high code rate signals of 100MHz or even several hundred MHz are generally used for bidirectional time comparison. Back-end processing equipment uses zero-IF reception to reduce power consumption and improve processing capabilities. The system sampling rate of this method is generally slightly higher than twice the code rate, i.e., above 200MHz. However, due to the limitations of the processing speed of back-end logic devices, this sampling rate cannot be increased indefinitely. It can be seen that the above two aspects are contradictory. That is, when the sampling rate is not high enough, the traditional method of controlling the lead-lag of the code by shifting an integer number of clock cycles cannot achieve a delay accuracy of 0.1 or even 0.01 chips, and new methods for delay processing need to be found. Summary of the Invention
[0004] The purpose of this invention is to provide a method and apparatus for generating a high code rate narrow correlator. By using a fractional delay filter to precisely delay the generated local code sequence with a non-integer clock, the accurate generation of lead and lag codes is achieved, thus solving the problem of generating narrow correlators with high code rates and low system sampling rates.
[0005] In a first aspect, the present invention provides a method for generating a high code rate narrow correlator, comprising the following steps:
[0006] The local code sequence is stored in the logic device memory. The local code sequence is a pseudo-random sequence of 0 / 1 levels.
[0007] The local code sequence is level-shifted, keeping the 1 level unchanged and changing the 0 level to -1 level;
[0008] The local code sequence after level conversion is subjected to fractional clock delay to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the technical sequence are both 0.1 chips.
[0009] Compared with existing technologies, this method uses a fractional delay filter to precisely delay the generated local code sequence with a non-integer clock, thereby achieving accurate generation of lead and lag codes and solving the problem of narrow correlator generation at high code rates and low system sampling rates.
[0010] As one possible implementation, the system clock is set to 250MHz, the code rate to 100MHz, and the lead / lag correlation interval to 0.1 chips. Three code sequences are to be generated: a lead sequence with a 0.1-chip lag, an instantaneous sequence with a 0.2-chip lag, and a lag sequence with a 0.3-chip lag. Based on this, the clock periods required to delay the level-converted local code sequences are determined to be 0.04, 0.08, and 0.12, respectively. Fractional delay filters are designed using these values, and their parameters are calculated. The level-converted local code sequences are then subjected to fractional delay filtering using these three filters to obtain the lead, instantaneous, and lag sequences.
[0011] As one possible implementation, the fractional delay filter is a low-order fractional delay filter.
[0012] As one possible implementation, driven by the system clock, a numerically controlled oscillator method is used to continuously change the incrementing query address and read the generated local code sequence in real time.
[0013] As one possible implementation, the clock period is determined in the following way:
[0014] Number of delayed chips * (code rate / system clock).
[0015] Secondly, a high code rate narrow correlator generation device, characterized in that it comprises:
[0016] A logic device memory for storing a local code sequence, wherein the local code sequence is a 0 / 1 level pseudo-random sequence;
[0017] A level converter is used to perform level transformation on the local code sequence, keeping the 1 level unchanged and transforming the 0 level to the -1 level;
[0018] A fractional clock delayer is used to perform a fractional clock delay on the local code sequence after level conversion to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the technical sequence are both 0.1 chips.
[0019] As one possible implementation, the system clock is set to 250MHz, the code rate to 100MHz, and the lead / lag correlation interval to 0.1 chips. Three code sequences are to be generated: a lead sequence with a 0.1-chip lag, an instantaneous sequence with a 0.2-chip lag, and a lag sequence with a 0.3-chip lag. Based on this, the clock periods required to delay the level-converted local code sequences are determined to be 0.04, 0.08, and 0.12, respectively. Fractional delay filters are designed using these values, and the parameters of the three fractional delay filters are calculated. The level-converted local code sequences are then subjected to fractional delay filtering using these three fractional delay filters to obtain the lead sequence, the instantaneous sequence, and the lag sequence.
[0020] As one possible implementation, the fractional delay filter is a low-order fractional delay filter.
[0021] As one possible implementation, driven by the system clock, a numerically controlled oscillator method is used to continuously change the incrementing query address and read the generated local code sequence in real time.
[0022] As one possible implementation, the clock period is determined in the following way:
[0023] Number of delayed chips * (code rate / system clock).
[0024] Compared with the prior art, the beneficial effects of the high code rate narrow correlator generation device provided by the present invention are the same as those of the high code rate narrow correlator generation method provided by the above-mentioned technical solutions, and will not be repeated here. Attached Figure Description
[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0026] Figure 1 A flowchart of a high code rate narrow correlator generation method provided in an embodiment of the present invention;
[0027] Figure 2 The local code sequence provided in the embodiments of the present invention;
[0028] Figure 3 Level conversion of local code sequences provided in embodiments of the present invention;
[0029] Figure 4 The present invention provides a graph of leading sequence, instantaneous sequence and lag sequence obtained by performing fractional delay filtering on local code sequence;
[0030] Figure 5 This is a structural block diagram of a high code rate narrow correlator generation device provided in an embodiment of the present invention. Detailed Implementation
[0031] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0032] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0034] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0035] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0036] See Figure 1 Firstly, this invention provides a method for generating a high code rate narrow correlator. Assuming a system clock of 250MHz and a code rate of 100MHz, the minimum delay achieved using the traditional clock cycle shift delay method is only 100MHz / 250MHz = 0.4 chips, resulting in a narrow correlator lead-lag interval of 0.4 × 2 = 0.8 chips. However, a finer correlation spacing can be achieved using a fractional delay filter. Specifically, using the high code rate narrow correlator generation method provided in this invention, assuming the lead-lag correlation spacing is set to 0.2 chips, the minimum delay required is 0.1 chips. This can be achieved through the following steps:
[0037] S10. Store the local code sequence in the logic device memory. The local code sequence is a pseudo-random sequence of 0 / 1 levels. See also Figure 2 Driven by the system clock, the local code sequence is generated in real time by continuously changing the incrementing query address using a numerically controlled oscillator method.
[0038] S11. Perform level transformation on the local code sequence, keeping the 1 level unchanged and transforming the 0 level to -1 level. See also Figure 3 The code level generated in step S10 is a logic 0 / 1 level. A 0 level represents no information and cannot be directly delayed by a fractional delay filter. The 0 level needs to be transformed into a -1 level, and the original 1-bit data needs to be transformed into 2-bit data to represent a negative value. The binary two's complement 01 represents level 1, and the binary two's complement 11 represents level -1.
[0039] S12. Perform fractional clock delay on the local code sequence after level conversion to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the technical sequence are both 0.1 chips.
[0040] See Figure 4To achieve a lead-lag correlation interval of 0.1 chips, three code sequences are needed: a lead sequence with a 0.1-chip lag, an instant sequence with a 0.2-chip lag, and a lag sequence with a 0.3-chip lag. Based on these chip values, the original code sequences need to be delayed by 0.1*100MHz / 250MHz = 0.04 clock cycles, 0.2*100MHz / 250MHz = 0.08 clock cycles, and 0.3*100MHz / 250MHz = 0.12 clock cycles, respectively. Using these 0.04, 0.08, and 0.12 clock cycle parameters, fractional delay filters are designed, and the parameters for the three fractional delay filters are calculated. These fractional delay filters are then applied to the local code generated in the second step to obtain the lead, instant, and lag sequences. Because the fractional delay filters are band-limited, the resulting new code sequences have a smoother transition.
[0041] In practical implementation, in order to save back-end logic resources, the order of the fractional delay filter used should be as small as possible to improve system stability. At the same time, since the higher the order of the delay filter, the greater the overall delay, the more lagging the response of the generated narrow correlator, which has a certain impact on the dynamic design of the receiver, it is also required that the order of the fractional delay filter used to generate the narrow correlator be as small as possible.
[0042] Compared with existing technologies, this method uses a fractional delay filter to precisely delay the generated local code sequence with a non-integer clock, thereby achieving accurate generation of lead and lag codes and solving the problem of narrow correlator generation at high code rates and low system sampling rates.
[0043] Secondly, see Figure 5 A high code rate narrow correlator generation device, comprising:
[0044] A logic device memory for storing a local code sequence, wherein the local code sequence is a 0 / 1 level pseudo-random sequence;
[0045] A level converter is used to perform level transformation on the local code sequence, keeping the 1 level unchanged and transforming the 0 level to the -1 level;
[0046] A fractional clock delayer is used to perform a fractional clock delay on the local code sequence after level conversion to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the technical sequence are both 0.1 chips.
[0047] As one possible implementation, the system clock is set to 250MHz, the code rate to 100MHz, and the lead / lag correlation interval to 0.1 chips. Three code sequences are to be generated: a lead sequence with a 0.1-chip lag, an instantaneous sequence with a 0.2-chip lag, and a lag sequence with a 0.3-chip lag. Based on this, the clock periods required to delay the level-converted local code sequences are determined to be 0.04, 0.08, and 0.12, respectively. Fractional delay filters are designed using these values, and the parameters of the three fractional delay filters are calculated. The level-converted local code sequences are then subjected to fractional delay filtering using these three fractional delay filters to obtain the lead sequence, the instantaneous sequence, and the lag sequence.
[0048] As one possible implementation, the fractional delay filter is a low-order fractional delay filter.
[0049] As one possible implementation, driven by the system clock, a numerically controlled oscillator method is used to continuously change the incrementing query address and read the generated local code sequence in real time.
[0050] As one possible implementation, the clock period is determined in the following way:
[0051] Number of delayed chips * (code rate / system clock).
[0052] Compared with the prior art, the beneficial effects of the high code rate narrow correlator generation device provided by the present invention are the same as those of the high code rate narrow correlator generation method provided by the above-mentioned technical solutions, and will not be repeated here.
[0053] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0054] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for generating a high code rate narrow correlator, characterized in that, Includes the following steps: The local code sequence is stored in the logic device memory, and the local code sequence is a 0 / 1 level pseudo-random sequence; The local code sequence is level-shifted, keeping the 1 level unchanged and shifting the 0 level to -1 level; The local code sequence after level conversion is subjected to fractional clock delay to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the instantaneous sequence are both 0.1 chips; The system clock is set to 250MHz, the code rate to 100MHz, and the lead / lag correlation interval to 0.1 chips. Three code sequences are to be generated: a 0.1-chip lag lead sequence, a 0.2-chip lag instantaneous sequence, and a 0.3-chip lag lag sequence. Based on this, the clock periods required to delay the level-converted local code sequences are determined to be 0.04, 0.08, and 0.12, respectively. Fractional delay filters are designed using these values, and their parameters are calculated. The level-converted local code sequences are then subjected to fractional delay filtering using these three filters to obtain the lead, instantaneous, and lag sequences.
2. The method for generating a high code rate narrow correlator according to claim 1, characterized in that, The fractional delay filter is a low-order fractional delay filter.
3. The method for generating a high code rate narrow correlator according to claim 1, characterized in that, Driven by the system clock, the local code sequence is generated in real time by continuously changing the incrementing query address using a numerically controlled oscillator method.
4. The method for generating a high code rate narrow correlator according to claim 1, characterized in that, The clock period is determined in the following way: Number of delayed chips * (code rate / system clock).
5. A high code rate narrow correlator generation device, characterized in that, include: A logic device memory for storing a local code sequence, wherein the local code sequence is a 0 / 1 level pseudo-random sequence; A level converter is used to perform level transformation on the local code sequence, keeping the 1 level unchanged and transforming the 0 level to the -1 level; A fractional clock delayer is used to perform a fractional clock delay on the local code sequence after level conversion to obtain a leading sequence, an instantaneous sequence, and a lagging sequence; wherein the correlation interval between the leading sequence and the instantaneous sequence, and the correlation interval between the lagging sequence and the instantaneous sequence are both 0.1 chips. The system clock is set to 250MHz, the code rate to 100MHz, and the lead / lag correlation interval to 0.1 chips. Three code sequences are to be generated: a 0.1-chip lag lead sequence, a 0.2-chip lag instantaneous sequence, and a 0.3-chip lag lag sequence. Based on this, the clock periods required to delay the level-converted local code sequences are determined to be 0.04, 0.08, and 0.12, respectively. Fractional delay filters are designed using these values, and their parameters are calculated. The level-converted local code sequences are then subjected to fractional delay filtering using these three filters to obtain the lead, instantaneous, and lag sequences.
6. The high code rate narrow correlator generating apparatus according to claim 5, characterized in that, The fractional delay filter is a low-order fractional delay filter.
7. The high code rate narrow correlator generating apparatus according to claim 5, characterized in that, Driven by the system clock, the local code sequence is generated in real time by continuously changing the incrementing query address using a numerically controlled oscillator method.
8. The high code rate narrow correlator generating apparatus according to claim 7, characterized in that, Clock cycle through Determine using the following method: Number of delayed chips * (code rate / system clock).