Display substrate and preparation method thereof, display panel

Abstract

This application relates to a display substrate and its fabrication method, a display panel, and a display device. The display substrate includes a pixel circuit and a substrate. The pixel circuit is located on the substrate and includes: a driving transistor, a storage capacitor, a first initialization transistor, and a second initialization transistor. The gate of the driving transistor is a first metal layer; the first electrode of the storage capacitor is the first metal layer, and the second electrode of the storage capacitor is a second metal layer. The driving transistor is a top-gate thin-film transistor, and the first and second initialization transistors are bottom-gate thin-film transistors. The gates of the first and second initialization transistors are on the same shielding metal layer, and the orthographic projection of the second metal layer onto the substrate at least partially overlaps with the orthographic projection of the shielding metal layer onto the substrate. Using this display substrate can save layout design space.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate and its preparation method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is a technology that uses light-emitting materials to emit light when driven by an electric current to achieve display. OLED displays have advantages such as being ultra-lightweight, ultra-thin, high-brightness, wide viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing process, use of fewer raw materials, high luminous efficiency, and wide temperature range.

[0003] However, as PPI (Pixels Per Inch) increases, layout space becomes increasingly limited. Summary of the Invention

[0004] Therefore, it is necessary to provide a display substrate, its preparation method, display panel, and display device that can save layout design space to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display substrate, the display substrate including a pixel circuit and a substrate, the pixel circuit being located on the substrate, the pixel circuit including:

[0006] A driving transistor, wherein the gate of the driving transistor is a first metal layer, and the driving transistor is used to provide driving current to a light-emitting device;

[0007] A storage capacitor, wherein the first electrode of the storage capacitor is the first metal layer, the second electrode of the storage capacitor is the second metal layer, and the first electrode of the storage capacitor is connected to the gate of the driving transistor;

[0008] A first initialization transistor, the gate of the first initialization transistor is used to receive a first scan signal, the first terminal of the first initialization transistor is connected to the first plate of the storage capacitor and the second terminal of the driving transistor, and the second terminal of the first initialization transistor is used to receive a first initialization signal.

[0009] The second initialization transistor has a gate for receiving a second scan signal, a first electrode for receiving a second initialization signal, and a second electrode connected to the anode of the light-emitting device.

[0010] The driving transistor is a top-gate thin-film transistor, the first initialization transistor and the second initialization transistor are bottom-gate thin-film transistors, and the gates of the first initialization transistor and the second initialization transistor are the same shielding metal layer. The orthographic projection of the second metal layer on the substrate and the orthographic projection of the shielding metal layer on the substrate at least partially overlap.

[0011] In one embodiment, the pixel circuit further includes:

[0012] A data writing transistor, wherein the gate of the data writing transistor is used to receive a third scan signal, the first terminal of the data writing transistor is used to receive a data voltage, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor;

[0013] A first light-emitting control transistor, wherein the gate of the first light-emitting control transistor is used to receive a light-emitting control signal, the first terminal of the first light-emitting control transistor is used to receive a first power supply voltage, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor;

[0014] The second light-emitting control transistor has a gate for receiving the light-emitting control signal, a first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and a second terminal of the second light-emitting control transistor is connected to the anode of the light-emitting device.

[0015] A threshold compensation transistor, wherein the gate of the threshold compensation transistor is used to receive a fourth scan signal, the first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the gate of the driving transistor;

[0016] The data writing transistor, the first light-emitting control transistor, the second light-emitting control transistor, and the threshold compensation transistor are all top-gate thin-film transistors.

[0017] In one embodiment, the bottom-gate thin-film transistor includes the shielding metal layer and a first active layer, the shielding metal layer being located between the substrate and the first active layer.

[0018] In one embodiment, the display substrate further includes a first insulating layer located between the shielding metal layer and the first active layer.

[0019] In one embodiment, the display substrate further includes a second insulating layer located between the shielding metal layer and the substrate.

[0020] In one embodiment, the top-gate thin-film transistor includes a first metal layer and a second active layer, the second active layer being located between the substrate and the first metal layer, the first metal layer serving as the gate of the top-gate thin-film transistor, and the orthographic projection of the second active layer on the substrate at least partially overlapping the orthographic projection of the first metal layer on the substrate.

[0021] In one embodiment, the display substrate further includes an insulating dielectric layer located between the first metal layer and the second metal layer.

[0022] Secondly, this application provides a display panel, including the display substrate described above.

[0023] Thirdly, this application provides a method for preparing a display substrate, the method comprising:

[0024] Provide substrate;

[0025] A pixel circuit is formed on the substrate, wherein the pixel circuit includes a driving transistor, a storage capacitor, a first initialization transistor, and a second initialization transistor. The driving transistor is a top-gate thin-film transistor, and its gate is a first metal layer. The first electrode of the storage capacitor is a first metal layer, and its second electrode is a second metal layer. The first electrode of the storage capacitor is connected to the gate of the driving transistor. The first initialization transistor and the second initialization transistor are bottom-gate thin-film transistors with their gates sharing the same shielding metal layer. The orthographic projection of the second metal layer on the substrate at least partially overlaps with the orthographic projection of the shielding metal layer on the substrate.

[0026] In one embodiment, forming the pixel circuit on the substrate includes:

[0027] A shielding metal layer is formed on the upper surface of the substrate;

[0028] A first insulating layer is formed on the exposed surfaces of the substrate and the shielding metal layer;

[0029] A first active layer and a second active layer are formed on the surface of the first insulating layer away from the substrate;

[0030] A second insulating layer is formed on the exposed surfaces of the first insulating layer, the first active layer, and the second active layer;

[0031] A first metal layer is formed on the surface of the second insulating layer away from the substrate;

[0032] An insulating dielectric layer is formed on the exposed surfaces of the second insulating layer and the first metal layer;

[0033] A second metal layer is formed on the surface of the insulating dielectric layer away from the substrate, wherein the orthographic projection of the second metal layer on the substrate at least partially overlaps with the orthographic projection of the shielding metal layer on the substrate.

[0034] The aforementioned display substrate, display panel, and display substrate fabrication method utilize bottom-gate thin-film transistors (WTMTs) for both the first and second initialization transistors, and ensures that their gates are connected to the same shielding metal layer. This places the shielding metal layer below the active layer and creates a greater distance between the shielding metal layer and the second metal layer. In related technologies, top-gate WTMTs are used, with the first metal layer above the active layer and a thin insulating dielectric layer between the first and second metal layers. To prevent short circuits, sufficient spacing is maintained between the first and second metal layers in the column direction, resulting in increased pixel spacing in the pixel circuit column direction. However, in this application, because the shielding metal layer and the second metal layer are far apart, the spacing between them does not need to be considered in the layout design, allowing the orthogonal projections of the shielding metal layer and adjacent metal layers onto the substrate to overlap. Therefore, the overall circuit layout design can be altered, reducing the distance in the column direction and saving layout design space. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a layout design drawing of a display substrate according to an embodiment of this application;

[0037] Figure 2 This is a partial cross-sectional schematic diagram of a display substrate in one embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the pixel circuit structure in one embodiment of this application;

[0039] Figure 4 This is a layout design drawing of a display substrate in related technologies;

[0040] Figure 5 This is a partial cross-sectional schematic diagram of a display substrate in related technologies;

[0041] Figure 6 This is a schematic flowchart of a method for preparing a display substrate according to an embodiment of this application;

[0042] Figure 7 This is a flowchart illustrating the step of forming a pixel circuit on the substrate in one embodiment of this application. Detailed Implementation

[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0045] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0046] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0047] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0048] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0049] When a phrase such as “at least one of…” follows a list of elements, it modifies the entire list of elements, not individual elements within that list. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. As used in the application documents, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0050] Electronic or electrical devices and / or any other related devices or components (e.g., display devices including a display panel and a display panel driver, wherein the display panel driver further includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and a transmit driver) according to embodiments of the concepts described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Additionally, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in memory, which may be implemented in a computing device using standard storage devices such as random access memory (RAM). Computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present application.

[0051] While exemplary embodiments of the display module and the display device including the display module have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that the display module and the display device including the display module, constructed according to the principles of this application, may be implemented in ways other than those specifically described herein. This application is also defined in the claims and their equivalents.

[0052] As described in the background section, existing organic light-emitting diode (OLED) display technology is a technology that uses light-emitting materials to emit light under the drive of an electric current to achieve display. OLED displays have advantages such as being ultra-lightweight, ultra-thin, high-brightness, wide viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing process, use of fewer raw materials, high luminous efficiency, and wide temperature range.

[0053] However, as PPI (Pixels Per Inch) increases, layout space becomes increasingly limited.

[0054] For the reasons mentioned above, such as Figures 1 to 3 As shown, this application provides a display substrate, which includes a pixel circuit and a substrate 21. The pixel circuit is located on the substrate 21 and includes a driving transistor T0, a storage capacitor Cst, a first initialization transistor T1, and a second initialization transistor T2.

[0055] The gate of the driving transistor T0 is the first metal layer 23, and the driving transistor T0 is used to provide driving current to the light-emitting device.

[0056] The first electrode of the storage capacitor Cst is the first metal layer 23, and the second electrode of the storage capacitor is the second metal layer 27 (i.e., Figure 1 In M2), the first plate of the storage capacitor Cst is connected to the gate of the driving transistor T0.

[0057] A first initialization transistor T1, the gate of which is used to receive a first scan signal S1, the first terminal of which is connected to the first plate of the storage capacitor Cst and the gate of the driving transistor T0, and the first initialization transistor T1 is used to receive a first initialization signal Vref1.

[0058] A second initialization transistor T2 has its gate used to receive a second scan signal S2, its first terminal used to receive a second initialization signal Vref2, and its second terminal connected to the anode of the light-emitting device. The first initialization signal Vref1 and the second initialization signal Vref2 can be the same initialization signal.

[0059] In this design, the driving transistor T0 is a top-gate thin-film transistor, and the first initialization transistor T1 and the second initialization transistor T2 are bottom-gate thin-film transistors. The gates of the first initialization transistor T1 and the second initialization transistor T2 are connected to the same shielding metal layer. The orthographic projection of the second metal layer 27 onto the substrate 21 at least partially overlaps with the orthographic projection of the shielding metal layer 22 onto the substrate. The shielding metal layer 22 can be a back-side metal (BSM), and the following explanation will use BSM as an example.

[0060] In applications, thin-film transistors (TFTs) include an active layer and a gate layer. The active layer includes a channel region and source and drain regions located on either side of the channel region. With the substrate as the orientation downwards, the gate layer of a top-gate TFT is located above the active layer, while the gate layer of a bottom-gate TFT is located below the active layer.

[0061] In related technologies, the thin-film transistors in pixel circuits are all top-gate thin-film transistors, such as... Figure 4 and Figure 5 As shown, the top-gate thin-film transistor includes a first metal layer 12 and an active layer 13. The first metal layer 12 is above the active layer 13 and serves as the gate of the thin-film transistor. There is only one insulating dielectric layer 14 between the first metal layer 12 and the second metal layer 11. This insulating dielectric layer 14 is very thin. To avoid short circuits between the first metal layer 12 and the second metal layer 11, a barrier is set in the column direction (i.e.,...). Figure 4 The first metal layer 12 and the second metal layer 11 are spaced sufficiently in the Y direction, which results in an increase in the pixel spacing in the pixel circuit column direction.

[0062] Compared to existing technologies, in this embodiment, the thin-film transistors of the first initialization transistor T1 and the second initialization transistor T2 are bottom-gate thin-film transistors, and the gate is a shielding metal layer 22. In this case, since the shielding metal layer 22 is below the active layer 24 and the second metal layer 27 is above the active layer 24, and the distance between the shielding metal layer 22 and the second metal layer 27 is large, it is not necessary to consider the column orientation of the shielding metal layer 22 and the second metal layer 27 (i.e.,...). Figure 1The spacing in the Y direction (of the substrate). Therefore, in the layout design, the projections of the shielding metal layer 22 and the second metal layer 27 onto the substrate 21 can overlap, which can change the layout design of the entire circuit and reduce the distance in the column direction. At the same time, it can be understood that using the shielding metal layer 22 can block the bottom light and reduce screen mura; it can also increase transmittance and reduce the risk of excessively low highlights or abnormal fingerprint recognition.

[0063] The aforementioned display substrate uses bottom-gate thin-film transistors (TFTs) for both the first initialization transistor T1 and the second initialization transistor T2, and the gates of both transistors are connected to the same shielding metal layer 22. This places the shielding metal layer 22 below the active layer 24, resulting in a greater distance between the shielding metal layer 22 and the second metal layer 27. In related technologies, top-gate TFTs are used, with the first metal layer 12 above the active layer 13. Only a thin insulating dielectric layer 14 separates the first metal layer 12 from the second metal layer 11. To prevent short circuits between the first and second metal layers 12 and 11, a sufficient spacing is maintained between them in the column direction, leading to an increase in the pixel pitch in the column direction of the pixel circuit. However, in this application, because the shielding metal layer 22 is far from the second metal layer 27, the spacing between the second metal layer 27 and the shielding metal layer 22 does not need to be considered in the layout design. The orthographic projections of the shielding metal layer and adjacent metal layers on the substrate 21 can overlap. Therefore, the layout design of the entire circuit can be changed, the distance in the column direction can be reduced, and thus the layout design space can be saved.

[0064] In one embodiment, such as Figure 3 As shown, the pixel circuit further includes: a data writing transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, and a threshold compensation transistor T6, wherein the data writing transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, and the threshold compensation transistor T6 are top-gate thin-film transistors.

[0065] The gate of the data writing transistor T3 is used to receive the third scan signal S3, the first terminal of the data writing transistor T3 is used to receive the data voltage Vdata, and the second terminal of the data writing transistor T3 is connected to the first terminal of the driving transistor T0. During the first writing phase, in response to the third scan signal S3, the data writing transistor T3 turns on its first and second terminals, thereby causing the first terminal of the driving transistor T0 to receive the data voltage Vdata. The data voltage Vdata is written to the gate of the driving transistor T0 by the first and second terminals of the driving transistor T0 and the threshold compensation transistor T6.

[0066] The first light-emitting control transistor T4 has a gate for receiving a light-emitting control signal EM, a first terminal for receiving a first power supply voltage VDD, and a second terminal connected to the first terminal of the driving transistor T0.

[0067] The second light-emitting control transistor T5 has a gate for receiving the light-emitting control signal EM. The first terminal of the second light-emitting control transistor T5 is connected to the second terminal of the driving transistor T0, and the second terminal of the second light-emitting control transistor T5 is connected to the anode of the light-emitting device.

[0068] The first light-emitting control transistor T4 and the second light-emitting control transistor T5 both have switching functions. The gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM. The first terminal of the first light-emitting control transistor T4 receives the first power supply voltage VDD, and the second terminal is connected to the first terminal of the driving transistor T0. The first terminal of the second light-emitting control transistor T5 is connected to the second terminal of the driving transistor T0, and the second terminal of the second light-emitting control transistor T5 is connected to the anode of the light-emitting device. During the light-emitting stage, the first and second terminals of the first light-emitting control transistor T4 are turned on, the first terminal of the driving transistor T0 is connected to the first power supply voltage VDD, the first and second terminals of the second light-emitting control transistor T5 are turned on, the second terminal of the driving transistor T0 is connected to the light-emitting device, and then the second power supply voltage VSS is connected, so that the driving transistor T0 can provide driving current to the light-emitting device and drive the light-emitting device to emit light.

[0069] A threshold compensation transistor T6 is provided, the gate of which receives a fourth scan signal S4. The first terminal of the threshold compensation transistor T6 is connected to the second terminal of the driving transistor T0, and the second terminal of the threshold compensation transistor T6 is connected to the gate of the driving transistor T0. The fourth scan signal S4 and the third scan signal S3 can be the same scan signal. The threshold compensation transistor T6 has a threshold compensation function. Under the control of the fourth scan signal S4, the threshold compensation transistor T6 changes the switching state of its first and second terminals. When the first and second terminals of the driving transistor T0 and the threshold compensation transistor T6 are both on, the first terminal of the driving transistor T0 receives a data voltage Vdata. The data voltage Vdata is transmitted to the second terminal through the on-state driving transistor T0, and then to the gate of the driving transistor T0 via the threshold compensation transistor T6, thereby achieving threshold voltage compensation for the driving transistor T0.

[0070] In one embodiment, such as Figure 2As shown, the bottom-gate thin-film transistor includes a shielding metal layer 22 and a first active layer 24, with the shielding metal layer 22 located between the substrate 21 and the first active layer 24.

[0071] In this embodiment, by disposing the shielding metal layer 22 between the substrate 21 and the first active layer 24, the shielding metal layer 22 is positioned below the first active layer 24. When the shielding metal layer 22 serves as the gate layer, the first active layer 24 and the shielding metal layer 22 can form a bottom-gate thin-film transistor. Furthermore, by making the orthographic projection of the first active layer 24 onto the substrate 21 as close as possible to the orthographic projection of the shielding metal layer 22 onto the substrate 21, the area of ​​the bottom-gate thin-film transistor is defined, ensuring the rationality of the layout design.

[0072] In one embodiment, such as Figure 2 As shown, the display substrate further includes a first insulating layer 26, which is located between the shielding metal layer 22 and the first active layer 24.

[0073] In this embodiment, by providing a first insulating layer 26 between the shielding metal layer 22 and the first active layer 24, the shielding metal layer 22 and the first active layer 24 are isolated by the first insulating layer 26, thereby preventing a short circuit between the shielding metal layer 22 and the first active layer 24.

[0074] In one embodiment, such as Figure 2 As shown, the display substrate further includes a second insulating layer 25, which is located between the shielding metal layer 22 and the substrate 21.

[0075] In this embodiment, by providing a second insulating layer 25 between the shielding metal layer 22 and the substrate 21, the second insulating layer 25 further isolates the shielding metal layer 22, thereby preventing the shielding metal layer 22 from being electrically connected to the corresponding conductive layer.

[0076] In one embodiment, the top-gate thin-film transistor includes a first metal layer 23 and a second active layer (not shown). The second active layer is located between the substrate 21 and the first metal layer 23. The first metal layer 23 serves as the gate of the top-gate thin-film transistor. The orthographic projection of the second active layer on the substrate 21 at least partially overlaps with the orthographic projection of the first metal layer 23 on the substrate 21.

[0077] Since existing thin-film transistors mainly use top-gate thin-film transistors, by placing the second active layer between the substrate 21 and the first metal layer 23, the first metal layer 23 is located above the second active layer, and the first metal layer 23 and the second active layer form a top-gate thin-film transistor.

[0078] In one embodiment, such as Figure 2 As shown, the display substrate further includes an insulating dielectric layer 28, which is located between the first metal layer 23 and the second metal layer 27.

[0079] In this embodiment, an insulating dielectric layer 28 is disposed on the first metal layer 23 and the second metal layer 27, thereby spacing the first metal layer 23 and the second metal layer. The first metal layer 23 and the second metal layer serve as the first and second plates of a capacitor, and the first plate, the second plate, and the insulating dielectric layer 28 located between them form a capacitor. The first terminal of the storage capacitor is used to receive the first power supply voltage VDD, and the second terminal of the second storage capacitor is connected to the first terminal of the driving transistor T0 to maintain a stable voltage difference between the second terminal and the gate of the driving transistor T0 during the light-emitting phase.

[0080] Based on the same inventive concept, in one embodiment, this application also provides a display panel, including a display substrate as described in any of the above embodiments.

[0081] The aforementioned display panel includes the aforementioned display substrate, and the pixel circuitry included in the display substrate can save layout design space, thereby facilitating the optimization of the spatial arrangement of the display panel. In addition, the shielding metal layer 22 can block bottom light, reduce screen mura of the display panel, improve the display effect of the display panel, and at the same time help increase the light transmittance of the display panel, thereby reducing the risk of excessively low highlights or abnormal fingerprint recognition.

[0082] In one embodiment, this application provides a display device including a display panel as described above.

[0083] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0084] In one embodiment, such as Figure 6 As shown, this application also provides a method for fabricating a display substrate, the method comprising:

[0085] S601: Provides a substrate;

[0086] S602: A pixel circuit is formed on the substrate, wherein the pixel circuit includes a driving transistor, a storage capacitor, a first initialization transistor, and a second initialization transistor. The driving transistor is a top-gate thin-film transistor, and the gate of the driving transistor is a first metal layer. The first electrode of the storage capacitor is a first metal layer, and the second electrode of the storage capacitor is a second metal layer 27. The first electrode of the storage capacitor is connected to the gate of the driving transistor. The first initialization transistor and the second initialization transistor are bottom-gate thin-film transistors with their gates sharing the same shielding metal layer. The projection of the second metal layer 27 onto the substrate at least partially overlaps with the orthographic projection of the shielding metal layer onto the substrate.

[0087] In related technologies, the thin-film transistors in pixel circuits are all top-gate thin-film transistors, such as... Figure 4 and Figure 5 As shown, the top-gate thin-film transistor includes a first metal layer 12 and an active layer 13. The first metal layer 12 is above the active layer 13 and serves as the gate of the thin-film transistor. There is only one insulating dielectric layer 14 between the first metal layer 12 and the second metal layer 11. This insulating dielectric layer 14 is very thin. To avoid short circuits between the first metal layer 12 and the second metal layer 11, a barrier is set in the column direction (i.e.,...). Figure 4 The first metal layer 12 and the second metal layer 11 are spaced sufficiently in the Y direction, which results in an increase in the pixel spacing in the pixel circuit column direction.

[0088] Compared to existing technologies, in this embodiment, such as Figures 1 to 3 As shown, the thin-film transistors of the first initialization transistor T1 and the second initialization transistor T2 are bottom-gate thin-film transistors, and the gate is a shielding metal layer 22. In this case, since the shielding metal layer 22 is below the active layer 24 and the second metal layer 27 is above the active layer 24, and the distance between the shielding metal layer 22 and the second metal layer 27 is large, it is not necessary to consider the distance between the shielding metal layer 22 and the second metal layer 27 in the column direction (i.e., Figure 1 The spacing in the Y direction (of the substrate). Therefore, in the layout design, the projections of the shielding metal layer 22 and the second metal layer 27 onto the substrate 21 can overlap, which can change the layout design of the entire circuit and reduce the distance in the column direction. At the same time, it can be understood that using the shielding metal layer 22 can block the bottom light and reduce screen mura; it can also increase transmittance and reduce the risk of excessively low highlights or abnormal fingerprint recognition.

[0089] The aforementioned method for fabricating a display substrate uses bottom-gate thin-film transistors (WTMTs) for both the first and second initialization transistors, and makes their gates the same shielding metal layer. This places the shielding metal layer below the active layer and creates a greater distance between it and the second metal layer. In related technologies, top-gate WTMTs are used, with the first metal layer above the active layer. Only a thin insulating dielectric layer separates the first and second metal layers. To prevent short circuits, sufficient spacing is maintained between the first and second metal layers in the column direction, increasing the pixel pitch in the column direction of the pixel circuit. However, in this application, because the shielding metal layer is farther from the second metal layer, the spacing between them does not need to be considered in the layout design. The orthogonal projections of the shielding metal layer and adjacent metal layers on the substrate can overlap. Therefore, the overall circuit layout design can be modified, reducing the distance in the column direction and saving layout space.

[0090] In one embodiment, such as Figure 2 and Figure 7 As shown, forming a pixel circuit on the substrate includes:

[0091] S701: A shielding metal layer 22 is formed on the upper surface of the substrate 21;

[0092] S702: A first insulating layer 26 is formed on the exposed surfaces of the substrate 21 and the shielding metal layer 22;

[0093] S703: A first active layer 24 and a second active layer (not shown) are formed on the surface of the first insulating layer 26 away from the substrate 21;

[0094] S704: A second insulating layer 25 is formed on the exposed surfaces of the first insulating layer 26, the first active layer 24, and the second active layer;

[0095] S705: A first metal layer 23 is formed on the surface of the second insulating layer 25 away from the substrate 21;

[0096] S706: An insulating dielectric layer 28 is formed on the exposed surfaces of the second insulating layer 25 and the first metal layer 23;

[0097] S707: A second metal layer 27 is formed on the surface of the insulating dielectric layer 28 away from the substrate 21, wherein the orthographic projection of the second metal layer 27 on the substrate 21 at least partially overlaps with the orthographic projection of the shielding metal layer 22 on the substrate.

[0098] It is understood that a shielding metal layer 22 is first formed on the upper surface of the substrate 21, and then a first insulating layer 26 is formed on the exposed surfaces of the substrate 21 and the shielding metal layer 22. A first active layer 24 and a second active layer are formed on the surface of the first insulating layer 26 away from the substrate 21, so that the shielding metal layer 22 is located below the first active layer 24, and the shielding metal layer 22 and the first active layer 24 are isolated by the first insulating layer 26. The shielding metal layer 22 and the first active layer 24 can cooperate to form a first initialization transistor and a second initialization transistor, which are fixed-gate thin-film transistors, and the shielding metal layer 22 is the gate. A second insulating layer 25 is formed on the exposed surfaces of the first insulating layer 26, the first active layer 24, and the second active layer. After a first metal layer 23 is formed on the surface of the second insulating layer 25 away from the substrate 21, the second active layer and the first metal layer 23 can form the remaining thin-film transistors of the pixel circuit. Since the first metal layer 23 is located above the second active layer as the gate, the existing related technology process does not change significantly, thus avoiding a major change in the process flow. An insulating dielectric layer 28 is formed on the exposed surfaces of the second insulating layer 25 and the first metal layer 23;

[0099] After the second metal layer 27 is formed on the surface of the insulating dielectric layer 28 away from the substrate 21, the first metal layer 23, the insulating dielectric layer 28, and the second metal layer 27 can form a storage capacitor. Furthermore, since the spacing between the second metal layer 27 and the shielding metal layer 22 does not need to be considered in the layout design, the orthographic projection of the second metal layer 27 on the substrate 21 and the orthographic projection of the shielding metal layer 22 on the substrate 21 can overlap. Therefore, according to related technologies, the layout design of the entire circuit can be changed, reducing the distance in the column direction and thus saving layout design space.

[0100] In one embodiment, before forming a shielding metal layer on the upper surface of the substrate, the method may include: forming a second insulating layer on the upper surface of the substrate. That is, forming a second insulating layer on the upper surface of the substrate, and then forming a shielding metal layer on the surface of the second insulating layer away from the substrate.

[0101] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0102] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display substrate, characterized by, The display substrate comprises a pixel circuit and a substrate, the pixel circuit is located on the substrate, and the pixel circuit comprises: a driving transistor, a gate of the driving transistor is a first metal layer, and the driving transistor is used for providing a driving current to a light emitting device; a storage capacitor, a first plate of the storage capacitor is the first metal layer, a second plate of the storage capacitor is a second metal layer, and the first plate of the storage capacitor is connected with the gate of the driving transistor; a first initialization transistor, a gate of the first initialization transistor is used for receiving a first scanning signal, a first pole of the first initialization transistor is connected with the first plate of the storage capacitor and a second pole of the driving transistor, and a second pole of the first initialization transistor is used for receiving a first initialization signal; a second initialization transistor, a gate of the second initialization transistor is used for receiving a second scanning signal, a first pole of the second initialization transistor is used for receiving a second initialization signal, and a second pole of the second initialization transistor is connected with an anode of the light emitting device; wherein the driving transistor is a top-gate thin film transistor, the first initialization transistor and the second initialization transistor are bottom-gate thin film transistors, the gates of the first initialization transistor and the second initialization transistor are the same shielding metal layer, and a normal projection of the second metal layer on the substrate at least partially overlaps with a normal projection of the shielding metal layer on the substrate.

2. The display substrate of claim 1, wherein, The pixel circuit further comprises: a data writing transistor, a gate of the data writing transistor is used for receiving a third scanning signal, a first pole of the data writing transistor is used for receiving a data voltage, and a second pole of the data writing transistor is connected with a first pole of the driving transistor; a first light emitting control transistor, a gate of the first light emitting control transistor is used for receiving a light emitting control signal, a first pole of the first light emitting control transistor is used for receiving a first power voltage, and a second pole of the first light emitting control transistor is connected with the first pole of the driving transistor; a second light emitting control transistor, a gate of the second light emitting control transistor is used for receiving the light emitting control signal, a first pole of the second light emitting control transistor is connected with a second pole of the driving transistor, and a second pole of the second light emitting control transistor is connected with the anode of the light emitting device; a threshold value compensation transistor, a gate of the threshold value compensation transistor is used for receiving a fourth scanning signal, a first pole of the threshold value compensation transistor is connected with the second pole of the driving transistor, and a second pole of the threshold value compensation transistor is connected with the gate of the driving transistor; wherein the data writing transistor, the first light emitting control transistor, the second light emitting control transistor and the threshold value compensation transistor are top-gate thin film transistors. 3.The display substrate of claim 1, wherein, The bottom-gate thin film transistor comprises the shielding metal layer and a first active layer, and the shielding metal layer is located between the substrate and the first active layer.

4. The display substrate of claim 3, wherein, The display substrate further comprises a first insulating layer, and the first insulating layer is located between the shielding metal layer and the first active layer.

5. The display substrate of claim 4, wherein, The display substrate further comprises a second insulating layer between the shielding metal layer and the substrate. 6.The display substrate of claim 1, wherein, The top-gate thin film transistor comprises the first metal layer and a second active layer between the substrate and the first metal layer, the first metal layer serving as the gate of the top-gate thin film transistor, and a projection of the second active layer on the substrate at least partially overlaps a projection of the first metal layer on the substrate. 7.The display substrate of claim 6, wherein, The display substrate further comprises an insulating medium layer between the first metal layer and the second metal layer.

8. A display panel, characterized by, The display substrate according to any one of claims 1 to 7.

9. A method for preparing a display substrate, characterized in that, The method comprises: providing a substrate; forming a pixel circuit on the substrate, wherein the pixel circuit comprises a drive transistor, a storage capacitor, a first initialization transistor and a second initialization transistor, the drive transistor being a top-gate thin film transistor, a gate of the drive transistor being a first metal layer, a first plate of the storage capacitor being the first metal layer, a second plate of the storage capacitor being a second metal layer, the first plate of the storage capacitor being connected to the gate of the drive transistor, the first initialization transistor and the second initialization transistor being gates of bottom-gate thin film transistors, the gates of the first initialization transistor and the second initialization transistor sharing a same shielding metal layer, and a projection of the second metal layer on the substrate at least partially overlaps a projection of the shielding metal layer on the substrate.

10. The method of manufacturing the display substrate according to claim 9, wherein The forming a pixel circuit on the substrate comprises: forming a shielding metal layer on an upper surface of the substrate; forming a first insulating layer on surfaces of the substrate and the shielding metal layer exposed to the outside; forming a first active layer and a second active layer on a surface of the first insulating layer away from the substrate; forming a second insulating layer on surfaces of the first insulating layer, the first active layer and the second active layer exposed to the outside; forming a first metal layer on a surface of the second insulating layer away from the substrate; forming an insulating medium layer on surfaces of the second insulating layer and the first metal layer exposed to the outside; forming a second metal layer on a surface of the insulating medium layer away from the substrate, wherein a projection of the second metal layer on the substrate at least partially overlaps a projection of the shielding metal layer on the substrate.

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