Display substrate, display panel and display device

Abstract

A display substrate, a display panel and a display device, the display substrate comprising a first display area, the first display area comprising a plurality of pixel islands and a light-transmitting region between the plurality of pixel islands, the pixel islands comprising pixel circuits, the pixel circuits comprising a plurality of signal lines; between the pixel islands, a material of at least part of the signal lines adopts metal wiring. The present disclosure can better realize high-frequency display.

Description

[0001] The present application is a divisional application of patent application No. 202111088853.1, the original application date of which is September 16, 2021, the application number of which is 202111088853.1, and the title of the invention is "Display substrate, preparation method thereof, and display panel". TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, the technical field of display, and in particular, to a display substrate, a display panel and a display device. BACKGROUND

[0003] With the development of technology, the appearance of mobile terminals is increasingly attracting people's attention. Among them, large-screen terminals with relatively high screen-to-body ratio have gradually become one of the mainstream designs of mobile terminals. Large-screen terminals can improve the game entertainment experience of users, are conducive to split-screen display, and have higher technological sense, thereby bringing stronger visual impact to users.

[0004] At present, full-screen display has become a mainstream trend in mobile phone display. Full-screen compresses the design space of devices such as cameras, infrared sensors and receivers, and places devices such as cameras and infrared sensors under the display screen, which is a relatively promising display device design at present. SUMMARY

[0005] The embodiments of the present disclosure provide a display substrate, a display panel and a display device, which can better realize high-frequency display.

[0006] The embodiments of the present disclosure provide a display substrate, which comprises a first display area, the first display area comprises a plurality of first sub-pixels and a light-transmitting region between the plurality of first sub-pixels, the first sub-pixel comprises a pixel circuit, and the pixel circuit comprises a plurality of signal lines; in the light-transmitting region of the first display area, the material of at least part of the signal lines adopts transparent wiring, and in the region outside the light-transmitting region of the first display area, the material of at least part of the signal lines adopts metal wiring.

[0007] The embodiments of the present disclosure also provide a display substrate, which comprises a first display area, the first display area comprises a plurality of pixel islands and a light-transmitting region between the plurality of pixel islands; the pixel island comprises a pixel circuit, and the pixel circuit comprises a plurality of signal lines; between the pixel islands, the material of at least part of the signal lines adopts metal wiring.

[0008] In some example embodiments, the plurality of signal lines comprises a scanning signal line, a data signal line, a first power supply line, an initial signal line and a light-emitting signal line, wherein:

[0009] The scanning signal line, the data signal line, the first power supply line and the initial signal line are all metal wiring.

[0010] In some example embodiments, the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate;

[0011] In the first display area, the first power line and the data signal line are on different conductive layers, and a projection of the first power line on the base overlaps with a projection of the data signal line on the base.

[0012] In some example embodiments, the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scan signal line comprises a first scan signal line and a second scan signal line, the first scan signal line and the second scan signal line are on different conductive layers;

[0013] The pixel circuit comprises a driving sub-circuit, a data writing sub-circuit and a first reset sub-circuit, the driving sub-circuit is configured to generate a driving current between a second node and a third node under the control of a first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line;

[0014] In the first display area, a projection of the first scan signal line on the base overlaps with a projection of the second scan signal line on the base.

[0015] In some example embodiments, in the first display area, the second scan signal line extends along a first direction, the second scan signal line comprises a plurality of spaced-apart bending portions, the bending portions extend along a second direction, the first direction intersects with the second direction.

[0016] In some example embodiments, in the first display area, a projection of the initial signal line on the base overlaps with a projection of the first scan signal line on the base and / or a projection of the second scan signal line on the base.

[0017] In some example embodiments, the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scan signal line comprises a first scan signal line and a second scan signal line, the first scan signal line and the second scan signal line are on different conductive layers;

[0018] The semiconductor layer comprises an active layer of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer comprises the second scan signal line, the first source-drain metal layer comprises the initial signal line and the first power supply line, and the second source-drain metal layer comprises the data signal line.

[0019] In some example embodiments, each of the pixel islands comprises at least one first sub-pixel, and the semiconductor layer in the first sub-pixel of each column is staggered with the semiconductor layer in the first sub-pixel of an adjacent column in a row direction.

[0020] In some example embodiments, in the first display area, the first scan signal line comprises a plurality of branches, the first transparent conductive layer comprises a fourteenth connection electrode and a fifteenth connection electrode, the first source-drain metal layer comprises a sixth connection electrode and a seventh connection electrode, and the first gate metal layer comprises a first connection electrode.

[0021] The sixth connection electrode and the seventh connection electrode are respectively electrically connected to both ends of the first connection electrode through vias, the fourteenth connection electrode is electrically connected to the seventh connection electrode through a via, and the fifteenth connection electrode is electrically connected to the sixth connection electrode through a via.

[0022] Each branch of the first scan signal line is respectively electrically connected to the fourteenth connection electrode and the fifteenth connection electrode in adjacent two first sub-pixels of the same row through vias.

[0023] In some example embodiments, in the first display area, the initial signal line comprises a plurality of branches, and the second gate metal layer comprises a third connection electrode.

[0024] Each branch of the initial signal line is respectively electrically connected to the third connection electrode in adjacent two first sub-pixels of the same row through vias.

[0025] In some example embodiments, in the first display area, the first power supply line comprises a plurality of branches, the display substrate further comprises an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer comprises a seventeenth connection electrode.

[0026] The seventeenth connection electrode is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode through vias, and each branch of the first power supply line is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode in adjacent two first sub-pixels of the same column through vias.

[0027] In some example embodiments, a plurality of metal layers are included between the pixel islands, and there is an overlapping area between at least two metal layers.

[0028] The display substrate provided by the embodiment of the present disclosure comprises a first display area, the first display area comprises a plurality of pixel units and a light-transmitting area between the plurality of pixel units; the pixel unit comprises a pixel circuit, the pixel circuit comprises a plurality of signal lines; and the material of at least part of the signal lines adopts metal wiring between the pixel units.

[0029] In some example embodiments, at least one of the plurality of pixel units comprises a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are arranged in a triangular shape.

[0030] The display panel provided by the embodiment of the present disclosure comprises the display substrate as described in any of the embodiments of the present disclosure.

[0031] The display device provided by the embodiment of the present disclosure comprises the display panel as described in any of the embodiments of the present disclosure and a light-sensing element, and the light-sensing element overlaps the first display area.

[0032] The display substrate, the display panel, and the display device provided by the embodiment of the present disclosure can better realize high-frequency display by adopting metal material for part of the signal lines of the first display area, and in addition, can effectively reduce the area occupied by the metal wiring of the first display area by overlapping the plurality of signal lines, increase the light transmittance of the first display area, and improve the photographing function of the front camera, such as selfie and face recognition. In addition, the preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0033] Other features and advantages of the present disclosure will be described in the following description, and some will become apparent from the description, or will be learned through implementation of the present disclosure. Other advantages of the present disclosure can be achieved and obtained through the solutions described in the specification and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0035] Figure 1 A structural schematic diagram of a display panel provided by the embodiment of the present disclosure is shown in FIG. 1;

[0036] Figure 2 A structural schematic diagram of a display panel provided by the embodiment of the present disclosure is shown in FIG. 1;

[0037] Figure 3 A structural schematic diagram of a display panel provided by the embodiment of the present disclosure is shown in FIG. 1;Figure 2 A schematic view of a pixel arrangement structure in the display panel shown;

[0038] Figure 4 An equivalent circuit diagram of a pixel circuit provided for an embodiment of the present disclosure;

[0039] Figure 5 An equivalent circuit diagram of a pixel circuit provided for an embodiment of the present disclosure; Figure 4 A working timing diagram of the pixel circuit shown;

[0040] Figure 6a A schematic view of a planar structure of a display substrate provided for an embodiment of the present disclosure;

[0041] Figure 6b A schematic view of a planar structure of a display substrate provided for an embodiment of the present disclosure; Figure 6a A sectional view along the position A-A in the display substrate shown;

[0042] Figure 7 A schematic view of a structure of a semiconductor layer of a display substrate provided for an embodiment of the present disclosure;

[0043] Figure 8 A schematic view of a structure of a first conductive layer of a display substrate provided for an embodiment of the present disclosure;

[0044] Figure 9 A schematic view of a structure of a second conductive layer of a display substrate provided for an embodiment of the present disclosure;

[0045] Figure 10 A schematic view of a structure of a fourth insulating layer of a display substrate provided for an embodiment of the present disclosure;

[0046] Figure 11 A schematic view of a structure of a third conductive layer of a display substrate provided for an embodiment of the present disclosure;

[0047] Figure 12 A schematic view of a structure of a fifth insulating layer of a display substrate provided for an embodiment of the present disclosure;

[0048] Figure 13 A schematic view of a structure of a fourth conductive layer of a display substrate provided for an embodiment of the present disclosure;

[0049] Figure 14 A schematic view of a structure of a first planar layer of a display substrate provided for an embodiment of the present disclosure;

[0050] Figure 15 A schematic view of a structure of a fifth conductive layer of a display substrate provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] For the purpose of making the objects, technical solutions, and advantages of the present disclosure clearer, the following will be used in conjunction with the accompanying drawings to describe embodiments of the present disclosure in detail. Note that the embodiments can be implemented in a variety of different forms. Those of ordinary skill in the art can easily understand that the specific manner and content can be varied without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

[0052] In the drawings, the size, the thickness, or the region of each constituent element shown in some cases is exaggerated for the purpose of explanation and is not necessarily to scale. Thus, one embodiment of the present disclosure is not necessarily limited to the size shown in the drawings, and the shapes and the sizes of the components in the drawings do not reflect the actual ratio. In addition, the drawings are schematically shown ideal examples, and one embodiment of the present disclosure is not limited to the shapes or the numerical values shown in the drawings.

[0053] In the present specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among constituent elements and are not used to constitute a limitation as to the number thereof in the articles.

[0054] In the present specification, for the purpose of convenience in explanation, words indicating the orientation or the positional relation such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relation of the constituent elements with reference to the drawings, and are used only for the purpose of facilitating the description of the present specification and simplifying the description, and thus cannot be understood as indicating or implying that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relation of the constituent elements is changed as appropriate according to the direction in which each constituent element is described. Thus, the words described in the specification are not limited, and can be changed as appropriate according to the situation.

[0055] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connecting", and "linking" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection via an intermediate, or communication between two elements internally. Those of ordinary skill in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0056] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0057] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0058] In this specification, "electrically connected" includes the case where components are connected through an element having some function. There is no particular limitation on the element having some function as long as electric signals can be transmitted and received between components connected. Examples of the element having some function include an electrode and a wiring, a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0059] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0060] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0061] "About" in this disclosure means not strictly limited to a boundary, allowing a range of values within process and measurement errors.

[0062] Figure 1 A structure of a display panel is illustrated. As Figure 1As shown, the OLED display panel can include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, the pixel array can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In some exemplary embodiments, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signals in a manner of sequentially transferring the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the clock signal, m can be a natural number. The light emitting signal driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting signal driver can sequentially provide the emission signals having off-pulse to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signals in a manner of sequentially transferring the light emitting stop signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signal, o can be a natural number. The pixel array can include a plurality of sub-pixels Pxij, each of the sub-pixels Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, i and j can be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0063] Figure 2 A schematic view of a planar structure of a display panel according to an exemplary embodiment of the present disclosure is shown. As shown, the display panel can include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, the pixel array can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In some exemplary embodiments, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting signal driver to the light emitting signal driver. The data signal driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signals in a manner of sequentially transferring the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the clock signal, m can be a natural number. The light emitting signal driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting signal driver can sequentially provide the emission signals having off-pulse to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signals in a manner of sequentially transferring the light emitting stop signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signal, o can be a natural number. The pixel array can include a plurality of sub-pixels Pxij, each of the sub-pixels Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, i and j can be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line. Figure 2As shown, the display panel provided by the embodiment of the present application includes a first display area 100 and a second display area 200, the first display area 100 includes a plurality of first sub-pixels and a plurality of light-transmitting areas, the second display area 200 includes a plurality of second sub-pixels, the first sub-pixels and the first sub-pixels satisfy at least one of the following: the distribution density of the first sub-pixels is less than the distribution density of the second sub-pixels, and the area occupied by the first sub-pixels is less than the area occupied by the second sub-pixels. By reducing the distribution density of the first sub-pixels in the first display area 100 or reducing the area occupied by the first sub-pixels, the area of the light-transmitting area in the first display area 100 is increased, so that the imaging structure can be arranged in the light-transmitting area, so that the first display area 100 can be used for display to improve the screen ratio of the display area, and the first display area 100 can also be imaged through the light-transmitting area to meet the various needs of users.

[0064] In some example embodiments, the relative position relationship between the first display area 100 and the second display area 200 can be that at least part of the edge of the first display area 100 coincides with at least part of the edge of the second display area 200, and the remaining part of the first display area 100 is surrounded by the second display area 200, so that the first display area 100 can be arranged at the edge of the display area of the display panel. In other example embodiments, the relative position relationship between the second display area 200 and the first display area 100 can also be that the second display area 200 surrounds the first display area 100, so that the first display area 100 can be arranged inside the display area of the display panel, such as Figure 2 For example, the first display area 100 can be arranged at the upper left corner of the second display area 200. For example, the first display area 100 can be arranged at the upper right corner of the second display area 200. For example, the first display area 100 can be arranged at the left side of the second display area 200. For example, the first display area 100 can be arranged at the upper side of the second display area 200. Of course, in actual applications, the specific position of the first display area 100 can be designed and determined according to the actual application environment, which is not limited herein.

[0065] In actual implementation, the shape of the first display area 100 can be a regular shape, such as a rectangle, the top corner of the rectangle can be a right angle, or the top corner of the rectangle can also be an arc-shaped corner. For example, the shape of the first display area 20 can also be a trapezoid, which can be a right trapezoid or an inverted trapezoid. In addition, the top corner of the trapezoid can be a regular angle or an arc-shaped corner. For example, the shape of the first display area 100 can also be an irregular shape. For example, the shape of the first display area 100 can be a water drop shape. Of course, in actual applications, the shape of the first display area 100 can be designed according to the shape of the element arranged in the first display area 100, which is not limited herein.

[0066] In some exemplary embodiments, the area of ​​the first display area 100 is smaller than the area of ​​the second display area 200. Of course, in practical applications, the design can be based on the components disposed within the first display area 100, and no limitation is made here.

[0067] Figure 3 This is a schematic diagram of a pixel array arrangement structure as an exemplary embodiment of this disclosure. Figure 3 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first light-emitting unit P1 that emits a first color light, a second light-emitting unit P2 that emits a second color light, and a third light-emitting unit P3 that emits a third color light. Each of the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 includes a pixel driving circuit and a light-emitting element. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting element under the control of the scan signal line and the light-emitting signal line. The light-emitting elements in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of their respective light-emitting unit. The light-emitting elements are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective light-emitting unit.

[0068] In an exemplary embodiment, a pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or it may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit; this disclosure does not limit the scope of the invention. In an exemplary embodiment, the shape of the light-emitting units in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three light-emitting units, the three light-emitting units may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four light-emitting units, the four light-emitting units may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the scope of the invention.

[0069] In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 This is an equivalent circuit diagram of a pixel driving circuit as an exemplary embodiment of the present disclosure. Figure 4As shown, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and a plurality of signal lines (data signal line D, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light-emitting control signal line E).

[0070] In some example embodiments, the gate electrode of the first transistor T1 is connected with the second scan signal line S2, the first electrode of the first transistor T1 is connected with the initial signal line INIT, and the second electrode of the first transistor T1 is connected with the first node N1. The gate electrode of the second transistor T2 is connected with the first scan signal line S1, the first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the first node N1. The gate electrode of the third transistor T3 is connected with the first node N1, the first electrode of the third transistor T3 is connected with the second node N2, and the second electrode of the third transistor T3 is connected with the third node N3. The gate electrode of the fourth transistor T4 is connected with the first scan signal line S1, the first electrode of the fourth transistor T4 is connected with the data signal line D, and the second electrode of the fourth transistor T4 is connected with the second node N2. The gate electrode of the fifth transistor T5 is connected with the light-emitting control signal line E, the first electrode of the fifth transistor T5 is connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected with the second node N2. The gate electrode of the sixth transistor T6 is connected with the light-emitting control signal line E, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the fourth node N4 (i.e., the first electrode of the light-emitting element). The gate electrode of the seventh transistor T7 is connected with the first scan signal line S1 or the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected with the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected with the fourth node N4. The first end of the storage capacitor C is connected with the first power supply line VDD, and the second end of the storage capacitor C is connected with the first node N1.

[0071] In some example embodiments, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0072] In some exemplary embodiments, the second electrode of the light-emitting element is connected to the second power line VSS, the signal of the second power line VSS is a continuously low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row can be the same signal line to reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0073] In some exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT all extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0074] In some exemplary embodiments, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0075] Figure 5 for Figure 4 The diagram shows a timing sequence of a pixel driving circuit. The following is a breakdown of its operation. Figure 5 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 4 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C1, and 7 signal lines (data signal line DATA, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light emission signal line EM). All 7 transistors are P-type transistors.

[0076] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0077] In the first stage, A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the first node N1 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0078] The second stage A2, called data writing stage or threshold compensation stage, the signal of the first scan signal line S1 is low level signal, the signals of the second scan signal line S2 and the emitting signal line E are high level signals, and the data signal line D outputs data voltage. In this stage, the second end of the storage capacitor C is low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 is low level signal, so the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The turning on of the second transistor T2 and the fourth transistor T4 makes the data voltage outputted by the data signal line D be provided to the first node N1 through the second node N2, the turned on third transistor T3, the third node N3, the turned on second transistor T2, and the sum of the data voltage outputted by the data signal line D and the threshold voltage of the third transistor T3 be charged into the storage capacitor C, so that the voltage of the second end (the second node N2) of the storage capacitor C is Vdata+Vth, Vdata is the data voltage outputted by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The turning on of the seventh transistor T7 makes the initial voltage of the initial signal line INIT be provided to the first electrode of the OLED, so that the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode of the OLED is emptied, the initialization is completed, and it is ensured that the OLED does not emit light. The signal of the second scan signal line S2 is high level signal, so the first transistor T1 is disconnected. The signal of the emitting signal line E is high level signal, so the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0079] The third stage A3, called emitting stage, the signal of the emitting signal line E is low level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 are high level signals. The signal of the emitting signal line E is low level signal, so the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving voltage is provided to the first electrode of the OLED from the first power supply line VDD through the turned on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so that the OLED is driven to emit light.

[0080] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the third transistor T3. Since the voltage of the second node N2 is Vdata+Vth, the driving current of the third transistor T3 is:

[0081] I=K*(Vgs-Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdata–Vdd)] 2

[0082] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current of the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line D, and Vdd is the power voltage output by the first power supply line VDD.

[0083] As can be seen from the above formula, the current I flowing through the light emitting element is independent of the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I, and ensuring the uniformity of the brightness.

[0084] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light emitting element after the last light emission, realizes compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

[0085] In a conventional pixel circuit design, the signal lines between the pixel circuits in the first display area are connected by transparent indium tin oxide (ITO) or indium zinc oxide (IZO) traces. However, due to the relatively large resistance value of the transparent ITO or IZO traces, it is very unfavorable for high-frequency display applications.

[0086] Figure 6a A structure schematic diagram of a display substrate provided by an embodiment of the present disclosure in a first display area is provided, Figure 6b For Figure 6a A cross-sectional view along the A-A position. As Figure 6a And Figure 6b shown, in the first display area, a plurality of first sub-pixels include a pixel circuit (located in a non-light-transmitting area), the pixel circuit includes a plurality of signal lines, adjacent pixel circuits are connected to each other by the signal lines, and each signal line is used to provide different signals for the pixel circuit; in the light-transmitting region of the first display area, at least part of the signal lines adopt transparent traces; in the region outside the light-transmitting region of the first display area, at least part of the signal lines adopt metal traces.

[0087] In some example embodiments, the plurality of signal lines include a scan signal line, a data signal line D, a first power supply line VDD, an initial signal line INIT, and a light emitting signal line E. Wherein, the scan signal line is used to provide a scan signal for the pixel circuit, the data signal line D is used to provide a data signal for the pixel circuit, the first power supply line VDD is used to provide a first power supply signal for the pixel circuit, the initial signal line INIT is used to provide an initial signal for the pixel circuit, and the light emitting signal line E is used to provide a light emitting control signal for the pixel circuit.

[0088] In some example embodiments, the scan signal line, the data signal line D, the first power supply line VDD and the initial signal line INIT are metal tracks, and the light-emitting signal line E is a transparent track.

[0089] In some example embodiments, in a plane perpendicular to the display substrate, the display substrate comprises a substrate 90 and a plurality of conductive layers on the substrate 90, the scan signal line comprises a first scan signal line S1 and a second scan signal line S2, and the first scan signal line S1 and the second scan signal line S2 are located on different conductive layers.

[0090] In some example embodiments, the pixel circuit comprises a driving sub-circuit, a data writing sub-circuit and a first reset sub-circuit, the driving sub-circuit is configured to generate a driving current between the second node and the third node under the control of the first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line S1; and the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line S2.

[0091] In some example embodiments, the first scan signal line S1 and the second scan signal line S2 are metal tracks.

[0092] Since the load of the signal tracks such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD and the initial signal line INIT has a greater impact on high frequency, the display substrate of the present disclosure replaces the ITO tracks of the signal tracks such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD and the initial signal line INIT with conventional metal tracks, thereby reducing the resistance of the signal tracks, which is conducive to better high-frequency display of the first display area; in addition, since the light-emitting signal line E has a smaller impact on high-frequency display, no change is made and transparent conductive tracks such as indium tin oxide ITO or indium zinc oxide IZO are still used.

[0093] In some example embodiments, as shown in FIG. 1, in a plane perpendicular to the display substrate, the display substrate comprises a substrate and a plurality of conductive layers on the substrate, and the scan signal line comprises a first scan signal line S1 and a second scan signal line S2. Figures 7 to 15

[0094] The semiconductor layer comprises an active layer of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer comprises the second scan signal line S2, the first source-drain metal layer comprises the initial signal line INIT and the first power supply line VDD, the first transparent conductive layer comprises the light-emitting signal line E, and the second source-drain metal layer comprises the first scan signal line S1 and the data signal line D.

[0095] ​In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X. Figure 7

[0096] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X. Figure 6a

[0097] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X. Figure 8

[0098] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X. Figures 7 to 15

[0099] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X.

[0100] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X.

[0101] In some example embodiments, as shown in FIG. 1, the first display area includes a plurality of columns of first sub-pixels, and the semiconductor layers in each column of first sub-pixels are staggered with the semiconductor layers in the first sub-pixels of an adjacent column in the first direction X. Figures 7 to 15

[0102] ​​​​​In some example embodiments, in the first display area, the initial signal line INIT includes a plurality of branches, the second gate metal layer includes the third connection electrode 21; each branch of the initial signal line INIT is electrically connected to the third connection electrode 21 in the adjacent two first sub-pixels of the same row through a via.

[0103] In some example embodiments, as shown in FIG. 1A, in the first display area, the first power line VDD includes a plurality of branches, the first transparent conductive layer includes the eleventh connection electrode 41 and the twelfth connection electrode 42, and the second source-drain metal layer includes the seventeenth connection electrode 51. Figure 6a As shown in FIG. 1A, in the first display area, the first power line VDD and the data signal line D overlap on the substrate. In this embodiment, by overlapping the first power line VDD and the data signal line D, the influence of metal wiring on the transmittance can be minimized.

[0104] In some example embodiments, as shown in FIG. 1A, in the first display area, the first power line VDD includes a plurality of branches, the first transparent conductive layer includes the eleventh connection electrode 41 and the twelfth connection electrode 42, and the second source-drain metal layer includes the seventeenth connection electrode 51. Figures 11 to 15

[0105] The seventeenth connection electrode 51 is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 through a via, and each branch of the first power line VDD is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 in the adjacent two first sub-pixels of the same column through a via.

[0106] The structure of the display substrate of the embodiments of the present disclosure will be described below by way of example through the preparation process of the display substrate. The "patterning process" in the present disclosure includes processes such as deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist. The deposition can be performed by any one or more selected from sputtering, evaporation, and chemical vapor deposition, the coating can be performed by any one or more selected from spraying and spin coating, and the etching can be performed by any one or more selected from dry etching and wet etching. The "thin film" refers to a thin film of a certain material formed on a substrate by deposition or coating process. If the "thin film" does not need to be subjected to the patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still needs to be subjected to the patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "the orthogonal projection of A contains the orthogonal projection of B" means that the orthogonal projection of B falls within the range of the orthogonal projection of A, or the orthogonal projection of A covers the orthogonal projection of B.

[0107] In some example embodiments, as shown in FIG. 1A, in the first display area, the first power line VDD includes a plurality of branches, the first transparent conductive layer includes the eleventh connection electrode 41 and the twelfth connection electrode 42, and the second source-drain metal layer includes the seventeenth connection electrode 51. Figure 6a and Figure 6b The preparation process of the display substrate shown in FIG. 1A can include the following steps: ​

[0108] (1) Form a semiconductor layer pattern on the substrate 90. Forming a semiconductor layer pattern on the substrate 90 includes: first depositing an insulating thin film on the substrate 90 to form a first insulating layer 91 pattern covering the entire substrate 90. Subsequently, deposit an active layer thin film, and pattern the active layer thin film through a patterning process to form a semiconductor layer pattern disposed on the first insulating layer 91, as Figure 7 shown. Among them, the semiconductor layer pattern in the first display area may include the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, the active layer 40 of the fourth transistor T4, the active layer 50 of the fifth transistor T5, the active layer 60 of the sixth transistor T6, and the active layer 70 of the seventh transistor T7. In some exemplary embodiments, the first active layer 10, the second active layer 20, the third active layer 30, the fourth active layer 40, the fifth active layer 50, the sixth active layer 60, and the seventh active layer 70 may be an integrally connected structure.

[0109] In some exemplary embodiments, the shape of the first active layer 10 may be in the shape of a door frame, and the shape of the second active layer 20 may be in the shape of a certain shape, the shape of the third active layer 30 may be in the shape of a "ji" character, the shape of the fourth active layer 40 may be in the shape of a "1" character, the shapes of the fifth active layer 50 and the sixth active layer 60 may be in the shape of an "L" character, and the shape of the seventh active layer 70 may be in the shape of a dumbbell.

[0110] In some example embodiments, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In some example embodiments, the second region 102 of the first active layer 10 simultaneously serves as the second region 202 of the second active layer 20, i.e., the second region 102 of the first active layer 10 and the second region 202 of the second active layer 20 are connected to each other. The first region 301 of the third active layer 30 simultaneously serves as the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50, i.e., the first region 301 of the third active layer 30, the second region 402 of the fourth active layer 40, and the second region 502 of the fifth active layer 50 are connected to each other. The second region 302 of the third active layer 30 simultaneously serves as the first region 601 of the sixth active layer 60 and the first region 201 of the second active layer 20, i.e., the second region 302 of the third active layer 30, the first region 601 of the sixth active layer 60, and the first region 201 of the second active layer 20 are connected to each other. The first region 101 of the first active layer 10 simultaneously serves as the first region 701 of the seventh active layer 70, i.e., the first region 101 of the first active layer 10 and the first region 701 of the seventh active layer 70 are connected to each other. The first region 401 of the fourth active layer 40, the first region 501 of the fifth active layer 50, the second region 602 of the sixth active layer 60, and the second region 702 of the seventh active layer 70 are separately provided.

[0111] In some example embodiments, in the first display area 100, the plurality of first sub-pixels includes two or more columns, and the semiconductor layers of the first sub-pixels of each column are staggered with the semiconductor layers of the first sub-pixels of adjacent columns in the first direction. By staggering the semiconductor layers of the first sub-pixels of adjacent columns in the first direction, the margin of the semiconductor layers of the first sub-pixels of adjacent columns in the first direction is increased, so that the light transmission area on both sides of the first sub-pixel for imaging is larger.

[0112] In some example embodiments, the semiconductor layer can be polycrystalline silicon (p-Si), i.e., the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor can all be LTPS thin film transistors.

[0113] After this process, the display substrate includes the first insulating layer 91 disposed on the base 90 and the semiconductor layer disposed on the first insulating layer 91, and the semiconductor layer can include the active layers of the plurality of transistors.

[0114] (2) forming a first conductive layer pattern. In some example embodiments, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first metal thin film on the substrate 90 on which the aforementioned pattern is formed, patterning the first metal thin film by a patterning process, forming a second insulating layer 92 covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer 92, the first conductive layer pattern of the first display area at least including: a second scan signal line S2, a first connecting electrode 11, a second connecting electrode 12, and a first plate Ce1 of a storage capacitor, as shown in FIG. 2. In some example embodiments, the first conductive layer can be referred to as a first gate metal (GATE1) layer. Figure 8

[0115] In the embodiments of the present disclosure, by adopting a metal trace for the second scan signal line S2 of the first display area, the influence of trace load on high-frequency display can be reduced, so that the first display area can better realize high-frequency display.

[0116] In some example embodiments, within each sub-pixel, the second scan signal line S2 is located on the side of the first connecting electrode 11 away from the first plate Ce1 of the storage capacitor, and the first plate Ce1 of the storage capacitor is disposed between the first connecting electrode 11 and the second connecting electrode 12.

[0117] In some example embodiments, the area where the second scan signal line S2 overlaps with the first active layer of the first transistor T1 serves as a gate electrode of the double-gate structure of the first transistor T1.

[0118] In some example embodiments, in the first display area 100, the second scan signal line S2 is in a zigzag structure. Since in the first display area 100, the semiconductor layers of the first sub-pixels of each column are staggered with the semiconductor layers of the first sub-pixels of the adjacent column in the first direction, and the second scan signal line S2 overlaps with the first active layer of the first transistor T1 in a row of first sub-pixels, the second scan signal line S2 is in a zigzag structure.

[0119] ​In some example embodiments, the region where the first connection electrode 11 overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. The first connection electrode 11 is provided with a gate block 11-1 protruding toward the side of the second scan signal line S2, and the orthogonal projection of the gate block 11-1 on the base 90 overlaps with the orthogonal projection of the second active layer of the second transistor T2 on the base 90, and the region where the first connection electrode 11 and the gate block 11-1 overlap with the second active layer of the second transistor T2 serves as the gate electrode of the double-gate structure of the second transistor T2. The region where the first connection electrode 11 overlaps with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7. That is, the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the gate electrode of the seventh transistor T7 are connected to each other to form an integrated structure.

[0120] In some example embodiments, the region where the second connection electrode 12 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and the region where the second connection electrode 12 overlaps with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. That is, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 are connected to each other to form an integrated structure.

[0121] In some example embodiments, the first electrode plate Ce1 can be rectangular, and the corners of the rectangular shape can be chamfered, and the orthogonal projection of the first electrode plate Ce1 on the base 90 overlaps with the orthogonal projection of the third active layer of the third transistor T3 on the base 90. In some example embodiments, the first electrode plate Ce1 simultaneously serves as the gate electrode of the third transistor T3, and the region where the third active layer of the third transistor T3 overlaps with the first electrode plate Ce1 serves as the channel region of the third transistor T3, and one end of the channel region is connected to the first region of the third active layer, and the other end is connected to the second region of the third active layer.

[0122] In some example embodiments, after forming the first conductive layer pattern, the semiconductor layer can be conductorized by using the first conductive layer as a shield, and the semiconductor layer in the region shielded by the first conductive layer forms the channel region of each transistor, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of each active layer are conductorized.

[0123] After this process, the display substrate includes the first insulating layer 91 disposed on the base 90, the semiconductor layer disposed on the first insulating layer 91, the second insulating layer 92 covering the semiconductor layer, and the first conductive layer disposed on the second insulating layer 92, and the first conductive layer can include the second scan signal line S2, the first connection electrode 11, the second connection electrode 12, and the first electrode plate Ce1 of the storage capacitor.

[0124] (3) forming a second conductive layer pattern. In some example embodiments, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second metal thin film on the substrate 90 on which the aforementioned patterns are formed, patterning the second metal thin film by using a patterning process, forming a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93, the second conductive layer pattern of the first display area at least including: a second electrode plate Ce2 of a storage capacitor and a third connection electrode 21, as shown in FIG. 6. In some example embodiments, the second conductive layer can be referred to as a second gate metal (GATE2) layer. Figure 9

[0125] In some example embodiments, within each sub-pixel, the third connection electrode 21 is located on the side of the second scan signal line S2 away from the first connection electrode 11, and the third connection electrode 21 is used to connect an initial signal line INIT formed subsequently.

[0126] In some example embodiments, the second electrode plate Ce2 can have a rectangular shape with a notch H, and the corners of the rectangular shape can be chamfered, and the orthographic projection of the second electrode plate Ce2 on the substrate 90 and the orthographic projection of the first electrode plate Cel on the substrate 90 have an overlapping area. The notch H can be located at a corner of the second electrode plate Ce2. The notch H can be polygonal, and the notch H exposes the third insulating layer covering the first electrode plate Cel, and the orthographic projection of the first electrode plate Cel on the substrate 90 and the orthographic projection of the notch H on the substrate 90 overlap. In some example embodiments, the notch H is configured to accommodate a third via formed subsequently, the third via is located in the notch H and exposes the first electrode plate Cel, so that the second electrode of a second transistor T2 formed subsequently is connected to the first electrode plate Cel.

[0127] After this process, the display substrate includes: a first insulating layer 91 disposed on the substrate 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, a first conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the first conductive layer, and a second conductive layer disposed on the third insulating layer 93, the second conductive layer at least including: a second electrode plate Ce2 of a storage capacitor and a third connection electrode 21.

[0128] ​(4) Forming the fourth insulating layer 94 pattern. Forming the fourth insulating layer 94 pattern includes: on the substrate 90 of the above-mentioned structure, depositing a fourth insulating thin film, patterning the fourth insulating thin film by a patterning process, forming the fourth insulating layer 94 pattern with a plurality of vias, the plurality of vias including: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, and a fourteenth via V14, as shown in Figure 10

[0129] In an exemplary embodiment, the fourth insulating layer in the first via V1 is etched away, exposing the surface of the second plate Ce2 of the storage capacitor, configured to make the second branch VDD-B2 of the first power line VDD formed subsequently pass through the via and be electrically connected with the second plate Ce2 of the storage capacitor.

[0130] In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via V2 are etched away, exposing the surface of the first region 501 of the fifth active layer, configured to make the second branch VDD-B2 of the first power line VDD formed subsequently pass through the via and be connected with the first region 501 of the fifth active layer.

[0131] In an exemplary embodiment, the fourth insulating layer and the third insulating layer in the third via V3 are etched away, exposing the surface of the first plate Ce1 of the storage capacitor, configured to make the fourth connection electrode 31 formed subsequently pass through the via and be electrically connected with the first plate Ce1 of the storage capacitor.

[0132] In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing the surface of the second region 102 of the first active layer (also the second region 202 of the second active layer), configured to make the second electrode of the first transistor T1 formed subsequently pass through the via and be connected with the first active layer, and make the second electrode of the second transistor T2 formed subsequently pass through the via and be connected with the second active layer.

[0133] In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via V5 are etched away, exposing the surface of the second region 702 of the seventh active layer, configured to make the fifth connection electrode 32 formed subsequently pass through the via and be electrically connected with the second region 702 of the seventh active layer.

[0134] ​In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region 602 of the sixth active layer, configured to enable the fifth connecting electrode 32 formed subsequently to be electrically connected to the second region 602 of the sixth active layer through the via.

[0135] In an exemplary embodiment, the fourth insulating layer within the seventh via V7 is etched away, exposing the surface of one end of the third connecting electrode 21, configured to enable the first branch INIT-B1 of the initial signal line INIT formed subsequently to be electrically connected to one end of the third connecting electrode 21 through the via.

[0136] In an exemplary embodiment, the fourth insulating layer within the eighth via V8 is etched away, exposing the surface of the other end of the third connecting electrode 21, configured to enable the second branch INIT-B2 of the initial signal line INIT formed subsequently to be electrically connected to the other end of the third connecting electrode 21 through the via.

[0137] In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away, exposing the surface of the first region 101 of the first active layer (also the first region 701 of the seventh active layer), configured to enable the initial signal line formed subsequently to be electrically connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the via.

[0138] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the tenth via V10 are etched away, exposing the surface of one end of the first connecting electrode 11, configured to enable the sixth connecting electrode 33 formed subsequently to be electrically connected to one end of the first connecting electrode 11 through the via.

[0139] In an exemplary embodiment, the fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the other end of the first connecting electrode 11, configured to enable the seventh connecting electrode 34 formed subsequently to be electrically connected to the other end of the first connecting electrode 11 through the via.

[0140] In an exemplary embodiment, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the first region 401 of the fourth active layer, configured to enable the eighth connecting electrode 35 formed subsequently to be electrically connected to the first region 401 of the fourth active layer through the via.

[0141] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away, exposing the surface of one end of the second connecting electrode 12, configured to enable the ninth connecting electrode 36 formed subsequently to be electrically connected to one end of the second connecting electrode 12 through the via.

[0142] In an example embodiment, the fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away, exposing the surface of the other end of the second connection electrode 12, configured to enable the tenth connection electrode 37 formed subsequently to be electrically connected to the other end of the second connection electrode 12 through the via.

[0143] (5) Forming a third conductive layer pattern. In some example embodiments, forming the third conductive layer can include: on the substrate 90 on which the aforementioned patterns are formed, depositing a third metal thin film, and patterning the third metal thin film using a patterning process to form a third conductive layer disposed on the fourth insulating layer 94. As shown in FIG. 5, the third conductive layer of the first display area can include a first branch VDD-B1 of the first power line VDD, a second branch VDD-B2 of the first power line VDD, a first branch INIT-B1 of the initial signal line INIT, a second branch INIT-B2 of the initial signal line INIT, a fourth connection electrode 31, a fifth connection electrode 32, a sixth connection electrode 33, a seventh connection electrode 34, an eighth connection electrode 35, a ninth connection electrode 36, and a tenth connection electrode 37. In some example embodiments, the third conductive layer can be referred to as a first source-drain metal (SD1) layer. Figure 11

[0144] In the embodiments of the present disclosure, by using metal wiring for the first power line VDD and the initial signal line INIT of the first display area, the influence of wiring load on high-frequency display can be reduced, thereby enabling the first display area to better implement high-frequency display.

[0145] In some example embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD through a plurality of vias (here, the plurality of vias include: a fifteenth via V15, a sixteenth via V16, a twenty-sixth via, and a twenty-seventh via V27) and a plurality of connection electrodes (here, the plurality of connection electrodes include: an eleventh connection electrode 41, a twelfth connection electrode 42, and a seventeenth connection electrode 51) formed subsequently.

[0146] In some example embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the second plate Ce2 of the storage capacitor through the first via V1, and is connected to the first area 501 of the fifth active layer through the second via V2, so that the first electrode of the fifth transistor T5 has the same potential as the first power line VDD.

[0147] ​In some example embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD within the current sub-pixel through the subsequently formed multiple vias and multiple connection electrodes, and extends to the previous sub-pixel in the column where the current sub-pixel is located as the second branch VDD-B2 of the first power line VDD in the previous sub-pixel in the column.

[0148] In some example embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the first branch VDD-B1 of the first power line VDD within the current sub-pixel through the subsequently formed multiple vias and multiple connection electrodes, and extends to the next sub-pixel in the column where the current sub-pixel is located as the first branch VDD-B1 of the first power line VDD in the next sub-pixel in the column.

[0149] In some example embodiments, the first branch INIT-B1 of the initial signal line INIT is connected to one end of the third connection electrode 21 through the seventh via V7, and the second branch INIT-B2 of the initial signal line INIT is connected to the other end of the third connection electrode 21 through the eighth via V8. In this embodiment, the electrical connection between the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT is achieved through the third connection electrode 21, the seventh via V7 and the eighth via V8.

[0150] In some example embodiments, the second branch INIT-B2 of the initial signal line INIT is connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the ninth via V9, so that the first electrode of the first transistor T1 (also the first electrode of the seventh transistor T7) has the same potential as the first initial signal line INIT1.

[0151] In some example embodiments, the first branch INIT-B1 of the initial signal line INIT is electrically connected to the second branch INIT-B2 of the initial signal line INIT within the current sub-pixel through the third connection electrode 21, and extends to the previous sub-pixel in the row where the current sub-pixel is located as the second branch INIT-B2 of the initial signal line INIT in the previous sub-pixel in the row.

[0152] In some example embodiments, the second branch INIT-B2 of the initial signal line INIT is electrically connected to the first branch INIT-B1 of the initial signal line INIT within the current sub-pixel through the third connection electrode 21, and extends to the next sub-pixel in the row where the current sub-pixel is located as the first branch INIT-B1 of the initial signal line INIT in the next sub-pixel in the row.

[0153] In some example embodiments, the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT have overlapping regions with the orthogonal projection of the second scan signal line S2 on the substrate.

[0154] In some example embodiments, the fourth connection electrode 31 is electrically connected with the first plate Ce1 of the storage capacitor through the third via V3, and is connected with the second region 102 of the first active layer (also the second region 202 of the second active layer) through the fourth via V4. In some example embodiments, the fourth connection electrode 31 can serve as the second electrode of the first transistor T1 and the second electrode of the second transistor T2.

[0155] In some example embodiments, the fifth connection electrode 32 is electrically connected with the second region 702 of the seventh active layer through the fifth via V5, and is connected with the second region 602 of the sixth active layer through the sixth via V6. In some example embodiments, the fifth connection electrode 32 can serve as the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6.

[0156] In some example embodiments, the sixth connection electrode 33 is electrically connected with one end of the first connection electrode 11 through the tenth via V10.

[0157] In some example embodiments, the seventh connection electrode 34 is electrically connected with the other end of the first connection electrode 11 through the eleventh via V11.

[0158] In some example embodiments, the eighth connection electrode 35 is electrically connected with the first region 401 of the fourth active layer through the twelfth via V12. In some example embodiments, the eighth connection electrode 35 can serve as the first electrode of the fourth transistor T4.

[0159] In some example embodiments, the ninth connection electrode 36 is electrically connected with one end of the second connection electrode 12 through the thirteenth via V13.

[0160] In some example embodiments, the tenth connection electrode 37 is electrically connected with the other end of the second connection electrode 12 through the fourteenth via V14.

[0161] (6) Forming the fifth insulating layer 95 pattern. Forming the fifth insulating layer 95 pattern includes: coating a fifth insulating film on the substrate 90 formed with the aforementioned patterns, forming the fifth insulating layer 95 pattern covering the third conductive layer by a photolithography process of exposure and development through a mask, and the fifth insulating layer 95 of the first display area is provided with a fifteenth via hole V15, a sixteenth via hole V16, a seventeenth via hole V17, an eighteenth via hole V18, a nineteenth via hole V19, a twentieth via hole V20, a twenty-first via hole V21, and a twenty-second via hole V22, as shown in Figure 12

[0162] In some example embodiments, the fifth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the second branch VDD-B2 of the first power supply line VDD, configured to make the eleventh connection electrode 41 formed subsequently through the via hole and the second branch VDD-B2 of the first power supply line VDD electrically connected.

[0163] In some example embodiments, the fifth insulating layer in the sixteenth via hole V16 is etched away to expose the surface of the first branch VDD-B1 of the first power supply line VDD, configured to make the twelfth connection electrode 42 formed subsequently through the via hole and the first branch VDD-B1 of the first power supply line VDD electrically connected.

[0164] In some example embodiments, the fifth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the ninth connection electrode 36, configured to make the first branch E-B1 of the light-emitting signal line E formed subsequently through the via hole and the ninth connection electrode 36 electrically connected.

[0165] In some example embodiments, the fifth insulating layer in the eighteenth via hole V18 is etched away to expose the surface of the tenth connection electrode 37, configured to make the second branch E-B2 of the light-emitting signal line E formed subsequently through the via hole and the tenth connection electrode 37 electrically connected.

[0166] In some example embodiments, the fifth insulating layer in the nineteenth via hole V19 is etched away to expose the surface of the fifth connection electrode 32, configured to make the thirteenth connection electrode 43 formed subsequently through the via hole and the fifth connection electrode 32 electrically connected.

[0167] In some example embodiments, the fifth insulating layer in the twentieth via hole V20 is etched away to expose the surface of the seventh connection electrode 34, configured to make the fourteenth connection electrode 44 formed subsequently through the via hole and the seventh connection electrode 34 electrically connected.

[0168] ​In some example embodiments, the fifth insulating layer within the twenty-first via V21 is etched away to expose a surface of the sixth connection electrode 33, configured to enable the fifteenth connection electrode 45 formed subsequently to be electrically connected with the sixth connection electrode 33 through the via.

[0169] In some example embodiments, the fifth insulating layer within the twenty-second via V22 is etched away to expose a surface of the eighth connection electrode 35, configured to enable the sixteenth connection electrode 46 formed subsequently to be electrically connected with the eighth connection electrode 35 through the via.

[0170] (7) Forming a fourth conductive layer pattern. In some example embodiments, forming the fourth conductive layer can include: on the substrate 90 on which the aforementioned patterns are formed, depositing a first transparent conductive thin film, and patterning the first transparent conductive thin film to form the fourth conductive layer disposed on the fifth insulating layer 95. As shown in FIG. 7, the fourth conductive layer of the first display area can include a first branch E-B1 of the light-emitting signal line E, a second branch E-B2 of the light-emitting signal line E, the eleventh connection electrode 41, the twelfth connection electrode 42, the thirteenth connection electrode 43, the fourteenth connection electrode 44, the fifteenth connection electrode 45, and the sixteenth connection electrode 46. In some example embodiments, the fourth conductive layer can be referred to as a first transparent conductive layer. Figure 13

[0171] In the embodiments of the present disclosure, by using a transparent conductive material for the light-emitting signal line E of the first display area, the light transmittance of the camera area is increased, and the imaging effect is improved. At the same time, since the signal load of the light-emitting signal line E has less influence on high-frequency display, the use of the transparent conductive material for the light-emitting signal line E does not affect the effect of high-frequency display.

[0172] In some example embodiments, the first branch E-B1 of the light-emitting signal line E is electrically connected with one end of the second connection electrode 12 in the current sub-pixel through the seventeenth via V17, and extends to the previous sub-pixel in the row where the current sub-pixel is located, and is electrically connected with the other end of the second connection electrode 12 in the previous sub-pixel in the row where the current sub-pixel is located through the eighteenth via V18 in the previous sub-pixel in the row where the current sub-pixel is located.

[0173] In some example embodiments, the second branch E-B2 of the light-emitting signal line E is electrically connected with the other end of the second connection electrode 12 in the current sub-pixel through the eighteenth via V18, and extends to the next sub-pixel in the row where the current sub-pixel is located, and is electrically connected with one end of the second connection electrode 12 in the next sub-pixel in the row where the current sub-pixel is located through the seventeenth via V17 in the next sub-pixel in the row where the current sub-pixel is located.

[0174] ​In this embodiment, the first branch E-B1 of the light-emitting signal line E is electrically connected with the second branch E-B2 of the light-emitting signal line E through the second connection electrode 12, the seventeenth via hole V17 and the eighteenth via hole V18.

[0175] In some example embodiments, the eleventh connection electrode 41 is electrically connected with the second branch VDD-B2 of the first power supply line VDD through the fifteenth via hole V15.

[0176] In some example embodiments, the twelfth connection electrode 42 is electrically connected with the first branch VDD-B1 of the first power supply line VDD through the sixteenth via hole V16.

[0177] In some example embodiments, the thirteenth connection electrode 43 is electrically connected with the fifth connection electrode 32 through the nineteenth via hole V19.

[0178] In some example embodiments, the fourteenth connection electrode 44 is electrically connected with the seventh connection electrode 34 through the twentieth via hole V20.

[0179] In some example embodiments, the fifteenth connection electrode 45 is electrically connected with the sixth connection electrode 33 through the twenty-first via hole V21.

[0180] In some example embodiments, the sixteenth connection electrode 46 is electrically connected with the eighth connection electrode 35 through the twenty-second via hole V22.

[0181] (8) Forming a first planar layer 96 pattern. Forming the first planar layer 96 pattern includes: depositing a first planar film on the substrate 90 on which the aforementioned patterns are formed, patterning the first planar film by using a patterning process, forming the first planar layer 96 disposed on the fourth conductive layer, the first planar layer 96 being provided with a twenty-third via hole V23, a twenty-fourth via hole V24, a twenty-fifth via hole V25, a twenty-sixth via hole V26, a twenty-seventh via hole V27 and a twenty-eighth via hole V28, the thirteenth via hole V13 exposing the fourth connection line L4, and the fourteenth via hole V14 exposing the seventh connection line L7, as shown in Figure 14

[0182] In some example embodiments, the first planar layer in the twenty-third via hole V23 is etched away, exposing the surface of the fourteenth connection electrode 44, which is configured to allow the first branch S1-B1 of the first scan signal line S1 formed subsequently to be electrically connected with the fourteenth connection electrode 44 through the via hole.

[0183] ​In some exemplary embodiments, the first planarization layer within the twenty-fourth via V24 is etched away to expose the surface of the fifteenth connecting electrode 45, configured to allow the second branch S1-B2 of the subsequently formed first scan signal line S1 to be electrically connected to the fifteenth connecting electrode 45 through the via.

[0184] In some exemplary embodiments, the first planarization layer within the 25th via V25 is etched away to expose the surface of the 16th connection electrode 46, configured to allow a subsequently formed data signal line D to be electrically connected to the 16th connection electrode 46 through the via.

[0185] In some exemplary embodiments, the first planarization layer within the twenty-sixth via V26 is etched away to expose the surface of the twelfth connection electrode 42, configured to allow the subsequently formed seventeenth connection electrode 51 to be electrically connected to the twelfth connection electrode 42 through the via.

[0186] In some exemplary embodiments, the first planarization layer within the twenty-seventh via V27 is etched away to expose the surface of the eleventh connection electrode 41, configured to allow the subsequently formed seventeenth connection electrode 51 to be electrically connected to the eleventh connection electrode 41 through the via.

[0187] In some exemplary embodiments, the first planarization layer within the twenty-eighth via V28 is etched away to expose the surface of the thirteenth connection electrode 43, configured to allow the subsequently formed eighteenth connection electrode 52 to be electrically connected to the thirteenth connection electrode 43 through the via.

[0188] (9) Forming a fifth conductive layer pattern. Forming the fifth conductive layer may include: depositing a fifth metal thin film on the substrate 90 where the aforementioned pattern is formed, and patterning the fifth metal thin film using a patterning process to form a fifth conductive layer disposed on the first planarization layer. For example... Figure 15 As shown, the fifth conductive layer of the first display area may include a first branch S1-B1 of the first scan signal line S1, a second branch S1-B2 of the first scan signal line S1, a data signal line D, a seventeenth connecting electrode 51, and an eighteenth connecting electrode 52. In some exemplary embodiments, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0189] In this embodiment of the disclosure, by using metal traces for the first scan signal line S1 and the data signal line D of the first display area, the impact of trace load on high-frequency display can be reduced, thereby enabling the first display area to better achieve high-frequency display.

[0190] In some example embodiments, the first branch S1-B1 of the first scan signal line S1 is electrically connected to the fourteenth connection electrode 44 in the self sub-pixel through the twenty-third via V23, and extends to the next sub-pixel in the row where the self sub-pixel is located, and is electrically connected to the fifteenth connection electrode 45 in the next sub-pixel in the row where the self sub-pixel is located through the twenty-fourth via V24 in the next sub-pixel in the row where the self sub-pixel is located.

[0191] In some example embodiments, the second branch S1-B2 of the first scan signal line S1 is electrically connected to the fifteenth connection electrode 45 in the self sub-pixel through the twenty-fourth via V24, and extends to the next sub-pixel in the row where the self sub-pixel is located, and is electrically connected to the fourteenth connection electrode 44 in the next sub-pixel in the row where the self sub-pixel is located through the twenty-third via V23 in the next sub-pixel in the row where the self sub-pixel is located.

[0192] Since the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via V20, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via V21, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via V10, and the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via V11, the electrical connection between the first branch S1-B1 of the first scan signal line S1 and the second branch S1-B2 of the first scan signal line S1 is achieved.

[0193] In some example embodiments, the first branch S1-B1 of the first scan signal line S1 has an overlapping area with the first branch INIT-B1 of the initial signal line INIT in the orthographic projection on the substrate 90, and the second branch S1-B2 of the first scan signal line S1 has an overlapping area with the second branch INIT-B2 of the initial signal line INIT in the orthographic projection on the substrate 90.

[0194] In some example embodiments, the first branch S1-B1 of the first scan signal line S1 and the second branch S1-B2 of the first scan signal line S1 have an overlapping area with the second scan signal line S2 in the orthographic projection on the substrate 90.

[0195] In some example embodiments, the first branch S1-B1 of the first scan signal line S1, the first branch INIT-B1 of the initial signal line INIT, and the second scan signal line S2 have an overlapping area in the orthographic projection on the substrate 90, and the second branch S1-B2 of the first scan signal line S1, the second branch INIT-B2 of the initial signal line INIT, and the second scan signal line S2 have an overlapping area in the orthographic projection on the substrate 90.

[0196] In the embodiments of the present disclosure, by making the projections of the first scan signal line S1 and the second scan signal line S2 on the substrate 90 overlap, the influence of the metal wiring on the transmittance can be minimized, the light transmittance of the first display area is higher, and the shooting performance is better. By arranging the initial signal line INIT between the first scan signal line S1 and the second scan signal line S2, the signal crosstalk between the first scan signal line S1 and the second scan signal line S2 can be reduced, and the first display area can better realize high-frequency display, thereby greatly improving the display quality.

[0197] In some example embodiments, the data signal line D is electrically connected with the sixteenth connection electrode 46 through the twenty-fifth via hole V25. Since the sixteenth connection electrode 46 is electrically connected with the eighth connection electrode 35 through the twenty-second via hole V22, and the eighth connection electrode 35 is electrically connected with the first region 401 of the fourth active layer through the twelfth via hole V12, the electrical connection between the data signal line and the first electrode of the fourth transistor is realized, and the data signal transmitted by the data signal line D can be written into the fourth transistor.

[0198] In some example embodiments, the projections of the data signal line D, the first branch VDD-B1 of the first power supply line VDD, and the second branch VDD-B2 of the first power supply line VDD on the substrate 90 overlap.

[0199] In the embodiments of the present disclosure, by making the projections of the data signal line D and the first power supply line VDD on the substrate overlap, the influence of the metal wiring on the transmittance can be minimized, the light transmittance of the first display area is higher, and the shooting performance is better. In addition, the first power supply line VDD can shield the signal crosstalk generated by the metal wiring below the third conductive layer to the data signal line D, and the first display area can better realize high-frequency display, thereby greatly improving the display quality.

[0200] In some example embodiments, the seventeenth connection electrode 51 is electrically connected with the twelfth connection electrode 42 through the twenty-sixth via hole V26, and is electrically connected with the eleventh connection electrode 41 through the twenty-seventh via hole V27. Since the twelfth connection electrode 42 is electrically connected with the first branch VDD-B1 of the first power supply line VDD through the sixteenth via hole V16, and the eleventh connection electrode 41 is electrically connected with the second branch VDD-B2 of the first power supply line VDD through the fifteenth via hole V15, the electrical connection between the first branch VDD-B1 of the first power supply line VDD and the second branch VDD-B2 of the first power supply line VDD is realized.

[0201] In some example embodiments, the eighteenth connection electrode 52 is electrically connected with the thirteenth connection electrode 43 through the twenty-eighth via hole V28.

[0202] (10) Forming the second planarization layer 97 pattern. In some example embodiments, forming the second planarization layer 97 pattern can include: on the substrate 90 on which the aforementioned patterns are formed, coating a second planarization film, patterning the second planarization film by using a patterning process, forming the second planarization layer 97 covering the fifth conductive layer, and the second planarization layer 97 of the first display area being provided with at least a twenty-ninth via V29, as shown in Figure 6a .

[0203] In some example embodiments, the twenty-ninth via V29 is located in the area where the eighteenth connection electrode 52 is located, the second planarization layer in the twenty-ninth via V29 is removed to expose the surface of the eighteenth connection electrode 52, and the twenty-ninth via V29 is configured to enable the anode formed subsequently to be electrically connected to the eighteenth connection electrode 52 through the via.

[0204] (11) In some example embodiments, forming the anode pattern can include: on the substrate 90 on which the aforementioned patterns are formed, depositing a transparent conductive film, patterning the transparent conductive film by using a patterning process, and forming the anode disposed on the second planarization layer 97.

[0205] In some example embodiments, in the first display area, the anode is connected to the eighteenth connection electrode 52 through the twenty-ninth via V29. Since the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty-eighth via V28, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through the nineteenth via V19, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5 and to the second region 602 of the sixth active layer through the sixth via V6, the pixel circuit is thus enabled to drive the light-emitting element to emit light.

[0206] In some example embodiments, the subsequent preparation process can include: coating a pixel definition film, patterning the pixel definition film by using a patterning process to form a pixel definition layer (PDL), the pixel definition layer of each sub-pixel being provided with a sub-pixel opening (SA), and the sub-pixel opening exposing the anode. An organic light-emitting layer is formed by using an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, which can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0207] In some example embodiments, the substrate 90 can be a flexible substrate, or can be a rigid substrate. The rigid substrate can be one or more of, but not limited to, glass, quartz, and the flexible substrate can be one or more of, but not limited to, polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some example embodiments, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together, the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0208] In some example embodiments, the first, second, third, and fifth conductive layers can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The fourth conductive layer and the anode can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first insulating layer is referred to as a buffer (BUF) layer for improving the water and oxygen resistance of the substrate, the second insulating layer is referred to as a first gate insulating (GI1) layer, the third insulating layer is referred to as a second gate insulating (GI2) layer, the fourth insulating layer is referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer is referred to as a passivation (PVX) layer. The first and second planarization (PLN1 and PLN2) layers can be made of an organic material. The semiconductor layer can be made of polycrystalline silicon (p-Si) or an oxide.

[0209] The display substrate provided by the embodiment of the present disclosure reduces the resistance of the signal lines by replacing the ITO lines of the signal lines such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD and the initial signal line INIT with conventional metal lines, thereby facilitating the first display area to better perform high-frequency display. In addition, by overlapping the signal lines, the metal line occupation area of the first display area is effectively reduced, the light transmittance of the first display area is increased, and the photographing function such as selfie and face recognition of the front camera is improved. In addition, the preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.

[0210] The structure of the display substrate and the preparation process thereof shown in the present disclosure are only exemplary descriptions, and in some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs, which is not limited herein. The structure of the display substrate and the preparation process thereof shown in the present disclosure are only exemplary descriptions, and in some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs, which is not limited herein. Figure 3 The pixel circuit of the 8T1C shown is taken as an example for description, and in other exemplary embodiments, the pixel circuit can also be of a structure of 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C, which is not limited herein.

[0211] The present disclosure also provides a preparation method of a display substrate for preparing the display substrate provided in the above embodiments. The display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting region between the plurality of first sub-pixels, the first sub-pixel includes a pixel circuit, and the pixel circuit includes a plurality of signal lines. In some exemplary embodiments, the preparation method of the display substrate can include the following steps:

[0212] forming a semiconductor layer on the substrate;

[0213] forming a first gate metal layer on the semiconductor layer;

[0214] forming a second gate metal layer on the first gate metal layer;

[0215] forming a first source-drain metal layer on the second gate metal layer;

[0216] forming a first transparent conductive layer on the first source-drain metal layer;

[0217] forming a second source-drain metal layer on the first transparent conductive layer; in the light-transmitting region of the first display area, the first transparent conductive layer is used to run at least part of the signal lines; and in the region outside the light-transmitting region of the first display area, at least one layer of the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer is used to run at least part of the signal lines.

[0218] The display substrate prepared by the preparation method of the display substrate provided by the present disclosure has similar principles and effects to those of the aforementioned display substrate, and thus will not be described here.

[0219] The present disclosure also provides a display panel, which comprises the aforementioned display substrate, a polarizing plate arranged on the light-emitting side of the display substrate, a cover plate, and a support layer, a heat dissipation layer, etc. arranged on the back light side of the display substrate. The display panel can be used in any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigation devices, etc., and the embodiments of the present disclosure are not limited thereto.

[0220] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, and the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized by, The display substrate comprises a first display area, the first display area comprises a plurality of pixel units and a light-transmitting region between the plurality of pixel units; The pixel unit comprises a pixel circuit, the pixel circuit comprises a plurality of signal lines; In the light-transmitting region between the pixel units, materials of at least two signal lines are metal traces and pass through the light-transmitting region, and in the light-transmitting region, the at least two signal lines have an overlapping region in orthographic projection on the display substrate.

2. The display substrate of claim 1, wherein, The plurality of signal lines comprise a scan signal line, a data signal line, a first power supply line, an initial signal line and a light-emitting signal line, wherein: The scan signal line, the data signal line, the first power supply line and the initial signal line are metal traces. 3.The display substrate of claim 2, wherein, In a plane perpendicular to the display substrate, the display substrate comprises a base and a plurality of conductive layers on the base; In the first display area, the first power supply line and the data signal line are on different conductive layers, and the first power supply line has an overlapping region with the data signal line in orthographic projection on the base. 4.The display substrate of claim 2, wherein, In a plane perpendicular to the display substrate, the display substrate comprises a base and a plurality of conductive layers on the base; the scan signal line comprises a first scan signal line and a second scan signal line, the first scan signal line and the second scan signal line are on different conductive layers; The pixel circuit comprises a driving sub-circuit, a data writing sub-circuit and a first reset sub-circuit, the driving sub-circuit is configured to generate a driving current between a second node and a third node under the control of a first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line; In the first display area, the first scan signal line has an overlapping region with the second scan signal line in orthographic projection on the base.

5. The display substrate of claim 4, wherein, In the first display area, the second scan signal line extends along a first direction, the second scan signal line comprises spaced-apart bending portions, the bending portions extend along a second direction, and the first direction intersects the second direction. 6.The display substrate of claim 4, wherein, In the first display area, the initial signal line has an overlapping region with the first scan signal line and / or the second scan signal line in orthographic projection on the base. 7.The display substrate of claim 4, wherein, In a plane perpendicular to the display substrate, the display substrate comprises a base and a plurality of conductive layers on the base; the scan signal line comprises a first scan signal line and a second scan signal line, the first scan signal line and the second scan signal line are on different conductive layers; The semiconductor layer comprises an active layer of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer comprises the second scan signal line, the first source-drain metal layer comprises the initial signal line and the first power supply line, and the second source-drain metal layer comprises the data signal line. 8.The display substrate of claim 7, wherein, Each of the pixel units comprises at least one first sub-pixel, and the semiconductor layers in the first sub-pixels of each column are staggered with the semiconductor layers in the first sub-pixels of adjacent columns in a row direction. 9.The display substrate of claim 7, wherein, In the first display area, the initial signal line comprises a plurality of branches, and the second gate metal layer comprises a third connection electrode. Each branch of the initial signal line is electrically connected to the third connection electrodes in two adjacent first sub-pixels of the same row through a via. 10.The display substrate of claim 7, wherein, In the first display area, the first power supply line comprises a plurality of branches, and the display substrate further comprises an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer comprises a seventeenth connection electrode. The seventeenth connection electrode is electrically connected to the eleventh connection electrode and the twelfth connection electrode through a via, and each branch of the first power supply line is electrically connected to the eleventh connection electrode and the twelfth connection electrode in two adjacent first sub-pixels of the same column through a via. 11.The display substrate of claim 1, wherein, The pixel units comprise a plurality of metal layers, and there is an overlapping area between at least two metal layers. 12.The display substrate of claim 1, wherein, At least one of the pixel units comprises a first light-emitting unit emitting first color light, a second light-emitting unit emitting second color light, and a third light-emitting unit emitting third color light, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are arranged in a triangular shape.

13. A display panel, characterized by, Comprise: The display substrate according to any one of claims 1 to 12.

14. A display device comprising the display panel and the imaging structure according to claim 13, and the imaging structure overlaps the first display area.

Images