A heterojunction memristor with linear continuous conductance change and a preparation method thereof

Abstract

The present invention discloses a heterojunction memristor with linear continuous conductance change and a preparation method thereof. The memristor comprises a top electrode, an upper active layer, a lower active layer, a bottom electrode and a substrate from top to bottom, the upper active layer is composed of an organic polymer material poly (3-hexylthiophene-2,5-diyl), and the lower active layer is composed of a non-metallic elemental carbon 60. The preparation method comprises first growing a layer of bottom electrode on the surface of the substrate, then cleaning and drying, then performing ultraviolet ozone treatment, then evaporating the lower active layer carbon 60 in a vacuum evaporation system, spin coating the upper active layer of poly (3-hexylthiophene-2,5-diyl) on the lower active layer, and finally evaporating the top electrode in a vacuum evaporation system. The heterojunction structure memristor of the present invention has multi-resistance state characteristics under the stimulation of a retrace voltage and a pulse voltage, and can maintain a linear conductivity growth trend under a specific pulse voltage.

Description

Technical Field

[0001] The invention relates to an organic diode memristor device, in particular to a heterojunction memristor with linear continuous conductance change under a pulse voltage and a preparation method thereof. Background Art

[0002] In order to cope with the stagnation of computing chip performance caused by the failure of Moore's Law, researchers have been inspired by the neural network of the human brain. The human neural network performs calculations and memory simultaneously, bypassing the repeated storage and reading of data in the traditional von Neumann architecture, so it has faster operation speed, higher operation efficiency and lower energy consumption. Neuromorphic computing has also become a new research direction to break Moore's Law. A single neural synapse consists of a presynaptic membrane, a synaptic cleft and a postsynaptic membrane, corresponding to the top electrode, active layer and bottom electrode of a two-port memristor. In addition, when the memristor is stimulated by an external signal, the resistance value of the device changes. When the external stimulus signal disappears, the behavior stimulated by the external signal will be stored in the device. This behavior characteristic with historical operation dependence enables the memristor to imitate a variety of synaptic behaviors, such as double pulse inhibition / facilitation, short-term / long-term synaptic plasticity, etc. At the same time, complex learning and forgetting behaviors also put forward higher requirements on the resistance performance of the memristor. The learning behavior characteristics of the memristors reported so far under pulse signals are mostly characterized by few resistance states and insufficient linearity, which results in poor accuracy when simulating complex neural synaptic behaviors. Therefore, it is necessary to develop memristors with multiple resistance states and high linearity. Summary of the invention

[0003] The object of the present invention is to provide a heterojunction memristor with linear continuous conductance change and a preparation method thereof, so as to solve the problems of few resistance states and insufficient linearity of existing memristors.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] On the one hand, the present invention provides a heterojunction memristor with linear continuous conductance change, which includes, from top to bottom, a top electrode, an upper active layer, a lower active layer, a bottom electrode and a substrate, wherein the upper active layer is composed of an organic polymer material poly(3-hexylthiophene-2,5-diyl), and the lower active layer is composed of a non-metallic elemental carbon 60.

[0006] Furthermore, the thickness of the lower active layer is 10-15 nm.

[0007] Furthermore, the total thickness of the upper active layer and the lower active layer is 35-40 nm.

[0008] Furthermore, the top electrode is an aluminum electrode, and the thickness of the top electrode is 80-90 nm.

[0009] Furthermore, the bottom electrode is indium tin oxide (ITO), and the thickness of the bottom electrode is 130-140 nm.

[0010] Furthermore, the substrate is conductive glass.

[0011] On the other hand, the present invention provides a method for preparing a heterojunction memristor with linear continuous conductance change, comprising:

[0012] Step 1: growing a bottom electrode layer on the surface of the substrate, and then cleaning it with a glass cleaning agent, ultrapure water ultrasonic cleaning and drying;

[0013] Step 2, subjecting the sample dried in step 1 to ultraviolet ozone treatment;

[0014] Step 3: Place the sample processed in step 2 into the vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 After Pa, the carbon 60 active layer was deposited; after the deposition was completed, the vacuum state was maintained and cooled;

[0015] Step 4: Spin-coat the poly(3-hexylthiophene-2,5-diyl) solution on the sample treated in step 3, and anneal at 80° C. in air to obtain a poly(3-hexylthiophene-2,5-diyl) active layer;

[0016] Step 5: Place the sample processed in step 4 into the vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 After Pa, vacuum evaporation of the top electrode begins; after the evaporation is completed, the vacuum state is maintained and cooled to room temperature to obtain a finished product.

[0017] Furthermore, in the step 1, the material of the bottom electrode is indium tin oxide, and the thickness of the bottom electrode is controlled to be 130-140 nm, wherein the bottom electrode serves as the anode of the device.

[0018] Furthermore, in step 1, the ultrasonic cleaning time of the glass cleaning agent and ultrapure water is 25 to 30 minutes respectively.

[0019] Furthermore, in the step 2, the ultraviolet ozone treatment time is 15 minutes.

[0020] Furthermore, in step 3, the evaporation rate of vacuum evaporation carbon 60 is The thickness of the carbon 60 active layer is controlled at 10 to 15 nm.

[0021] Furthermore, in the step 4, a poly(3-hexylthiophene-2,5-diyl) solution dissolved in chloroform is spin coated at a speed of 3000 rpm for 30 seconds, and annealed in an air environment at 80° C. for 20 minutes, while controlling the total thickness of the poly(3-hexylthiophene-2,5-diyl) active layer and the carbon 60 active layer to be 35-40 nm.

[0022] Furthermore, in step 5, the material of the top electrode is aluminum, and the evaporation rate of the top electrode is The thickness of the top electrode is controlled to be 90-100 nm, and the top electrode serves as the cathode of the device.

[0023] Furthermore, the substrate is made of conductive glass.

[0024] Compared with the prior art, the beneficial technical effects achieved by the present invention are:

[0025] 1. The heterojunction memristor provided by the present invention has the excellent characteristics of uniform and slow increase of conductance and smooth and stable current output under the retrace voltage. When a positive voltage is applied to the ITO end, the conductance continues to increase; when a negative voltage is applied to the ITO end, the conductance continues to decrease. And under the positive pulse voltage, it shows an increase in multiple conductive states and conductive linearity; under the negative pulse voltage, it shows a decrease in multiple conductive states and conductive linearity;

[0026] 2. After being placed in air for 6 months, the synaptic performance of the heterojunction memristor provided by the present invention remains substantially unchanged, showing excellent air stability;

[0027] 3. The process adopted by the present invention is simple, easy to operate, and has a high yield. The linear conductance change and multi-conducting state characteristics provide a new and effective way for memristors to imitate neural synapses. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of a heterojunction memristor with linear continuous conductance change according to the present invention;

[0029] Figure 2 Poly(3-hexylthiophene-2,5-diyl) (P3HT) and non-metallic carbon 60 (C 60 )Molecular structure diagram;

[0030] Figure 3 The structural energy level diagram of the heterojunction memristor prepared in Example 1;

[0031] Figure 4 This is a current-voltage diagram of the heterojunction memristor prepared in Example 1 in air;

[0032] Figure 5 for Figure 4The device conductivity change diagram at 8V and -7V sampling points in the current-voltage diagram;

[0033] Figure 6 The current-voltage diagram of the heterojunction memristor prepared in Example 1 after being placed in the air for 6 months (April 16, 2022 to October 20, 2022);

[0034] Figure 7 This is a graph showing the linear conductance change of the heterojunction memristor prepared in Example 1 under continuous positive and negative pulse voltages;

[0035] Figure 8 The conductivity change and sampling point diagram of the heterojunction memristor prepared in Example 1 when subjected to in-situ Raman testing at a fixed voltage;

[0036] Fig. 9 for Figure 8 Raman spectrum changes under 7V continuous voltage;

[0037] Fig.10 for Figure 8 Raman spectrum changes under -7V continuous voltage;

[0038] Fig.11 This is a diagram showing the change in synaptic weight of the heterojunction memristor prepared in Example 1 at different pulse intervals during a 7V double pulse test;

[0039] Fig.12 This is a diagram showing the change in synaptic weight of the heterojunction memristor prepared in Example 1 at different pulse intervals during a -5V double pulse test;

[0040] Fig.13 A schematic diagram of simulation of enhancement and inhibition of synaptic function of the heterojunction memristor prepared in Example 1 at different pulse intervals;

[0041] Fig.14 Schematic diagram of the pulse number-dependent synaptic plasticity of the heterojunction memristor prepared in Example 1;

[0042] Fig.15 Schematic diagram of the heterojunction memristor prepared in Example 1 simulating synaptic "learning-forgetting-relearning";

[0043] Fig.16 A circuit diagram of a heterojunction memristor and a shunt resistor in parallel prepared in Example 1;

[0044] Fig.17 This is a graph showing the linear conductance change of the heterojunction memristor prepared in Example 1 after being connected in parallel with a shunt resistor under a pulse voltage;

[0045] Fig.18This is a graph showing linear conductance changes of the heterojunction memristor prepared in Example 1 when connected in parallel with a shunt resistor under wide pulse voltages at multiple sampling points;

[0046] Fig.19 Schematic diagram of the continuous "learning-forgetting" behavior of the heterojunction memristor prepared in Example 1 after being connected in parallel with a shunt resistor. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with specific examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention.

[0048] Most single materials have their performance limitations, and the emergence of heterostructure systems has enriched the functional layer selection of memristors. Poly(3-hexylthiophene-2,5-diyl) has a high HOMO, which is conducive to hole injection; carbon 60 has a low LUMO, which is conducive to electron injection. The poly(3-hexylthiophene-2,5-diyl) and carbon 60 system is an important system in organic photovoltaic solar cells. It not only has charge separation carrier behavior, but also has the advantages of low temperature processing, high flexibility and fast processing speed compared to inorganic materials. When poly(3-hexylthiophene-2,5-diyl) and carbon 60 are in contact, due to the π-π stacking effect, the thiophene ring of poly(3-hexylthiophene-2,5-diyl) will obviously tilt toward the carbon 60 direction, which promotes effective charge transfer between donors and acceptors.

[0049] Based on this, the present invention provides a heterojunction memristor with linear continuous conductance change, the structure of which is as follows: Figure 1 As shown, from top to bottom, it includes a top electrode, an upper active layer, a lower active layer, a bottom electrode and a substrate, wherein the upper active layer is composed of an organic polymer material poly(3-hexylthiophene-2,5-diyl), and the lower active layer is composed of a non-metallic elemental carbon 60. The thickness of the lower active layer is 10-15 nm, and the total thickness of the upper active layer and the lower active layer is 35-40 nm.

[0050] Example 1

[0051] (1) growing a layer of indium tin oxide bottom electrode with a thickness of 135 nm on the surface of a conductive glass substrate to form an ITO conductive glass, and then sequentially cleaning it with a glass cleaning agent and ultrapure water ultrasonic cleaning for 30 min each, then drying it with nitrogen gas, and placing it in a 120° C. oven for 60 min to dry it;

[0052] (2) treating the sample dried in step (1) with ultraviolet ozone for 15 min;

[0053] (3) Place the sample processed in step (2) into the vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 After Pa, the carbon 60 active layer was evaporated. The structural formula of carbon 60 is as follows Figure 2 (right) shows that the evaporation rate is The thickness was controlled at 13nm by using a crystal oscillator, and the film was taken out after cooling in a vacuum chamber for 30 minutes. The thickness of the film was measured by a step profiler, and the thickness of subsequent films was measured in the same way;

[0054] (4) Using a pipette, drop a poly(3-hexylthiophene-2,5-diyl) solution dissolved in chloroform onto the sample prepared in step (3), spin-coat at 3000 rpm for 30 seconds, and place in an oven for annealing at 80°C in air for 20 minutes to form a film. The structural formula of the poly(3-hexylthiophene-2,5-diyl) material is as follows: Figure 2 (Left) shows that the total thickness of the two active layers is 38nm at this time;

[0055] (5) Place the sample in step (4) into a vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 Pa later, vacuum evaporation of the top electrode began. The top electrode material was aluminum, and the evaporation rate was A crystal oscillator is used to control the thickness to 90 nm. After the evaporation is completed, the vacuum state is maintained until the top electrode is cooled to room temperature, and the heterojunction memristor is obtained. Then, the wafer is taken out and the electrical performance of the device is tested.

[0056] Test Example 1

[0057] The overall energy level of the device prepared in Example 1 is as follows Figure 3 As shown, poly (3-hexylthiophene-2,5-diyl) (P3HT) has a high HOMO and is easy to accept holes; non-metallic single carbon 60 (C 60 ) has a low LUMO and is easy to accept electrons.

[0058] Figure 4 This is a current-voltage curve in air of the heterojunction memristor prepared in Example 1. As can be seen from the figure, the device exhibits a stable unidirectional increase (decrease) characteristic of conductivity under a positive (negative) retrace voltage. Figure 5 for Figure 4 In the current-voltage curve, the current data at 8V and -7V for each retrace is converted into a conductivity curve. As the number of retrace cycles increases, the device conductivity shows a monotonous increase or decrease, and preliminarily shows the device's multi-conductivity state and linear conductivity change characteristics.

[0059] Figure 6 This is a current-voltage curve of the heterojunction memristor prepared in Example 1 under a continuous retrace voltage after being placed in an air environment for 6 months. Figure 6 and Figure 4By comparison, it can be found that after the device is placed in an air environment for 6 months, it still shows a unidirectional increase (decrease) in conductance. This characteristic is the basis for the memristor to simulate artificial synapses, and this characteristic still exists at the 50th cycle, proving that the device has good air stability.

[0060] Figure 7 The conductivity change curve of the heterojunction memristor device prepared in Example 1 under continuous positive and negative pulse voltages. Figure 7 As shown in the figure, a positive pulse voltage of 8V with an interval of 1.8s is applied to the bottom electrode of ITO. The conductivity of the device increases rapidly after the first few pulse stimulations. When the subsequent pulse stimulation exceeds 120, its conductivity shows a stable and smooth linear increase. Then, the pulse voltage is set to -7V with an interval of 1.8s. After the subsequent 170 pulse voltage stimulations, its conductivity shows a stable linear decrease. The device is regarded as an artificial synapse triggered by a pulse signal, 8V is the excitatory signal, -7V is the inhibitory signal, and the multi-resistance state under pulse stimulation ensures the overall accuracy of the artificial synaptic device, while the linearity of the conductivity change ensures the accuracy of the local voltage change.

[0061] like Figure 8 As shown, it is the real-time learning and forgetting curve of the heterojunction memristor device prepared in Example 1 when the in-situ Raman test is performed under a fixed voltage. The marked positions in the figure are the time nodes of Raman laser irradiation, corresponding to Fig. 9 and Fig.10 Raman spectrum, the laser wavelength of in-situ Raman test is 532nm. Fig. 9 The Raman spectrum at 1446 cm-1 is shown when a fixed voltage of 7 V is applied to the ITO end. -1 Strong Raman bands at 1446 cm -1 The weak Raman bands at 1446cm -1 The intensity of the strong Raman band at the ITO end shows a continuous weakening. Afterwards, a fixed voltage of -7V is applied to the ITO end. The Raman spectrum is shown in Fig.10 Under continuous -7V voltage stimulation, 1446cm -1 The Raman intensity of the strong Raman band shows a continuous enhancement.

[0062] Fig.11 This is a diagram showing the change in synaptic weight of the heterojunction memristor prepared in Example 1 at different pulse intervals during a 7V double pulse test. Fig.11 , with 7V pulse voltage as the enhanced stimulation signal, the amplitude of the paired pulse enhancement is negatively correlated with the pulse interval, that is, the shorter the pulse interval, the greater the amplitude of the synaptic weight increase. Through the fitting analysis of the data, when the pulse interval is less than 1s, its growth trend increases rapidly. Fig.12 , using -5V pulse voltage as the inhibitory stimulation signal, the fitting results show that the amplitude of paired pulse inhibition is also negatively correlated with the pulse interval, that is, the shorter the pulse interval, the greater the amplitude of the synaptic weight reduction.

[0063] The "learning-forgetting" rule of the heterojunction memristor device prepared in Example 1 under different pulse intervals was investigated. Applying a 7V excitatory stimulation signal to the memristor is defined as learning, and applying a 5V inhibitory stimulation signal to the memristor is defined as forgetting. The learning and forgetting process is shown in Fig.13 . Different pulse intervals were selected for comparative testing, namely 1 second, 2.3 seconds and 2.9 seconds. For excitatory stimulation signals, the shorter the pulse interval, the faster the rate of device conductance growth. When the inhibitory stimulation signal is a positive voltage, the rate of conductance decay is related to the conductance G1 before the inhibitory signal is applied. G1 is the device conductance when the last excitatory stimulation signal is applied. The larger G1 is, the faster the decay rate is. This signal decay law is similar to the forgetting law of the human brain.

[0064] The synaptic plasticity law of the heterojunction memristor device prepared in Example 1 was investigated in terms of the number of pulses. A 7V excitatory pulse signal with a pulse interval of 0.9s was applied to the memristor. The current level after the excitatory pulse stimulation was positively correlated with the number of pulses. The more excitatory pulses there were, the heavier the synaptic weight was. Then a fixed voltage with an amplitude of 5V was applied to the memristor, and the forgetting process of the device under the inhibitory voltage was recorded, as shown in FIG. Fig.14 As shown in the figure. Under a fixed forgetting voltage, the current flowing through the memristor drops rapidly in a short period of time, and then the downward trend gradually slows down. The more excitatory pulses applied to the memristor, the heavier the remaining synaptic weight after the same forgetting time, and the better the learning effect.

[0065] The "learning-forgetting-relearning" behavior of the heterojunction memristor device prepared in Example 1 under pulse stimulation was investigated. Fig.15 As shown, an excitatory stimulation signal with an amplitude of 7V is applied to the ITO end for 25s, followed by 25s of forgetting under a 1V inhibitory stimulation signal, and then a 7V excitatory stimulation signal is applied again. At this time, the device only needs 2s to catch up with or even exceed the current intensity reached by the previous 25s stimulation, indicating that the device has learning and non-volatile memory capabilities under a 7V learning signal and a 1V forgetting signal.

[0066] There is a huge difference in resistance between the high resistance state and the low resistance state of the memristor. Based on this characteristic, the method of parallel shunt resistor is used to improve the stability of the synaptic performance of the memristor. A fixed value resistor is connected in parallel to the memristor as a buffer, such as Fig.16As shown in the figure, when a voltage of 7V is applied, the resistance of the memristor is between 1KΩ and 10KΩ, and when a voltage of 1V is applied, the resistance is between 100MΩ and 1000MΩ. Therefore, 1MΩ is selected as the shunt resistor, so that when the memristor is in a high-resistance state, it can effectively shunt current, and when it is in a low-resistance state, it does not affect the synaptic performance of the memristor itself.

[0067] The "learning-forgetting" behavior of the heterojunction memristor device prepared in Example 1 under the protection of the shunt resistor was investigated. The purpose of adding the shunt resistor is mainly to reduce the damage of the pulse voltage change to the conductive path of the organic material, such as Fig.17 As shown. For the circuit characteristics after adding the shunt resistor, 7V voltage is used as the excitatory pulse voltage, 6V voltage is used as the inhibitory pulse voltage, and -5V is used as the forgetting voltage. During the entire learning and forgetting process, the memristor shows a smooth conductance change, and under 120 excitatory stimulation voltages, the memristor has a uniform and linear conductance growth, and the local accuracy of the memristor has been significantly improved. The excitatory pulse is converted into a 6V inhibitory pulse. In the first 20 inhibitory pulses, the device conductance decreases in a linear and uniform manner; when the device conductance decreases to a certain threshold, the conductance decrease rate slows down, and when the decline curve gradually turns horizontal, the artificial synapse is converted from short-term memory to long-term memory. Applying a -5V forgetting voltage to the device, it can be seen that the device conductance rapidly decreases to an extremely low level, completing the forgetting process.

[0068] The "learning" behavior of the heterojunction memristor device prepared in Example 1 under multiple sampling points was investigated. The stimulation intensity of the excitatory pulse voltage on the artificial synapse was further increased by increasing the pulse width to 2.7s. When the shunt resistor is not used, the device not only reaches the basic saturation state faster under wide pulse stimulation, but also exhibits the disadvantage of delayed postsynaptic current growth under high-level multiple sampling points, that is, under wide pulse stimulation, the current exhibits an increase-decrease-and-increase. After the memristor prepared in Example 1 was connected in parallel with a shunt resistor, a wide pulse excitatory pulse voltage test was performed again. The test results are as follows: Fig.18 As shown in the figure, the current of the memristor under pulse stimulation generally maintains a linear growth trend; under single pulse multi-sampling point scanning, the disadvantage of delayed postsynaptic current growth disappears, and the single pulse also shows the ideal performance of linear current growth.

[0069] The "learning-forgetting" behavior of the heterojunction memristor device prepared in Example 1 under cyclic pulse stimulation was investigated. Fig.19, 10 sets of repeated high-intensity learning and forgetting tests were conducted, with 10 -5V forgetting pulses and 10 7V learning pulses as a group. In the process of learning cycles, the linearity of positive learning gradually increased, and the uniformity of conductance growth increased. This repeated learning and forgetting training method shows the excellent characteristics of the device's transformation to linear learning and self-optimization. In the test, the conductance values ​​of the memristor are also close to each other under the stimulation of two pulse voltage cycles. This behavior is conducive to the memristor to imitate the neural synapse with higher behavioral similarity; it also shows that the learning behavior of the memristor is adjustable, and the memristor has a wider adaptability when imitating neural synapses.

[0070] In summary, the heterojunction memristor prepared in Example 1 has multi-resistance state characteristics under both the retrace voltage and pulse voltage stimulation, and can maintain a linear conductivity growth trend under a specific pulse voltage. In addition, the method of using shunt resistors further improves the linearity, uniformity and stability of the conductivity change under pulse voltage stimulation. The present invention provides a new solution to the problem that the learning behavior of artificial synapses under pulse signals is characterized by few resistance states and insufficient linearity, and provides the possibility for the hardware realization of high-precision artificial neural synapses.

[0071] The present invention has been disclosed above with preferred embodiments, but they are not intended to limit the present invention. Any technical solutions obtained by adopting equivalent replacement or equivalent transformation solutions fall within the protection scope of the present invention.

Claims

1. A heterojunction memristor with linear and continuous conductance change, It is characterized in that From top to bottom, it includes a top electrode, an upper active layer, a lower active layer, a bottom electrode and a substrate. The upper active layer is composed of an organic polymer material poly(3-hexylthiophene-2,5-diyl), and the lower active layer is composed of a non-metallic elemental carbon 60; the thickness of the lower active layer is 10 to 15 nm; the total thickness of the upper active layer and the lower active layer is 35 to 40 nm.

2. The heterojunction memristor with linear continuous conductance change according to claim 1, It is characterized in that The top electrode is an aluminum electrode, and the thickness of the top electrode is 80-90 nm.

3. The heterojunction memristor with linear continuous conductance change according to claim 1, It is characterized in that The bottom electrode is made of indium tin oxide, and the thickness of the bottom electrode is 130-140 nm.

4. A method for preparing a heterojunction memristor with linear continuous conductance change, It is characterized in that include: Step 1: growing a bottom electrode layer on the surface of the substrate, and then cleaning it with a glass cleaning agent, ultrapure water ultrasonic cleaning and drying; Step 2, subjecting the sample dried in step 1 to ultraviolet ozone treatment; Step 3: Place the sample processed in step 2 into the vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 After Pa, the carbon 60 active layer is evaporated, and the thickness of the carbon 60 active layer is controlled to be 10-15 nm; after the evaporation is completed, the vacuum state is maintained for cooling; Step 4: spin-coat a poly(3-hexylthiophene-2,5-diyl) solution on the sample treated in step 3, anneal at 80° C. in air, and control the total thickness of the poly(3-hexylthiophene-2,5-diyl) active layer and the carbon 60 active layer to be 35-40 nm, to obtain a poly(3-hexylthiophene-2,5-diyl) active layer; Step 5: Place the sample processed in step 4 into the vacuum evaporation system and evacuate the chamber until the pressure is less than 5×10 -4 After Pa, vacuum evaporation of the top electrode begins; after the evaporation is completed, the vacuum state is maintained and cooled to room temperature to obtain a finished product.

5. The method for preparing a heterojunction memristor with linear continuous conductance change according to claim 4, It is characterized in that The material of the bottom electrode is indium tin oxide, and the thickness of the bottom electrode is controlled to be 130-140 nm; the material of the top electrode is aluminum, and the top electrode evaporation rate is 1-3 Å / s, and the thickness of the top electrode is controlled to be 90-100 nm.

6. The method for preparing a heterojunction memristor with linear continuous conductance change according to claim 4, It is characterized in that In the step 1, the ultrasonic cleaning time of the glass cleaning agent and the ultrapure water is 25 to 30 minutes respectively.

7. The method for preparing a heterojunction memristor with linear continuous conductance change according to claim 4, It is characterized in that In the step three, the vacuum evaporation rate of carbon 60 is 0.05-0.1 Å / s.

8. The method for preparing a heterojunction memristor with linear continuous conductance change according to claim 4, It is characterized in that In the step 4, a poly(3-hexylthiophene-2,5-diyl) solution dissolved in chloroform is spin-coated at a speed of 3000 rpm for 30 seconds and annealed in an air environment at 80° C. for 20 minutes.

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