Method for communication between a first passive participant and a second passive participant of a bus system

Abstract

The present invention relates to a method for communication between passive participants (100, 200) of a bus system 1. A first passive participant (100) encodes an original static model (306) in a first transmit SERDES element (111) and transmits it as an encoded static model (307) to a second passive participant (200), and encodes original usage data (312) in a second transmit SERDES element (112) synchronously with the original static model (306) in terms of time and transmits it as encoded usage data (314) to the second passive participant (200). The second passive participant (200) receives the encoded static model (307) and the encoded usage data (314) and generates a sampling clock (302) with a first phase shift and a clock (303) synchronized with a transmit-receive clock (301) with a second phase shift from the encoded static model (307). The second passive participant (200) decodes the encoded static model (307) by means of a first receive SERDES element (211) and decodes the encoded usage data (314) by means of a second receive SERDES element (212) to obtain received data words. The first receive SERDES element (211) and the second receive SERDES element (212) operate according to the sampling clock (302) and the received data words are output synchronously with the synchronized clock (303).

Description

Technical Field

[0001] The present invention relates to a method for communication between a first passive participant and a second passive participant in a bus system. The present invention also relates to the passive participants and the bus system as a whole between which communication can be carried out.

[0002] This patent application claims the priority of German patent application DE 10 2020 125 391.5, the disclosure of which is incorporated herein by reference. Background Art

[0003] Bus systems are known from the prior art, in which data telegrams can be exchanged between participants. In such bus systems, decentralized devices, such as machine peripherals, such as I / O modules, measurement converters, drives, valves, and operator terminals, can communicate with an automation system, an engineering system, or a visualization system via a powerful real-time communication system. Here, all devices are interconnected via a serial bus, preferably a field bus, where data exchange via the bus is typically implemented based on the master-slave principle.

[0004] Here, the active participant at the bus system is the control device. The control device has bus access rights and determines data transmission on the bus. The active participant is also referred to as the master device in a serial bus system.

[0005] The passive participants are usually machine peripherals. The machine peripherals do not have bus access rights, which means that they are only allowed to answer received messages or transmit messages to the active participant according to the inquiry of the active participant. Therefore, the passive participants are also referred to as slave devices in a serial bus system.

[0006] The master device usually includes a field bus connection, which is a link between the central data processing device in the master device and the field bus network, and performs bus management. Therefore, the complete bus protocol is also implemented in the field bus connection, which is usually configured as a separate component. The slave device has an interface module, which converts the data from the slave device into the data format of the field bus system. Therefore, the interface module only needs a small part of the bus protocol.

[0007] An important aspect in constructing such a bus system is to enable communication between passive participants, so that, for example, a data telegram can be forwarded from a first passive participant to a second passive participant. This achieves a significant reduction in the wiring cost or connection cost in the bus system. Typically, the communication is carried out via differential twin lines, and the data telegram is transmitted via the differential twin lines. In such a bus system, the maximum transmission speed is limited to, for example, 100 Mbit. For example, the reference US 8,498,370 B2 discloses a communication method based on differential twin lines. Summary of the Invention

[0008] The object of the present invention is to increase the maximum transmission speed between passive participants and to provide a suitable method, suitable passive participants and a suitable bus system therefor.

[0009] The object is achieved by a method, a first passive participant, a second passive participant and a bus system for communication between a first passive participant and a second passive participant of a bus system according to the independent patent claims. Advantageous designs are specified in the dependent patent claims.

[0010] A method for communication between a first passive participant and a second passive participant of a bus system is designed such that a first differential pair of lines and a second differential pair of lines are used for communication. An original static model with a preset bit length is transmitted via the first differential pair of lines, wherein the original static model defines a transmit-receive clock. Original usage data is transmitted via the second differential pair of lines, wherein the original usage data includes a transmit data word with a preset bit length. The first passive participant encodes the original static model in a first transmit SERDES element and sends the encoded static model to the second passive participant via the first differential pair of lines. In addition, the first passive participant encodes the original usage data in a second transmit SERDES element in a time-synchronized manner with the original static model and sends the encoded usage data to the second passive participant via the second differential pair of lines. The second passive participant receives the encoded static model and the encoded usage data and generates a sampling clock and a clock synchronized with the transmit-receive clock from the encoded static model, wherein the sampling clock has a first phase shift relative to the transmit-receive clock and the synchronized clock has a second phase shift relative to the transmit-receive clock. The second passive participant decodes the encoded static model by means of a first receive SERDES element and decodes the encoded usage data by means of a second receive SERDES element to obtain a received data word. Here, the first receive SERDES element and the second receive SERDES element operate according to the sampling clock and output the received data word in a manner synchronized with the synchronized clock.

[0011] Here, the first differential pair and the second differential pair can be designed as printed conductors on a circuit board. In this case, the first passive participant and the second passive participant can also be arranged on the circuit board. The first differential pair and the second differential pair can also be guided via terminals and each include a twin cable such that the first passive participant and the second passive participant are arranged in different housings. Here, the transmitted data word can include a bit sequence having a preset bit length, which is transmitted by the first passive participant. The received data word can include a bit sequence having a preset bit length, which is received by the second passive participant. In order to obtain again the bit sequence of the received data word, it can be proposed to decode the received data word in a time-offset manner according to a static model.

[0012] Compared with a conventional system in which only one communication channel in the form of a differential pair is used for transmitting usage data, by providing the first differential pair for transmitting the original static model, an additional communication channel is thus provided via which a clock signal can be transmitted. Thereby, the method is also suitable for high transmission rates because by synchronously outputting the encoded static model and the transmitted data word by the first participant, the second passive participant is enabled to perform a synchronous correlation of the received data word and the encoded static model. It can be proposed that for this purpose, the lengths of the respective lines of the first differential pair and the second differential pair deviate from each other by at most a preset length, where the preset length results from the desired transmission rate and the signal propagation speed in the differential pair.

[0013] It can be proposed to transmit at least one gigabit per second, in particular 1.25 Gbit / s, via the first differential pair and at least one gigabit per second, in particular 1.25 Gbit / s, via the second differential pair. For this case, it can be proposed that if, for example, the first differential pair and the second differential pair are designed as printed conductors on a circuit board, the lengths of the respective lines of the first differential pair and the second differential pair deviate from each other by at most 3 cm.

[0014] In one embodiment of the method, the transmit receive clock corresponds to one tenth of the data rate transmitted via the first differential pair or via the second differential pair. Thereby, a favorable ratio of the preset bit length and the sampling clock is achieved.

[0015] In one embodiment of the method, the sampling clock corresponds to the data rate transmitted via the first differential pair or via the second differential pair or half of the data rate transmitted via the first differential pair or via the second differential pair. These two ratios achieve a favorable ratio of the data rate and the sampling clock.

[0016] In one embodiment of the method, the first phase shift is 90 degrees. Thereby, the received data word can be scanned in the data eye.

[0017] In one embodiment of the method, the second phase shift is 18 degrees. Thus, the received data word can also be scanned in the data eye.

[0018] In one embodiment of the method, the static model includes a first number of first bits having a bit value of 1 and a second number of second bits having a bit value of 0. The first bits are set first and then the second bits are set in the static model, wherein the first number and the second number together correspond to the bit length. Thus, a simple transmission of the static pattern can be performed. It can be proposed that the first number and the second number are the same and thus each correspond to half of the bit length.

[0019] In one embodiment of the method, the static model decoded by the first receiving SERDES element is shifted by means of a first shift register until the original static model is output at the output of the first receiving SERDES element. The received data word decoded by the second receiving SERDES element is shifted by means of a second shift register by the same number of displacements as the first shift register. This enables a coarse adjustment of the transmission.

[0020] In one embodiment of the method, the static model encoded in the second passive participant is delayed by a first delay element, and the encoded usage data is delayed by a second delay element. At initialization, the delays of the first delay element and the second delay element are first gradually reduced respectively, and it is checked whether the sampled clock model changes. Thus, the lower limit of the delay is determined. In particular, the lower limit is obtained when the clock model changes. Subsequently, the delays of the first delay element and the second delay element are gradually increased respectively, and it is checked whether the sampled clock model changes. Thus, the upper limit of the delay is determined. In particular, the upper limit is obtained when the clock model changes. Subsequently, the delays of the first delay element and the second delay element are set to the average value of the lower limit and the upper limit. Thus, it can be achieved that sampling is performed at the optimal time point. Thereby, fine tuning is achieved. The fine tuning and the above-described coarse tuning can be performed in any order. An alternative possibility is that, in the case of knowing the period of the clock model and the lower limit or the upper limit of the clock model, the sampling adjustment is set to be offset by half a period with respect to the known lower limit or upper limit.

[0021] In one embodiment of the method, the usage data is encoded and decoded by means of 8b10b encoding, wherein the preset bit length corresponds to 10 bits. Thus, robust communication becomes feasible, wherein the number of 1s in the transmitted data word differs from the number of 0s by at most two, i.e., the transmitted data word contains four 1s and six 0s, five 1s and five 0s, or six 1s and four 0s. Thereby, 8 bits can be encoded and an additional control word can be transmitted.

[0022] The invention also includes a first passive participant of a bus system, which is designed to perform the method steps performed by the first passive participant.

[0023] To this end, a first passive participant of the bus system can have a first transmission interface for a first differential two-wire line, a second transmission interface for a second differential two-wire line, a first transmission SERDES element, and a second transmission SERDES element, and is designed to encode an original static model with a preset bit length in the first transmission SERDES element and transmit it as an encoded static model via the first transmission interface. Here, the original static model defines a transmit-receive clock. The first passive participant is also designed to encode the original usage data synchronously with the original static model time in the second transmission SERDES element and transmit it as encoded usage data via the second transmission interface. Here, the original usage data includes transmit data words with a preset bit length.

[0024] In one embodiment of the first passive participant, it is designed to transmit at least one gigabit per second, in particular 1.25 Gbit / s, via the first differential two-wire line and at least one gigabit per second, in particular 1.25 Gbit / s, via the second differential two-wire line.

[0025] In one embodiment of the first passive participant, the transmit-receive clock corresponds to one tenth of the data rate transmitted via the first differential two-wire line or via the second differential two-wire line.

[0026] In one embodiment of the first passive participant, the original static model includes a first number of first bits with a bit value of 1 and a second number of second bits with a bit value of 0. The first bits are set first and then the second bits in the static model, where the first number and the second number together correspond to the bit length.

[0027] In one embodiment of the first passive participant, it is designed to encode the original usage data by means of 8b10b encoding, where the bit length corresponds to 10 bits.

[0028] The invention also includes a second passive participant of the bus system, which is designed to perform the method steps performed by the second passive participant.

[0029] To this end, the second passive participant of the bus system can have a first receiving interface for the first differential two-wire line, a second receiving interface for the second differential two-wire line, a first receiving SERDES element, and a second receiving SERDES element. The second passive participant is designed to receive the encoded static model with a preset bit length via the first receiving interface and the encoded usage data with a preset bit length via the second receiving interface. In addition, the second passive participant is designed to generate a sampling clock and a clock synchronized with the transmit-receive clock from the encoded static model, where the sampling clock has a first phase shift relative to the transmit-receive clock, and the synchronized clock has a second phase shift relative to the transmit-receive clock. The second passive participant is also designed to decode the encoded static model by means of the first receiving SERDES element and decode the encoded usage data by means of the second receiving SERDES element, thereby obtaining a received data word. Here, the first receiving SERDES element and the second receiving SERDES element can operate according to the sampling clock, and the received data word can be output synchronously with the synchronized clock.

[0030] In one embodiment of the second passive participant, the transmit-receive clock corresponds to one-tenth of the data rate transmitted via the first differential two-wire line or via the second differential two-wire line.

[0031] In one embodiment of the second passive participant, the sampling clock corresponds to the data rate transmitted via the first differential two-wire line or via the second differential two-wire line or half of the data rate transmitted via the first differential two-wire line or via the second differential two-wire line.

[0032] In one embodiment of the second passive participant, the first phase shift is 90 degrees. In one embodiment of the second passive participant, the second phase shift is 18 degrees.

[0033] In one embodiment of the second passive participant, the encoded static model includes a first number of first bits with a bit value of 1 and a second number of second bits with a bit value of 0. The first bits are set first and then the second bits are set in the static model.

[0034] In one embodiment of the second passive participant, the static model designed to be decoded by the first receiving SERDES element is shifted by means of a first shift register until the original static model is output at the output of the first receiving SERDES element, and the received data word decoded by the second receiving SERDES element is shifted by means of a second shift register by the same number of bits as the first shift register.

[0035] In one embodiment of the second passive participant, the second passive participant further has a first delay element between the first receive input and the first receiver SERDES element and a second delay element between the second receive input and the first receiver SERDES element. The second passive participant is designed to delay the encoded static model by the first delay element and the encoded usage data by the second delay element. The second passive participant is also designed to initially gradually reduce the delays of the first delay element and the second delay element during initialization and check whether the sampled clock model changes to determine the lower limit of the delay, and then gradually increase the delays of the first delay element and the second delay element and check whether the sampled clock model changes to determine the upper limit of the delay. In addition, the second passive participant is designed to subsequently set the delays of the first delay element and the second delay element to the average of the lower limit and the upper limit.

[0036] In one embodiment of the second passive participant, the encoded usage data is decoded by means of 8b10b encoding, where a preset bit length corresponds to 10 bits.

[0037] The invention also includes a bus system having a first passive participant according to the invention and a second passive participant according to the invention. The bus system can also include an active participant, namely a control device. In particular, the first passive participant and the second passive participant can be arranged on a circuit board together with a first differential pair and a second differential pair, where the circuit board can be a PCB (printed circuit board). In this case, the first differential pair and the second differential pair can be designed as printed conductors.

[0038] It can be proposed that the second passive participant is also designed to communicate with the first passive participant via an additional first differential pair and an additional second differential pair, and in this case, the described method is used for communication from the second passive participant to the first passive participant.

[0039] In an exemplary embodiment of the bus system, the second passive participant has an additional first transmission interface for an additional first differential two-wire line, an additional second transmission interface for an additional second differential two-wire line, an additional first transmission SERDES element, and an additional second transmission SERDES element. The second passive participant is designed to encode an additional original static model consisting of a preset bit length in the additional first transmission SERDES element and transmit it as an additional encoded static model via the additional first transmission interface, where the additional original static model defines an additional transmission and reception clock. The second passive participant is also designed to encode additional original usage data in the additional second transmission SERDES element in time synchronization with the additional original static model and transmit it as additional encoded usage data via the additional second transmission interface, where the additional original usage data includes an additional transmission data word having a preset bit length. The first passive participant has an additional first reception interface for the additional first differential two-wire line, an additional second reception interface for the additional second differential two-wire line, an additional first reception SERDES element, and an additional second reception SERDES element. The first passive participant is designed to receive the additional encoded static model via the additional first reception interface and receive the additional encoded usage data via the additional second reception interface. The first passive participant is designed to generate an additional sampling clock and an additional clock synchronized with the additional transmission and reception clock from the additional encoded static model, where the additional sampling clock has an additional first phase shift relative to the additional transmission and reception clock, and the additional synchronized clock has an additional second phase shift relative to the additional transmission and reception clock. The first passive participant is also designed to decode the additional encoded static model by means of the additional first reception SERDES element and decode the additional encoded usage data by means of the additional second reception SERDES element to obtain an additional received data word. The first passive participant is designed to operate the additional first reception SERDES element and the additional second reception SERDES element according to the additional sampling clock, and the additional received data word can be output synchronously with the additional synchronized clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be explained in more detail below based on embodiments and with reference to the drawings. In this case, it is schematically shown respectively

[0041] Figure 1 showing a bus system;

[0042] Figure 2 showing the clock and usage data during communication; and

[0043] Figure 3 showing another bus system. Detailed implementation mode

[0044] Figure 1 The first passive participant 100 and the second passive participant 200 of the bus system 1 are shown, and the active participant 10 of the bus system 1 is also shown. The first passive participant 100 has a first transmission interface 101 for the first differential two-wire line 11 and a second transmission interface 102 for the second differential two-wire line 12. In addition, the first passive participant 100 has a first transmission SERDES element 111 and a second transmission SERDES element 112. The first passive participant 100 is connected to the second passive participant 200 by means of the first differential two-wire line 11 and the second differential two-wire line 12. The second passive participant 200 has a first reception interface 201 for the first differential two-wire line 11 and a second reception interface 202 for the second differential two-wire line 12. In addition, the second passive participant 200 has a first reception SERDES element 211 and a second reception SERDES element 212.

[0045] The first transmission SERDES element 111 can also be referred to as a first parallel-to-serial converter. The second transmission SERDES element 112 can also be referred to as a second parallel-to-serial converter. The first reception SERDES element 211 can also be referred to as a first serial-to-parallel converter. The second reception SERDES element 212 can also be referred to as a second serial-to-parallel converter.

[0046] The first passive participant 100 is designed to encode the original static model 306 with a preset bit length in the first transmission SERDES element 111 and transmit it as the encoded static model 307 via the first transmission interface 101. The original static model 306 defines a transmission and reception clock 301 ( Figure 1 not shown in the figure). In addition, the first passive participant 100 is designed to encode the original usage data 312 in the second transmission SERDES element 112 in a time-synchronized manner with the original static model 306 and transmit it as the encoded usage data 314 via the second transmission interface 102, where the original usage data 312 includes a transmission data word 311 with a preset bit length ( Figure 1 not shown in the figure).

[0047] The second passive participant 200 is designed to receive the encoded static model 307 with a preset bit length via a reception interface 201 and receive the encoded usage data 314 with a preset bit length via the second reception interface 202. In addition, the second passive participant 200 is designed to generate a sampling clock 302 ( Figure 1 not shown in the figure) and a clock 303 synchronized with the transmission and reception clock 301 from the encoded static model 307 ( Figure 1(not shown in the figure), wherein the sampling clock 302 has a first phase shift relative to the transmit-receive clock 301 and the synchronized clock 303 has a second phase shift relative to the transmit-receive clock 301. In addition, the second passive participant 200 is designed to: decode the encoded static model 307 by means of the first receive SERDES element 211 to obtain the decoded static model 308 and is also designed to: decode the encoded usage data 314 by means of the second receive SERDES element 212 to obtain the received data word as part of the decoded usage data 316. The first receive SERDES element 211 and the second receive SERDES element 212 can operate according to the sampling clock 302, wherein the received data word can be output synchronously with the synchronized clock 303.

[0048] In a method for communicating between the first passive participant 100 and the second passive participant 200 of the bus system 1, the first differential two-wire line 11 and the second differential two-wire line 12 are used for communication. The original static model 306 with a preset bit length is transmitted via the first differential two-wire line 11. The original static model 306 defines the transmit-receive clock 301. The original usage data 312 is transmitted via the second differential two-wire line 12. The original usage data 312 includes a transmit data word 311 with a preset bit length. The first passive participant 100 encodes the original static model 306 in the first transmit SERDES element 111 and sends it to the second passive participant 200 as the encoded static model 307 via the first differential line 11. The first passive participant 100 also encodes the original usage data 312 in the second transmit SERDES element 112 in a time-synchronized manner with the original static model 306 and sends it to the second passive participant 200 as the encoded usage data 314 via the second differential two-wire line 12. The second passive participant 200 receives the encoded static model 307 and the encoded usage data 314 and generates the sampling clock 302 and the clock 303 synchronized with the transmit-receive clock 301 from the encoded static model 307. The sampling clock 302 has a first phase shift relative to the transmit-receive clock 301. The synchronized clock 303 has a second phase shift relative to the transmit-receive clock 301. The second passive participant 200 decodes the encoded static model 307 by means of the first receive SERDES element 211 and decodes the encoded usage data 314 by means of the second receive SERDES element 212 to obtain the received data word. The first receive SERDES element 211 and the second receive SERDES element 212 operate according to the sampling clock 302, wherein the received data word is output synchronously with the synchronized clock 303.

[0049] It can be proposed that at least one gigabit per second, in particular 1.25 Gbit / s, can be transmitted via the first differential pair 11, and at least one gigabit per second, in particular 1.25 Gbit / s, can be transmitted via the second differential pair 12. It can be proposed that the transmit-receive clock 301 corresponds to one tenth of the data rate transmitted via the first differential pair 11 or via the second differential pair 12. Thus, it can be proposed that 1.25 Gbit / s is transmitted via the first differential pair 11 or the second differential pair 12 and the transmit-receive clock 301 corresponds to 125 MHz, i.e., 125 Mbit / s.

[0050] Other components of the first passive participant 100 and the second passive participant 200 are described below. These other components are optional and improve the described bus system 1. The first passive participant 100 includes an encoding unit 121 with which the usage data 310 can be encoded. Here, it can be proposed to use so-called 8b10b encoding, in which 8 information bits are encoded by 10 line bits. The preset bit length then corresponds to 10 bits, such that the static model also includes 10 bits. In particular, the information including 8 bits is converted into a transmit data word 311 including 10 bits, such that the transmit data word 311 includes at least four 1 bits and at most six 1 bits. The second passive participant 200 has a decoding unit 221 with which the usage data 310 can be decoded similar to the encoding unit 121 and, for example, the information including 8 bits can be obtained again from the received data word including 10 bits.

[0051] It can be proposed that the first passive participant 100 includes a first phase regulator 131. The first phase regulator 131 can be designed to output the transmit-receive clock 301. Here, the transmit-receive clock 301 is particularly output to the first transmit SERDES element 111 via the first clock line 132. In addition, the transmit-receive clock 301 can be forwarded from the first transmit SERDES element 111 to the second transmit SERDES element 112 via the first clock line 132. In addition, the transmit-receive clock 301 can also be forwarded to the encoding unit 121 via the first clock line 132. The first phase regulator 131 can be designed as a PLL. In addition, the first phase regulator 131 can be designed to output a data clock via the second clock line 133, which data clock corresponds to the transmission rate of the first differential pair 11 or the second differential pair 12. Alternatively, the first phase regulator 131 can be designed to output a data clock via the second clock line 133, which data clock has a data rate corresponding to half of the transmission rate of the first differential pair 11 or the second differential pair 12. In the first case, each bit to be transmitted can be transmitted at each rising edge 304 ( Figure 2 shown). In the second case, each bit to be transmitted can be transmitted at each rising edge 304 and each falling edge 305 (Figure 2 transmit each bit to be transmitted in the (shown in

[0052] It can be proposed that the static model includes a first number of first bits with a bit value of 1 and a second number of second bits with a bit value of 0, where the first bits are set first and then the second bits in the static model, and where the first number and the second number together correspond to the bit length. If the bit length is 10, the static model can in particular take the following form. 1000000000 1100000000 1110000000 1111000000 1111100000 1111110000 1111111000 1111111100 1111111110

[0062] In principle, it is also possible to change the static model, whereby nine different messages can be transmitted overall. Here, it can be proposed that the transmit-receive clock 301 output via the first clock line 132 is synchronized with the start of the static model respectively.

[0063] In one embodiment, the first number and the second number are the same. In the case of the static model 1111100000 corresponding to five ones and five zeros in the above example, the transmit-receive clock 301 is designed as a square wave signal with one-tenth of the transmission rate.

[0064] The second passive participant 200 includes a second phase regulator 231. The second phase regulator 231 is connected to the first receiving interface 201 and is designed to generate a clock 303 and a sampling clock 302 synchronized with the transmit-receive clock 301 from the transmitted and encoded static model 307. Here, the sampling clock 302 can have the same data rate as the data clock of the first passive participant 100. The synchronized clock 303 can be output via the third clock line 232. The sampling clock 302 can be output via the fourth clock line 233. The third clock line 232 connects the second phase regulator 231 to the first receiving SERDES element 211, the second receiving SERDES element 212, and the decoding unit 221. The second phase regulator 231 can be designed as a PLL.

[0065] It can be proposed that the first phase shift of the synchronized clock 303 is 90 degrees. It can be proposed that the second phase shift of the sampling clock 302 is 18 degrees.

[0066] The sampling clock 302 is forwarded via the fourth clock line 233 to the first receiving SERDES element 211 and the second receiving SERDES element 212. Based on the sampling clock 302, the individual bits of the encoded static model 307 can be sampled in the first receiving SERDES element 211 and the encoded usage data 314 can be sampled in the second receiving SERDES element 212, where the individual bits of the encoded static model and the encoded usage data are combined into a received data word by means of a synchronous clock 303, respectively.

[0067] The static model 308 decoded by the first receiving SERDES element 211 can be forwarded to the clock reset unit 234 of the second passive participant 200. This enables coarse adjustment of the received data word. For this purpose, the static model 308 decoded by the first receiving SERDES element 211 can be shifted by means of a first shift register until the original static model 306 is output at the output of the first receiving SERDES element 211, and furthermore, the received data word decoded by the second receiving SERDES element 212 can be shifted by means of a second shift register by the same number of positions as the first shift register. The clock reset unit 234 is also connected to the third clock line 232. Here, the first shift register can be integrated into the second passive participant 200 and in particular into the first receiving SERDES element 211 there. Here, the second shift register can be integrated into the second passive participant 200 and in particular into the second receiving SERDES element 212 there.

[0068] The second passive participant 200 also has a first delay element 241 and a second delay element 242. The encoded static model 307 is delayed by the first delay element 241 and the encoded usage data 314 is delayed by the second delay element 242. Here, as Figure 1 shown, it can be proposed that the encoded static model 307 forwarded to the second phase regulator 231 is not guided through the first delay element 241 and thus arrives at the second phase regulator 231 without delay. At initialization, the delays of the first delay element 241 and the second delay element 242 are first gradually reduced and it is checked whether the sampled clock model changes. Thus, the lower limit of the delay is determined. Then the delays of the first delay element 241 and the second delay element 242 are gradually increased and it is checked whether the sampled clock model changes. Thus, the upper limit of the delay is determined. Subsequently, the delays of the first delay element 241 and the second delay element 242 are adjusted to the average of the lower limit and the upper limit. Another alternative possibility is to adjust the sampling in such a way that it is offset by half a period with respect to the known lower or upper limit, given knowledge of the period of the clock model and the upper or lower limit of the clock model.

[0069] The first passive participant 100 has a first FIFO element 151. The first FIFO element 151 is connected to the active participant 10 via a transmission data line 152 and a first control line 153. Here, contrary to the illustration of Figure 1 , the transmission data line 152 and the first control line 153 can also be guided via other passive participants not shown. The first FIFO element 151 is designed to forward the telegrams received via the transmission data line 152 and possibly the control signals received via the first control line 153 to the encoding unit 121 according to the "first in, first out" principle. The second passive participant 200 has a second FIFO element 251. The second FIFO element 251 has a reception data line 252 and a second control line 253. The second FIFO element 251 is designed to forward the telegrams received from the decoding unit 221 via the reception data line 252 and possibly to forward the received control signals via the second control line 253 according to the "first in, first out" principle.

[0070] It can be proposed that the first transmission interface 101, the second transmission interface 102, the first reception interface 201, and the second reception interface 202 are designed as terminals, where the first twin line 11 and the second twin line 12 are respectively designed as cable connections. In this case, the first passive participant 100 and the second passive participant 200 can be arranged in different housings.

[0071] Alternatively, it can also be proposed that the first transmission interface 101, the second transmission interface 102, the first reception interface 201, the second reception interface 202, the first twin line 11, and the second twin line 12 are configured as printed conductors on a circuit board. In this case, the first passive participant 100 and the second passive participant 200 can be arranged in a common housing.

[0072] Within the first participant 100, the participating components, namely the first transmit SERDES element 111, the second transmit SERDES element 112, the encoding unit 121, the first phase regulator 131, and the first FIFO element 151, may be wholly or partly provided within a field programmable gate array (FPGA). Within the second participant 200, the participating components, namely the first receive SERDES unit 211, the second receive SERDES unit 212, the decoding unit 221, the second phase regulator 231, the clock reset unit 234, the first delay unit 241, the second delay element 242, and the second FIFO element 251, may be wholly or partly provided within a programmable logic gate. Instead of a programmable logic gate, an application-specific integrated circuit (ASIC) may also be used for the first passive participant 100 and the second passive participant 200.

[0073] Figure 2 The transmit-receive clock 301, the use data 310, the sampling clock 302, and the synchronized clock 303 during the execution of the communication method between the first passive participant 100 and the second passive participant 200 in the bus system 1 are shown in a vertically stacked manner with respect to each other. Here, the transmit-receive clock 301 includes the bit sequence 1111100000, i.e., five bit values of 1 followed by five bit values of 0. The transmit data word 311 consisting of ten bits is output as part of the use data 310 synchronously with the transmit-receive clock 301. The synchronized clock 303 is phase-shifted by 18 degrees with respect to the transmit-receive clock 301, because in this way it is possible to ensure that the use data 310 is always sampled in the data eye. The sampling clock 302 has a frequency five times that of the transmit-receive clock 301 or the synchronized clock 303, whereupon the use data 310 is sampled at the rising edge 304 and the falling edge 305.

[0074] Figure 3 The bus system 1 is shown, which corresponds to Figure 1The bus system 1. The second passive participant 200 has an additional first transmission interface 401 for an additional first differential two-wire line 13, an additional second transmission interface 402 for an additional second differential two-wire line 14, an additional first transmission SERDES element 411, and an additional second transmission SERDES element 412. The second passive participant 200 is designed to: encode an additional original static model 321 consisting of a preset bit length in the additional first transmission SERDES element 411 and transmit it as an additional encoded static model 322 via the additional first transmission connection 401, where the additional original static model 321 defines an additional transmission and reception clock. In addition, the second passive participant 200 is designed to: encode additional original usage data 331 in the additional second transmission SERDES element 412 in a time-synchronized manner with the additional original static model 321 and transmit it as additional encoded usage data 332 via the additional second transmission interface 402, where the additional original usage data 332 includes an additional transmission data word having a preset bit length. The first passive participant 100 has an additional first reception interface 501 for the additional first differential two-wire line 13, an additional second reception interface 502 for the additional second differential two-wire line 14, an additional first reception SERDES element 511, and an additional second reception SERDES element 512. The first passive participant 100 is designed to: receive the additional encoded static model 322 via the additional first reception interface 501 and receive the additional encoded usage data 332 via the additional second reception interface 502. The first passive participant 100 is designed to: generate an additional sampling clock and an additional synchronized clock synchronized with the additional transmission and reception clock from the additional encoded static model 322, where the additional sampling clock has an additional first phase shift relative to the additional transmission and reception clock, and the additional synchronized clock has an additional second phase shift relative to the additional transmission and reception clock. Here, the additional sampling clock and the additional synchronized clock can be part of an additional decoded static model 323. The first passive participant 100 is designed to: decode the additional encoded static model 322 by means of the additional first reception SERDES element 511 to obtain an additional decoded static model 323 and is also designed to: decode the additional encoded usage data 332 by means of the additional second reception SERDES element 512 to obtain an additional received data word as part of the additional decoded usage data 333. The additional first reception SERDES element 511 and the additional second reception SERDES element 512 can operate according to the additional sampling clock, where the additional received data word can be output synchronously with the additional synchronized clock.

[0075] At Figure 3It is also shown that the second passive participant 200 optionally has an additional first phase regulator 431, an additional first clock line 432, an additional second clock line 433, an additional first FIFO element 451, an additional transmission data line 452, and an additional first control line 453, which can be designed similar to the first phase regulator 131, the first clock line 132, the second clock line 132, the first FIFO element 151, the first transmission data line 152, or the first control line 153 of the first passive participant 100 and can perform the same functions. In addition, the first passive participant 100 includes an additional second phase regulator 531, an additional third clock line 532, an additional fourth clock line 533, an additional clock reset unit 534, an additional first delay element 541, an additional second delay element 542, an additional second FIFO element 551, an additional reception data line 552, and an additional second control line 553, which are designed similar to the second phase regulator 231, the third clock line 232, the fourth clock line 233, the clock reset unit 234, the first delay element 241, the second delay element 242, the second FIFO element 251, the reception data line 252, or the second control line 253 and can perform the same functions.

[0076] Thus, in Figure 3 the bus system 1, communication is carried out from the first passive participant 100 to the second passive participant 200 via the first differential pair 11 and the second differential pair 12, while communication from the second passive participant 200 to the first passive participant 100 is carried out via the additional first differential pair 13 and the additional second differential pair 14. The additional passive participant 600 of the bus system 1 is also shown in Figure 3 wherein the reception data line 252 and the second control line 253 are led through the additional passive participant 600 to the additional transmission data line 452 and the additional first control line 453. The additional reception data line 552 and the additional second control line 553 are connected to the active participant 10. The data telegram sent by the active participant 10 can thus be transmitted from the first passive participant 100 to the second passive participant 200 via the first differential pair 11 and the second differential pair 12, then traverse the additional passive participant 600 (or also multiple Figure 3 additional passive participants not shown in the figure), and then be transmitted from the second passive participant 200 to the first passive participant 100 via the additional first differential pair 13 and the additional second differential pair 14. The data telegram then reaches the active participant 10 again from the first passive participant 100. Thus, a communication structure corresponding to the EtherCAT standard is realized.

[0077] In particular, it can be stated here that the transmit-receive clock 301 and another transmit-receive clock have the same frequency. Additionally, it is also feasible that the sampling clock 302 and another sampling clock have the same frequency.

[0078] Description of Reference Numerals

[0079] 1 Bus system

[0080] 10 Active participant

[0081] 11 First differential pair

[0082] 12 Second differential pair

[0083] 13 Another first differential pair

[0084] 14 Another second differential pair

[0085] 100 First passive participant

[0086] 101 First transmit interface

[0087] 102 Second transmit interface

[0088] 111 First transmit SERDES element

[0089] 112 Second transmit SERDES element

[0090] 121 Encoding unit

[0091] 131 First phase regulator

[0092] 132 First clock line

[0093] 133 Second clock line

[0094] 151 First FIFO element

[0095] 152 Transmit data line

[0096] 153 First control line

[0097] 200 Second passive participant

[0098] 201 First receive interface

[0099] 202 Second receive interface

[0100] 211 First receive SERDES element

[0101] 212 Second receive SERDES element

[0102] 221 Decoding unit

[0103] 231 Second-phase regulator

[0104] 232 Third clock line

[0105] 233 Fourth clock line

[0106] 234 Clock reset unit

[0107] 241 First delay element

[0108] 242 Second delay element

[0109] 251 Second FIFO element

[0110] 252 Receive data line

[0111] 253 Second control line

[0112] 301 Transmit-receive clock

[0113] 302 Sampling clock

[0114] 303 Synchronized clock

[0115] 304 Rising edge

[0116] 305 Falling edge

[0117] 306 Original static model

[0118] 307 Encoded static model

[0119] 308 Decoded static model

[0120] 310 Use data

[0121] 311 Transmit data word

[0122] 312 Original use data

[0123] 314 Encoded use data

[0124] 316 Decoded use data

[0125] 321 Another original static model

[0126] 322 Another encoded static model

[0127] 323 Another decoded static model

[0128] 331 Another original use data

[0129] 332 Another encoded use data

[0130] 333 Additional decoded usage data

[0131] 401 Additional first transmission interface

[0132] 402 Additional second transmission interface

[0133] 411 Additional first transmission SERDES component

[0134] 412 Additional second transmission SERDES component

[0135] 421 Additional encoding unit

[0136] 431 Additional first phase regulator

[0137] 432 Additional first clock line

[0138] 433 Additional second clock line

[0139] 451 Additional first FIFO component

[0140] 452 Additional transmission data line

[0141] 453 Additional first control line

[0142] 501 Additional first reception interface

[0143] 502 Additional second reception interface

[0144] 511 Additional first reception SERDES component

[0145] 512 Additional second reception SERDES component

[0146] 521 Additional decoding unit

[0147] 531 Additional second phase regulator

[0148] 532 Additional third clock line

[0149] 533 Additional fourth clock line

[0150] 534 Additional clock reset unit

[0151] 541 Additional first delay component

[0152] 542 Additional second delay component

[0153] 551 Additional second FIFO component

[0154] 552 Additional reception data line

[0155] 553 Another second control line

[0156] 600 Another passive participant

Claims

1. A method for communication between a first passive participant (100) and a second passive participant (200) in a bus system (1), wherein a first differential two-wire line (11) and a second differential two-wire line (12) are used for communication, wherein an original static model (306) having a preset bit length is transmitted via the first differential two-wire line (11), wherein the original static model (306) defines a transmit-receive clock (301), wherein original usage data (312) is transmitted via the second differential two-wire line (12), wherein the original usage data (312) includes a transmit data word (311) having a preset bit length, wherein the first passive participant (100) encodes the original static model (306) in a first transmit SERDES element (111) and transmits it as an encoded static model (307) to the second passive participant (200) via the first differential two-wire line (11), and encodes the original usage data (312) synchronously with the original static model (306) in a second transmit SERDES element (112) and transmits it as encoded usage data (314) to the second passive participant (200) via the second differential two-wire line (12), wherein the second passive participant (200) receives the encoded static model (307) and the encoded usage data (314), wherein the second passive participant (200) generates a sampling clock (302) and a clock (303) synchronized with the transmit-receive clock (301) from the encoded static model (307), wherein the sampling clock (302) has a first phase shift relative to the transmit-receive clock (301), wherein the synchronized clock (303) has a second phase shift relative to the transmit-receive clock (301), wherein the second passive participant (200) decodes the encoded static model (307) by means of a first receive SERDES element (211) and decodes the encoded usage data (314) by means of a second receive SERDES element (212), thereby obtaining a received data word, wherein the first receive SERDES element (211) and the second receive SERDES element (212) operate according to the sampling clock (302), and wherein the received data word is output synchronously with the synchronized clock (303).

2. The method according to claim 1, wherein the transmit-receive clock (301) corresponds to one tenth of the data rate transmitted via the first differential two-wire line (11) or via the second differential two-wire line (12).

3. The method according to claim 1 or 2, wherein the sampling clock (302) corresponds to the data rate transmitted via the first differential two-wire line (11) or via the second differential two-wire line (12) or half of the data rate transmitted via the first differential two-wire line (11) or via the second differential two-wire line (12).

4. The method according to claim 1 or 2, wherein the first phase shift is 90 degrees.

5. The method according to claim 1 or 2, wherein the second phase shift is 18 degrees.

6. The method according to claim 1 or 2, wherein the original static model includes a first number of first bits having a bit value of 1 and a second number of second bits having a bit value of 0, wherein the first bits are set first and then the second bits are set in the original static model, and wherein the first number and the second number together correspond to the bit length.

7. The method according to claim 1 or 2, wherein the static model (308) decoded by the first receiving SERDES element (211) is shifted by means of a first shift register until the original static model (306) is output at the output of the first receiving SERDES element (211), and wherein the received data word decoded by the second receiving SERDES element (212) is shifted by the same number of bit positions as the first shift register by means of a second shift register.

8. The method according to claim 1 or 2, wherein in the second passive participant (200) the encoded static model (307) is delayed by a first delay element (241), and the encoded usage data (314) is delayed by a second delay element (242), wherein at initialization the delays of the first delay element (241) and the second delay element (242) are first gradually reduced, and it is checked whether the sampled clock model changes to determine the lower limit of the delay, then the delays of the first delay element (241) and the second delay element (242) are gradually increased, and it is checked whether the sampled clock model changes to determine the upper limit of the delay, and subsequently the delays of the first delay element (241) and the second delay element (242) are set to the average of the lower limit and the upper limit.

9. The method according to claim 1 or 2, wherein the original usage data is encoded and decoded by means of 8b10b encoding, and wherein the preset bit length corresponds to 10 bits.

10. A bus system (1) having a first passive participant (100) and a second passive participant (200), wherein the first passive participant (100) has a first transmission interface (101) for a first differential two-wire line (11), a second transmission interface (102) for a second differential two-wire line (12), a first transmission SERDES element (111) and a second transmission SERDES element (112), wherein the first passive participant (100) is designed to: encode an original static model (306) having a preset bit length in the first transmission SERDES element (111) and transmit it as an encoded static model (307) via the first transmission interface (101), wherein the original static model (306) defines a transmit-receive clock (301), and is also designed to: encode original usage data (312) in time synchronization with the original static model (306) in the second transmission SERDES element (112) and transmit it as encoded usage data (314) via the second transmission interface (102), wherein the original usage data (312) includes a transmit data word (311) having a preset bit length, wherein the second passive participant (200) has a first reception interface (201) for the first differential two-wire line (11), a second reception interface (202) for the second differential two-wire line (12), a first reception SERDES element (211) and a second reception SERDES element (212), wherein the second passive participant (200) is designed to: receive the encoded static model (307) having a preset bit length via the first reception interface (201) and receive the encoded usage data (314) having a preset bit length via the second reception interface (202), wherein the second passive participant (200) is designed to: generate a sampling clock (302) and a clock (303) synchronized with the transmit-receive clock (301) from the encoded static model (307), wherein the sampling clock (302) has a first phase shift relative to the transmit-receive clock (301), wherein the synchronized clock (303) has a second phase shift relative to the transmit-receive clock (301), wherein the second passive participant (200) is designed to: decode the encoded static model (307) by means of the first reception SERDES element (211) and decode the encoded usage data (314) by means of the second reception SERDES element (212) to obtain a received data word, wherein the first reception SERDES element (211) and the second reception SERDES element (212) can operate according to the sampling clock (302), and wherein the received data word can be output synchronously with the synchronized clock (303).

11. The bus system (1) according to claim 10, wherein the second passive participant (200) is designed such that: the static model (308) decoded by the first receiving SERDES element (211) is shifted by means of a first shift register until the original static model (306) is output at the output of the first receiving SERDES element (211), and wherein the received data word decoded by the second receiving SERDES element (212) is shifted by means of a second shift register by the same number of bits as the first shift register.

12. The bus system (1) according to claim 10 or 11, wherein the second passive participant (200) further has a first delay element (241) between the first receiving interface (201) and the first receiving SERDES element (211) and a second delay element (242) between the second receiving interface (202) and the second receiving SERDES element (212), wherein the encoded static model (307) can be delayed by the first delay element (241) and the encoded usage data (314) can be delayed by the second delay element (242), and wherein the second passive participant (200) is designed such that: during initialization, the delays of the first delay element (241) and the second delay element (242) are first gradually reduced, and it is checked whether the sampled clock model changes and thus the lower limit of the delay is determined, then the delays of the first delay element (241) and the second delay element (242) are gradually increased, and it is checked whether the sampled clock model changes and thus the upper limit of the delay is determined, and subsequently the delays of the first delay element (241) and the second delay element (242) are set to the average of the lower limit and the upper limit.

13. The bus system (1) according to claim 10 or 11, wherein the second passive participant (200) has an additional first transmission interface (401) for an additional first differential two-wire line (13), an additional second transmission interface (402) for an additional second differential two-wire line (14), an additional first transmission SERDES element (411) and an additional second transmission SERDES element (412), wherein the second passive participant (200) is designed to: encode an additional original static model (321) consisting of the preset bit length in the additional first transmission SERDES element (411) and transmit it as an additional encoded static model (322) via the additional first transmission interface (401), wherein the additional original static model (321) defines an additional transmission and reception clock, and is also designed to: encode the additional original static model (321) in the additional second transmission SERDES element (412) in time synchronization with the additional original static model (321) and transmit it as additional encoded usage data (332) via the additional second transmission interface (402), wherein the additional original usage data (331) includes additional transmission data words having a preset bit length, wherein the first passive participant (100) has an additional first reception interface (501) for the additional first differential two-wire line (13), an additional second reception interface (502) for the additional second differential two-wire line (14), an additional first reception SERDES element (511) and an additional second reception SERDES element (512), wherein the first passive participant (100) is designed to: receive the additional encoded static model (322) via the additional first reception interface (501) and receive the additional encoded usage data (332) via the additional second reception interface (502), wherein the first passive participant (100) is designed to: generate an additional sampling clock and a clock synchronized with the additional transmission and reception clock from the additional encoded static model (322), wherein the additional sampling clock has an additional first phase shift relative to the additional transmission and reception clock, wherein the additional synchronized clock has an additional second phase shift relative to the additional transmission and reception clock, wherein the first passive participant (100) is designed to: decode the additional encoded static model (322) by means of the additional first reception SERDES element (511), and decode the additional encoded usage data (332) by means of the additional second reception SERDES element (512) to obtain an additional received data word, wherein the additional first reception SERDES element (511) and the additional second reception SERDES element (512) can operate according to the additional sampling clock,Wherein the additional received data word can be output synchronously with the additional synchronous clock.

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