A high-side current detection circuit for bridge drive

Abstract

The present invention belongs to the technical field of power integrated circuits, and specifically relates to a high-side current detection circuit for bridge drive. In the present invention, an NMOS is used as the high-side power transistor for illustration. The gates of the main power transistor and the detection power transistor of the present invention are coupled together, and the sources are coupled together and connected to the power supply VS. The present invention uses a current mirror composed of PNP transistors and a current mirror composed of PMOS transistors cascaded to jointly clamp the source ends of the main power (NMOS) transistor and the detection power transistor (NMOS) to make their potentials consistent, ensuring that the detection current and the output current are scaled according to the ratio of the width-to-length ratios of the main power transistor and the detection power transistor, and ensuring the accuracy between the detection current and the detected current. The present invention can be used in a bridge drive circuit with medium and low voltages of 12-60V. The detection current is output to an external pin and an external high-precision resistor is connected for measurement.

Description

Technical Field

[0001] The present invention belongs to the technical field of power integrated circuits, and particularly relates to a current detection circuit for a high-side power transistor of a bridge drive circuit. Background Art

[0002] In a bridge motor drive chip, it is necessary to detect the magnitude of the current flowing through the power transistor in the high-side bridge arm in order to perform real-time control to avoid overheating caused by excessive current and burning out the chip. Since the "ground" of the high-side bridge arm is the output of the driver and is floating, floating between the global ground and the power supply voltage. The output of the full-bridge motor driver is connected to the motor load. If it is necessary to detect the current flowing through the load, using a resistor in series with the motor for measurement will cause a large power loss, and since the output is high voltage, an operational amplifier with a high common-mode range is required. Therefore, such a detection method is uneconomical and has high energy loss. Summary of the Invention

[0003] In view of the above requirements, the present invention can perform low-loss detection of current by using an integrated detection power transistor, and can be externally connected to a resistor to convert it into a voltage quantity for sampling to an external controller. The technical solution of the present invention is as follows:

[0004] A high-side power transistor detection circuit with a bridge drive, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first Zener diode, a first diode, a second diode, a first NPN transistor, a second NPN transistor, and a third NPN transistor; wherein, the gate of the first NMOS transistor is connected to the high-side power transistor drive circuit; the drain of the first NMOS transistor is connected to the power supply voltage VS; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the low-side power transistor drive circuit; the source of the third NMOS transistor is connected to ground; the source of the second NMOS transistor is connected to the power supply voltage VS; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor; the source of the second NMOS transistor is connected to the emitter of the second PNP transistor and the emitter of the third PNP transistor; the emitter of the first PNP transistor is connected to the source of the first NMOS transistor, and the base and collector of the first PNP transistor are connected to the source of the first PMOS transistor; the base of the second PNP transistor is connected to the base of the first PNP transistor and the base of the third PNP transistor, the collector of the second PNP transistor is connected to the source of the second PMOS transistor, and the collector of the third PNP transistor is connected to the source of the third PMOS transistor; the gate of the first PMOS transistor is connected to its drain to form a diode connection; the gates of the second PMOS transistor and the third PMOS transistor are connected to the gate of the first PMOS transistor; the drain of the third PMOS transistor is connected to the anode of the third diode; the cathode of the third diode is connected to the output pin; the drain of the first PMOS transistor is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and at the same time connected to the cathode of the first Zener diode; the gate of the fourth PMOS transistor is connected to a bias voltage generated internally by the power supply voltage; the source of the fourth PMOS transistor is connected to the power supply voltage; the anode of the first Zener diode is connected to ground; the source of the sixth NMOS transistor is connected to the collector of the first NPN transistor; the base of the first NPN transistor is connected to one end of the first resistor; the emitter of the first NPN transistor is connected to ground; the other end of the first resistor is connected to one end of the second resistor and at the same time connected to the source terminal of the fourth NMOS transistor, one end of the third resistor, and one end of the fourth resistor; the other end of the fourth resistor is connected to ground; the other end of the second resistor is connected to the base of the second NPN transistor; the emitter of the second NPN transistor is connected to ground; the collector of the second NPN transistor is connected to the gate of the fourth NMOS transistor and at the same time connected to the drain of the second PMOS transistor and at the same time connected to the cathode of the first diode;The drain of the fourth NMOS transistor is connected to the digital power supply DVDD for internal use generated by stepping down the power supply voltage; the other end of the third resistor is connected to the base of the third NPN transistor; the emitter of the third NPN transistor is connected to ground; the collector of the third NPN transistor is connected to the source of the fifth NMOS transistor and is also connected to the anode of the first diode and the drain of the fifth PMOS transistor; the gate of the fifth PMOS transistor is connected to the low-voltage bias generated by stepping down the power supply voltage; the source of the fifth PMOS transistor is connected to the analog power supply AVDD for internal use generated by stepping down the power supply voltage.

[0005] The beneficial effects of the present invention are as follows: 1) This circuit can perform proportional reduction current detection on the high-side power transistor; 2) It avoids the problem of excessive power loss caused by connecting a resistor in series in the load path; 3) The detection method of this circuit has no influence on the output current of the main power transistor. Description of the Drawings

[0006] Figure 1 It is a structural implementation diagram of a high-side current detection circuit applicable to a bridge drive circuit proposed by the present invention. Detailed Embodiment

[0007] The technical solution of the present invention will be described below with reference to the drawings:

[0008] The present invention supplies power to the overall circuit with the input voltage VS, and the bridge arm composed of the high-side and low-side power transistors is used to drive the motor load. The width-to-length ratio of the detection power transistor is reduced by N times in proportion to that of the main power transistor, and its gate and source are respectively connected to the gate and source of the main power transistor. The drain is clamped by the transistor below to make the drain voltage change the same as that of the main power transistor. It is ensured that the detected current is reduced by N times in proportion to the current flowing through the main power transistor and flows out of the pin and passes through the external high-precision resistor to be converted into a voltage quantity.

[0009] Figure 1 It is a high-side current detection circuit, and the current detection circuit module includes: the first NMOS transistor M0, the second NMOS transistor M2, the third NMOS transistor M1, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM3, the first PNP transistor Q1, the second PNP transistor Q2, the third PNP transistor Q3, the first PMOS transistor PM2, the second PMOS transistor PM3, the third PMOS transistor PM4, the fourth PMOS transistor PM1, the fifth PMOS transistor PM5, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first Zener diode DZ0, the first diode D2, the second diode D3, the first NPN transistor Q4, the second NPN transistor Q5, and the third NPN transistor Q6.

[0010] The power supply node Vs is connected to the drain of the first NMOS transistor M0, the drain of the second NMOS transistor M2, and the source of the fourth PMOS transistor PM1. The gate of the first NMOS transistor M0 is connected to its previous-stage high-side drive circuit; the source of the first NMOS transistor M0 is connected to the drain of the third NMOS transistor M1; the gate of the third NMOS transistor M1 is connected to the previous-stage low-side drive circuit; the source of the third NMOS transistor M1 is connected to ground; the gate of the second NMOS transistor M2 is connected to the gate of the first NMOS transistor M0; the source of the second NMOS transistor M2 is connected to the emitter of the third PNP transistor Q3; the emitter of the first PNP transistor Q1 is connected to the source of the main power transistor M0, i.e., the bridge arm output, and its base and collector are connected to the source terminal of the first PMOS transistor PM2; the sources of the second and third PNP transistors Q2 and Q3 are connected to the source of the detection power transistor M2, and their bases are connected to the base of the first PNP transistor Q1. The collector of the second PNP transistor Q2 is connected to the source of the second PMOS transistor PM3, and the collector of the third PNP transistor Q3 is connected to the source of the third PMOS transistor PM4; the gate of the first PMOS transistor PM2 is connected to its drain to form a diode connection; the gates of the second and third PMOS transistors PM3 and PM4 are connected to the gate of the first PMOS transistor PM2; the drain of the third PMOS transistor PM4 is connected to the anode of the third diode D3; the cathode of the third diode D3 is connected to the output pin; the drain of the first PMOS transistor PM2 is connected to the drain of the sixth NMOS transistor NM3; the gate of the sixth NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM1 and simultaneously to the cathode of the first Zener diode DZ0; the gate of the fourth PMOS transistor PM1 is connected to a bias voltage Vbias1 generated internally by the power supply voltage; the anode of the first Zener diode DZ0 is connected to ground; the source of the sixth NMOS transistor NM3 is connected to the collector of the first NPN transistor Q4; the base of the first NPN transistor Q4 is connected to the negative terminal of the first resistor R1; the emitter of the first NPN transistor Q4 is connected to ground; the positive terminal of the first resistor R1 is connected to the positive terminal of the second resistor R2, simultaneously to the source of the fourth NMOS transistor NM4, the positive terminal of the third resistor R3, and the positive terminal of the fourth resistor R4; the negative terminal of the fourth resistor R4 is connected to ground; the negative terminal of the second resistor R2 is connected to the base of the second NPN transistor Q5; the emitter of the second NPN transistor Q5 is connected to ground; the collector of the second NPN transistor Q5 is connected to the gate of the fourth NMOS transistor NM4, simultaneously to the drain of the second PMOS transistor PM3, and simultaneously to the cathode of the first diode D2; the drain of the fourth NMOS transistor NM4 is connected to the digital power supply DVDD for internal use generated by stepping down the power supply voltage; the negative terminal of the third resistor R3 is connected to the base of the third NPN transistor Q6; the emitter of the third NPN transistor Q6 is connected to ground; the collector of the third NPN transistor Q6 is connected to the source of the fifth NMOS transistor NM5, simultaneously to the anode of the first diode D2, and simultaneously to the drain of the fifth PMOS transistor PM5;The gate of the fifth PMOS transistor PM5 is connected to the low-voltage bias Vbias2 generated after stepping down the power supply voltage; the source of the fifth PMOS transistor PM5 is connected to the analog power supply AVDD for internal use generated after stepping down the power supply voltage.

[0011] The working principle of the present invention is as follows:

[0012] When the high-side power transistor M0 is turned on, the low-side power transistor M1 is turned off at the same time. The current of the high-side power transistor M0 flows through the load, and the current of the detection power transistor M2 flows through the third PNP transistor Q3 and the third PMOS transistor PM4 and flows through the second diode D3 to the high-precision detection resistor Rsense outside the pin to be converted into a voltage. When the power supply is powered on, the current flows through the fourth PMOS transistor PM1 and is regulated by the first Zener diode to make the gate of the sixth NMOS transistor NM3 reach the conduction turn-on voltage, so that it bears part of the high voltage. The internally generated analog power supply AVDD injects current into the second diode D2, the third NPN transistor Q6, the second NPN transistor Q5, and the fourth NMOS transistor NM4 through the fifth PMOS transistor PM5. When the first NMOS transistor M0 is turned on, the first PNP Q1 is turned on, and the first PMOS transistor PM2 is turned on, mirroring the current to the second PNP Q2 and the second PMOS transistor PM3 respectively. The current flows from the second PNP transistor Q2 to the second PMOS transistor PM3 to the second NPN transistor Q5 to form a path and raises the gate potential of the fourth NMOS transistor NM4 to make it conduct to form a buffer. The first to third NPN transistors Q4-Q6 below form a current source, and their base resistors, the first resistor R1 to the third resistor R3, are all used as base resistors to limit their current to prevent the collector current from being too large due to too large amplification factor. The fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are used as buffers. The ratio of the second PNP transistor Q2 to the third PNP transistor Q3 is 1:2, and the ratio of the second PMOS transistor PM3 to the third PMOS transistor PM4 is 1:2. The current of the detection power transistor, the second NMOS transistor M2, flows through the Q2 path detection and the Q3 path output to the external high-precision detection resistor according to the ratio of 1:2.

Claims

1. A high-side power transistor detection circuit with a bridge drive, characterized in that, It includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PNP transistor, a second PNP transistor, a third PNP transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first Zener diode, a first diode, a second diode, a first NPN transistor, a second NPN transistor, and a third NPN transistor; wherein, the gate of the first NMOS transistor is connected to the high-side power transistor driving circuit; the drain of the first NMOS transistor is connected to the power supply voltage VS; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the low-side power transistor driving circuit; the source of the third NMOS transistor is connected to the ground; the source of the second NMOS transistor is connected to the power supply voltage VS; the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor; the source of the second NMOS transistor is connected to the emitters of the second PNP transistor and the third PNP transistor; the emitter of the first PNP transistor is connected to the source of the first NMOS transistor, and the base and collector of the first PNP transistor are connected to the source of the first PMOS transistor; the base of the second PNP transistor is connected to the base of the first PNP transistor and the base of the third PNP transistor, the collector of the second PNP transistor is connected to the source of the second PMOS transistor, and the collector of the third PNP transistor is connected to the source of the third PMOS transistor; the gate of the first PMOS transistor is connected to its drain to form a diode connection; the gates of the second PMOS transistor and the third PMOS transistor are connected to the gate of the first PMOS transistor; the drain of the third PMOS transistor is connected to the anode of the third diode; the cathode of the third diode is connected to the output pin; the drain of the first PMOS transistor is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the drain of the fourth PMOS transistor and at the same time connected to the cathode of the first Zener diode; the gate of the fourth PMOS transistor is connected to a bias voltage generated internally by the power supply voltage; the source of the fourth PMOS transistor is connected to the power supply voltage; the anode of the first Zener diode is connected to the ground; the source of the sixth NMOS transistor is connected to the collector of the first NPN transistor; the base of the first NPN transistor is connected to one end of the first resistor; the emitter of the first NPN transistor is connected to the ground; the other end of the first resistor is connected to one end of the second resistor and at the same time connected to the source terminal of the fourth NMOS transistor, one end of the third resistor, and one end of the fourth resistor; the other end of the fourth resistor is connected to the ground; the other end of the second resistor is connected to the base of the second NPN transistor; the emitter of the second NPN transistor is connected to the ground; the collector of the second NPN transistor is connected to the gate of the fourth NMOS transistor and at the same time connected to the drain of the second PMOS transistor and at the same time connected to the cathode of the first diode; the drain of the fourth NMOS transistor is connected to the digital power supply DVDD for internal use generated by stepping down the power supply voltage.The other end of the third resistor is connected to the base of the third NPN transistor; the emitter of the third NPN transistor is connected to the ground; the collector of the third NPN transistor is connected to the source of the fifth NMOS transistor and is also connected to the anode of the first diode and the drain of the fifth PMOS transistor; the gate of the fifth PMOS transistor is connected to a low-voltage bias generated by stepping down the power supply voltage; the source of the fifth PMOS transistor is connected to an internal analog power supply AVDD generated by stepping down the power supply voltage.

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