Satellite navigation signal carrier loop tracking method, device, medium and equipment

Abstract

The application provides a satellite navigation signal carrier loop tracking method, device, medium and equipment, and relates to the technical field of satellite communication. In the phase detection processing of carrier tracking in the method, the sign bit is extracted in advance, and then the phase is obtained by absolute value. Compared with the prior art of directly performing phase detection processing on the to-be-detected signal, the technical solution provided by the application can improve the operation efficiency and reduce the operation time while ensuring the phase detection accuracy without considering the judgment of the sign bit.

Description

Technical Field

[0001] This application relates to the field of satellite communication technology, specifically to a carrier loop tracking method, apparatus, medium, and device for satellite navigation signals. Background Technology

[0002] With the development of science and technology and my country's satellite navigation industry, the functional requirements for various aerospace vehicles such as satellites and spacecraft are becoming increasingly higher. High-speed data transmission and processing technology is an indispensable part. Among them, high-speed modulation and demodulation technology is the core technology of high-speed data transmission system. To achieve correct demodulation of high-speed data, it largely depends on correct code synchronization and carrier loop tracking. In long-distance carrier loop tracking technology, the carrier loop tracking method used by direct-sequence spread spectrum receivers is phase-locked loop. A typical phase-locked loop design structure includes a phase discriminator, a loop filter, and a digitally controlled oscillator. However, due to the long transmission distance, the signal power received at the receiving end is very low, which increases the difficulty of identifying the phase difference during carrier loop tracking. Under the condition of a very low signal-to-noise ratio (SNR), the carrier loop tracking effect is not ideal.

[0003] To address this issue, commonly used phase detector algorithms in existing phase-locked loops include the method of multiplying the amplitude of the I-channel output by the amplitude of the Q-channel output, and the maximum likelihood estimation algorithm. The former has lower computational requirements and shorter computation time, but the phase rotation slope is proportional to the signal amplitude, achieving near-optimal phase detection performance at high SNR, but poor performance at low SNR. The latter uses the four-quadrant arctangent as its phase detection principle, and the resulting phase rotation slope is independent of the signal amplitude, maintaining optimal phase detection performance at both high and low SNR. However, this algorithm requires determining the rotation direction of the ideal point and the measurement point, resulting in higher computational requirements and longer computation time.

[0004] Therefore, for carrier tracking based on phase-locked loops under low signal-to-noise ratio, it is difficult to simultaneously meet the requirements of good phase detection performance and short computation time. Summary of the Invention

[0005] This application provides a carrier loop tracking method, apparatus, medium, and device for satellite navigation signals, which combines good phase detection and short computation time when performing carrier loop tracking under low signal-to-noise ratio conditions.

[0006] In a first aspect, this application provides a carrier loop tracking method for satellite navigation signals, the method comprising:

[0007] The input signal is demodulated to obtain the first in-phase signal and the first quadrature signal;

[0008] The output signal of the numerically controlled oscillator is processed by SIN / COS mapping to obtain a second in-phase signal and a second quadrature signal; the first in-phase signal and the second in-phase signal are multiplied to obtain a first phase detection signal; the first quadrature signal and the second quadrature signal are multiplied to obtain a second phase detection signal.

[0009] Extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal;

[0010] Obtain the absolute value of the phase amplitude of the first phase-detecting signal and the absolute value of the phase amplitude of the second phase-detecting signal; calculate the phase difference measurement result between the input signal and the output signal using the phase detection formula based on the sign bit of the first phase-detecting signal and the corresponding absolute value of the phase amplitude, and the sign bit of the second phase-detecting signal and the corresponding absolute value of the phase amplitude.

[0011] The phase difference measurement result is converted using a calibration factor to obtain the frequency offset measurement result. The value of the calibration factor is an adjustable value.

[0012] The frequency offset measurement results are subjected to second-order loop filtering to obtain an error correction signal;

[0013] The frequency offset of the output signal is adjusted based on the error correction signal until the frequency of the output signal can track and synchronize with the frequency of the input signal.

[0014] By adopting the above technical solution, the symbol bit is extracted in advance during phase detection processing for carrier tracking, and the phase is then calculated by absolute value. Compared with the existing technology that directly performs phase detection processing on the signal to be detected, since the decision of the symbol bit is not considered, the computational efficiency can be improved and the computation time reduced while ensuring the accuracy of phase detection.

[0015] Optionally, if the input signal is a BPSK signal, the phase detection formula includes:

[0016] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0017] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0018] Among them, ata psThe phase amplitude difference between the BPSK signal and the output signal is given by ATAN, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata represents the value of the phase amplitude difference between the BPSK signal and the output signal, and x represents the value of the phase amplitude difference between the BPSK signal and the output signal. ps The phase difference measurement result between the BPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0019] By adopting the above technical solution, based on the maximum likelihood algorithm, the phase amplitude difference is obtained by using the absolute value of the phase amplitude of the signal to be phased, which can adapt to the phase amplitude difference in each quadrant.

[0020] Optionally, the phase detection formula includes:

[0021] ata ps =Q ps rms(Q ps ) = 1;

[0022] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0023] Among them, Q ps The second phase detection signal is rms, which is the root mean square operator.

[0024] By adopting the above technical solution, for a BPSK signal composed of two orthogonal signals with a phase difference of 180°, the frequency deviation is only related to the value of the imaginary part. Therefore, in practical applications, the phase amplitude difference can be determined by the second phase detection signal.

[0025] Optionally, if the input signal is a QPSK signal, the phase detection formula includes:

[0026] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0027] ata2 ps =ATAN(|I ps | / |Q ps|), ata2=[0,π / 2];

[0028] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ), ats = [-π / 2, π / 2];

[0029] Among them, ata ps The phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata is the value of the phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, and ata2 is the value of the phase amplitude difference between the first phase detection signal and the output signal. ps The phase amplitude difference between the other symbol signal of the QPSK signal and the output signal is denoted as x, where ata is the value of the phase amplitude difference between the other symbol signal of the QPSK signal and the output signal. ps The phase difference measurement result between the QPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0030] By adopting the above technical solution, the sign bit with positive and negative signs is extracted. Since there is no influence of positive and negative signs in the calculation of the arctangent function of ATAN, the calculation range can be narrowed, making the calculated phase difference measurement results simpler and more stable.

[0031] Optionally, the phase detection formula includes:

[0032] ata ps =Q ps rms(Q ps ) = 1;

[0033] ata2 ps =I ps ,rms(I ps ) = 1;

[0034] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps), ats = [-π / 2, π / 2];

[0035] Among them, Q ps The second phase detection signal, I ps The first phase detection signal is denoted as rms, which is the root mean square operator.

[0036] By adopting the above technical solution, for a QPSK signal mapped by two consecutive binary bits, the frequency offset is determined simultaneously by the two phase detection signals. The sign of the frequency offset is determined by the actual sign bit. Only the phase amplitude difference at the absolute value level is calculated, which can eliminate the problem of phase ambiguity and reduce the computational complexity.

[0037] Optionally, the scaling factor includes:

[0038] KD=2^N2, N2=[1, 2, 3,...,16];

[0039] Where KD is the scaling factor and N2 is the value of the multiplier that performs the shift operation.

[0040] By adopting the above technical solution, since the phase difference is caused by frequency offset, the phase difference at the angle level is converted into a frequency offset at the frequency level through the shift operation of the multiplier. This not only saves multiplier resources but also facilitates subsequent filtering.

[0041] Optionally, the step of performing second-order loop filtering on the frequency offset measurement result to obtain the error correction signal includes:

[0042] Determine whether the frequency offset of the frequency offset measurement result is less than the set threshold, and select a second-order loop filter with the appropriate structure based on the determination result.

[0043] By adopting the above technical solution, the appropriate second-order loop filter structure can be adaptively selected based on different frequency offset magnitudes, enabling fast and accurate frequency offset measurement, and simultaneously adapting to frequency offset measurement results with both large and small frequency offsets.

[0044] Optionally, determining whether the frequency offset of the frequency offset measurement result is less than a set threshold, and selecting a second-order loop filter with a corresponding structure based on the determination result, includes:

[0045] If the frequency offset of the frequency offset measurement result is less than the set threshold, then the second-order loop filter of the first structure is selected.

[0046] The structural formula of the second-order loop filter of the first structure is:

[0047]

[0048] Among them, y psThe error correction signal is given by c1 and c2, which are the parameters of the second-order loop filter in the first structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the first structure, and τ1 and τ2 are time constants.

[0049] By adopting the above technical solution, for frequency offset measurement results with small frequency offset, the second-order loop filter of the first structure can shorten the tracking time and reduce carrier reference phase jitter.

[0050] Optionally, determining whether the frequency offset of the frequency offset measurement result is less than a set threshold, and selecting a second-order loop filter with a corresponding structure based on the determination result, includes:

[0051] If the frequency offset of the frequency offset measurement result is greater than or equal to the set threshold, then the second-order loop filter of the second structure is selected.

[0052] The structural formula of the second-order loop filter is as follows:

[0053]

[0054] Among them, y ps The error correction signal is given, and c1 and c2 are the parameters of the second-order loop filter in the second structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the second structure, and τ1 and τ2 are time constants.

[0055] By adopting the above technical solution, for frequency deviation measurement results with large frequency deviation, the second-order loop filter with the second structure has good noise immunity and good steady-state tracking capability.

[0056] Secondly, this application provides a carrier loop tracking device for satellite navigation signals, the device comprising: an input signal processing module for demodulating the input signal to obtain a first in-phase signal and a first quadrature signal;

[0057] The output signal mapping module is used to perform SIN / COS mapping processing on the output signal of the numerically controlled oscillator to obtain the second in-phase signal and the second quadrature signal.

[0058] The mixing module is used to multiply the first in-phase signal and the second in-phase signal to obtain the first phase detection signal, and to multiply the first quadrature signal and the second quadrature signal to obtain the second phase detection signal.

[0059] The quadrant extraction module is used to extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal; the phase amplitude acquisition module is used to acquire the absolute value of the phase amplitude of the first phase detection signal and the absolute value of the phase amplitude of the second phase detection signal.

[0060] The phase difference calculation module is used to calculate the phase difference measurement result between the input signal and the output signal based on the absolute value of the sign bit and the corresponding phase amplitude of the first phase detection signal and the absolute value of the sign bit and the corresponding phase amplitude of the second phase detection signal, using a phase detection formula.

[0061] The phase difference conversion module is used to convert the phase difference measurement result using a calibration factor to obtain the frequency offset measurement result. The value of the calibration factor is an adjustable value.

[0062] The loop filtering module is used to perform second-order loop filtering on the frequency offset measurement results to obtain an error correction signal;

[0063] The frequency offset adjustment module is used to adjust the frequency offset of the output signal based on the error correction signal until the frequency of the output signal can be synchronously tracked with the frequency of the input signal.

[0064] Thirdly, this application provides a computer-readable storage medium storing a plurality of instructions adapted for loading by a processor and executing any of the methods described above.

[0065] Fourthly, this application provides an electronic device including a processor, a memory, and a transceiver, wherein the memory is used to store instructions, the transceiver is used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform any of the methods described above.

[0066] In summary, one or more technical solutions provided in the embodiments of this application have the following technical effects or advantages: when performing phase detection processing for carrier tracking, the symbol bit is extracted in advance, and then the phase is obtained by absolute value. Compared with the prior art of directly performing phase detection processing on the signal to be detected, since the decision problem of the symbol bit is not considered, the operation efficiency can be improved and the operation time can be reduced while ensuring the accuracy of phase detection. Attached Figure Description

[0067] Figure 1 This is a schematic diagram of the basic structure of a phase-locked loop in the prior art;

[0068] Figure 2 This is a schematic diagram of the structure of a Costas ring in the prior art;

[0069] Figure 3 This is a schematic diagram of the structure of a phase detection algorithm in the prior art;

[0070] Figure 4 This is a schematic diagram illustrating the phase detection characteristics of a phase detection algorithm provided in an embodiment of this application;

[0071] Figure 5 This is a schematic flowchart of a carrier loop tracking method for satellite navigation signals provided in an embodiment of this application;

[0072] Figure 6 This is an example phasor diagram of a locked state provided in an embodiment of this application;

[0073] Figure 7 This is a phasor diagram of an exemplary BPSK signal in a pull-in state provided in an embodiment of this application;

[0074] Figure 8 This application provides a phasor diagram for QPSK signal phase rotation.

[0075] Figure 9 This is a schematic diagram of a BPSK / QPSK adjusted signal carrier Costas loop filter provided in an embodiment of this application;

[0076] Figure 10 This is a schematic diagram of the first structure of a second-order loop filter provided in an embodiment of this application;

[0077] Figure 11 This is a simulation diagram of a second-order loop filter with a first structure provided in this application under small frequency offset conditions.

[0078] Figure 12 This is a simulation diagram of a second-order loop filter with a first structure provided in this application embodiment, showing filtering under large frequency offset conditions;

[0079] Figure 13 This is a schematic diagram of the second structure of a second-order loop filter provided in an embodiment of this application;

[0080] Figure 14 This is a simulation diagram of a second-order loop filter with a second structure provided in this application under small frequency offset conditions.

[0081] Figure 15 This is a simulation diagram of a second-order loop filter with a second structure provided in this application embodiment, demonstrating filtering under large frequency offset conditions;

[0082] Figure 16 This is a diagram of the internal structure of a DDS provided in an embodiment of this application;

[0083] Figure 17This application provides a constellation diagram for demodulation under low SNR.

[0084] Figure 18 This is a frequency offset measurement diagram for demodulation under low SNR provided in an embodiment of this application;

[0085] Figure 19 This is a schematic diagram of the structure of a carrier loop tracking device for satellite navigation signals provided in an embodiment of this application;

[0086] Figure 20 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of this application.

[0087] Explanation of reference numerals in the attached diagram: 10, Input signal modulation module; 20, Output signal mapping module; 30, Mixing module; 40, Quadrant extraction module; 50, Phase amplitude acquisition module; 60, Phase difference calculation module; 70, Phase difference conversion module; 80, Loop filtering module; 90, Frequency offset adjustment module; 2000, Electronic device; 2001, Processor; 2002, Communication bus; 2003, User interface; 2004, Network interface; 2005, Memory. Detailed Implementation

[0088] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0089] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0090] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0091] The technical solution provided in this application can be applied to carrier tracking scenarios for phase-locked loops.

[0092] Please see Figure 1 This is a schematic diagram of the basic structure of a phase-locked loop (PLL) in the prior art. A PLL is an electronic control loop that generates and outputs periodic signals. By continuously adjusting the phase of the output signal, it keeps the phase between the output signal and the input signal consistent at all times. When the phases of the input signal and the output signal are basically consistent, the PLL enters a locked state, exhibiting steady-state characteristics. When the phases of the input signal and the output signal have not yet reached consistency but are approaching consistency, the PLL operates in a pulled-in state, exhibiting transient characteristics.

[0093] In the diagram, the input signal is multiplied by the output signal of the voltage-controlled oscillator (VCO). The phase is then detected by a phase detector, and the resulting phase detection signal is filtered out by a loop filter to remove high-frequency multiplication and noise. The output signal serves as the control voltage (current) signal for the VCO, causing it to output a periodic oscillation signal at a certain frequency. The purpose of the phase-locked loop (PLL) is to repeatedly identify the phase difference between the input and output signals and adjust the frequency of the output signal accordingly, thereby ultimately ensuring that the phase of the output signal is consistent with the phase of the input signal.

[0094] Please see Figure 2 This is a schematic diagram of a Costas ring in the prior art. The Costas ring uses the working principle of a phase-locked loop. The input signal is multiplied with two local carrier signals that are orthogonal in phase for phase detection. The output is sent to the phase detector after passing through a low-pass filter to obtain an error signal. After the error signal is filtered by the loop, the numerical control device generates an output signal. The output signal is multiplied with the input signal to form the Costas ring. The tracking speed and tracking accuracy of the Costas ring are greatly affected by the phase detection algorithm.

[0095] Please see Figure 3 This is a schematic diagram of a phase detection algorithm in the prior art. The phase detection algorithm consists of a sign function (Sign(*)) and a multiplier. Its phase detection characteristic equation is:

[0096] θ(k)=Sign[I(k)]×Q(k)=Sign(cosθ)·sinθ;

[0097] The sign function is: The phase detection algorithm using direct multiplication has a slope that is proportional to the signal amplitude during phase detection, and the issue of phase sign must also be considered.

[0098] Please see Figure 4The diagram above illustrates the phase detection characteristics of the phase detection algorithm. The structure using direct amplitude multiplication has a sawtooth phase detection characteristic, which has a good phase detection effect under high SNR, but the phase detection effect is poor in actual satellite communication, which is mostly under low SNR.

[0099] Please refer to Table 1, which lists several phase detection algorithms in the prior art and their corresponding output phase errors and characteristics. It can be seen that the phase detection algorithms in the prior art are difficult to balance the requirements of good tracking performance and low computational load under low SNR.

[0100] Table 1 Output error and characteristics of commonly used phase-locked loop (PLL) discriminators

[0101]

[0102]

[0103] Based on the above problems, the embodiments of this application improve the phase detection and loop filtering on the basis of the Costas loop, which can shorten the tracking time and improve the tracking accuracy.

[0104] Please see Figure 5 This is a flowchart illustrating a carrier loop tracking method for satellite navigation signals provided in an embodiment of this application. This method can be implemented using a computer program, a microcontroller, or run on a carrier loop tracking device for satellite navigation signals based on the von Neumann architecture. The computer program can be integrated into an application or run as a standalone utility application. This embodiment uses the carrier signal receiver as an example to describe the specific steps of the carrier loop tracking method in detail.

[0105] Step S101: Demodulate the input signal to obtain the first in-phase signal and the first quadrature signal.

[0106] The first in-phase signal is the I-channel (in-phase) signal of the input signal, and the first quadrature signal is the Q-channel (quadrature) signal of the input signal. In one embodiment, the input signal is a real number signal. The input signal is quadrature demodulated, and then filtered to obtain I / Q outputs. The specific demodulation method is related to the modulation method of the input signal at the transmitting end.

[0107] In another embodiment, if the input signal is a complex signal, then the input signal is mixed in subsequent processing.

[0108] Step S102: Perform SIN / COS mapping processing on the output signal of the numerically controlled oscillator to obtain the second in-phase signal and the second quadrature signal.

[0109] SIN / COS mapping is used to reproduce the output signal of the numerically controlled oscillator. Assuming the phase-locked loop is in a locked state, the reproduced ideal sine function is in phase with the input satellite signal, and the reproduced ideal cosine function is 90° out of phase with the input signal of the satellite carrier frequency. That is, the second in-phase signal and the second quadrature signal obtained after mapping the local signal output of the numerically controlled oscillator are 90° out of phase. The second in-phase signal is the I-channel signal, and the second quadrature signal is the Q-channel signal.

[0110] Step S103: Multiply the first in-phase signal and the second in-phase signal to obtain the first phase detection signal, and multiply the first quadrature signal and the second quadrature signal to obtain the second phase detection signal.

[0111] The second in-phase signal and the second quadrature signal are essentially copies of two sine and cosine carrier signals with a 90° phase difference. The copying objects are the first in-phase signal and the first quadrature signal. The input signal is multiplied by the copied carrier on the I-path (in-phase) and Q-path (quadrature) respectively, that is, the mixing process is performed to obtain the first phase detection signal and the second phase detection signal respectively. In practice, two multipliers can be used to achieve this, which facilitates the subsequent calculation of the phase difference between the input signal and the output signal.

[0112] Step S104: Extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal.

[0113] Use the `sign` function in MATLAB to extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal. The `sign` function returns the sign of a number; it returns 1 when the value is positive or crosses zero, and -1 when it is negative.

[0114] Step S105: Obtain the absolute value of the phase amplitude of the first phase detection signal and the absolute value of the phase amplitude of the second phase detection signal.

[0115] The first phase detection signal is an I-channel (in-phase) signal, and the second phase detection signal is a Q-channel (quadrature) signal. The absolute value of the phase amplitude is the magnitude of the phase amplitude of the two I / Q signals at the same sampling time. Using the absolute value can eliminate the influence of the sign bit. Since the initial phase of the input signal carrier is unknown, the demodulated data has a 180° phase ambiguity problem. Therefore, using the absolute value of the phase amplitude can eliminate the influence of the positive or negative sign of the phase sign bit and eliminate the phase ambiguity problem.

[0116] Step S106: Based on the absolute value of the sign bit and corresponding phase amplitude of the first phase detection signal and the absolute value of the sign bit and corresponding phase amplitude of the second phase detection signal, the phase difference measurement result between the input signal and the output signal is calculated using the phase detection formula.

[0117] Step S106A, if the input signal is a BPSK signal, the phase detection formula includes:

[0118] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0119] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0120] Among them, ata ps The phase amplitude difference between the BPSK signal and the output signal is given by ATAN, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata represents the value of the phase amplitude difference between the BPSK signal and the output signal, and x represents the value of the phase amplitude difference between the BPSK signal and the output signal. ps The phase difference measurement result between the BPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0121] In the above calculation, the phase angle of the complex vector synthesized from the first phase-detecting signal and the second phase-detecting signal is equal to the phase difference between the input signal and the output signal. By comparing Q at a certain moment ps with I ps Then, the phase difference at this moment is calculated using the arctangent function. Right now

[0122]

[0123] The angle value returned by the arctangent function in the second quadrant is between -π / 2 and π / 2, but the phase of the I / Q signal at a certain moment has a positive and negative difference, making it difficult to determine the direction of the frequency offset that causes the phase difference.

[0124] Using the tangent operator in MATLAB, the tangent value of the input can be returned, since |Q ps | / |I ps| is a real number, and the returned value is a value in the interval [-π / 2, π / 2]. Since the BPSK signal has only two clusters of measurement points in the constellation diagram, the phase amplitude difference between the returned BPSK signal and the output signal is between [0, π / 2].

[0125] After calculating the phase amplitude difference, the phase difference measurement result is obtained based on the sign bit of the first phase detection signal and the sign bit of the second phase detection signal.

[0126] In one feasible implementation, the phase detection formula includes:

[0127] ata ps =Q ps rms(Q ps ) = 1;

[0128] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0129] Among them, Q ps The second phase detection signal is rms, which is the root mean square operator.

[0130] When the phase-locked loop (PLL) enters the locked state, its steady-state characteristic is that the phase difference measurement result fluctuates around the zero and negative poles. At this time, the first phase detection signal contains the input signal and some noise, while the second phase detection signal is basically noise. The data of the first and second phase detection signals are marked on the phasor diagram. Please refer to [link to relevant documentation]. Figure 6 This is an example phasor diagram of a locked state provided in an embodiment of this application. The distribution of measurement points at multiple times is such that about half of the data is concentrated on the positive I-axis and the other half is concentrated on the negative I-axis. The distribution of measurement points at this time is an ideal point.

[0131] When the phase-locked loop is operating in the pulled-in state, please refer to Figure 7 This is an exemplary phasor diagram of a BPSK signal in a pulled-in state provided in this application embodiment. The directed line from the origin to the measurement point represents the actual phase deflection magnitude, and the angle of rotation of the I-axis to the directed line represents the phase difference measurement result. Alternatively, the outward directed line connecting the two measurement points can be used as the actual phase deflection magnitude. As can be seen from the figure, the phase adjustment range of the phase difference measurement result is [-π / 2, π / 2]. The rotation between the directed line and the I-axis can be simplified to using the second phase detection signal to calculate the phase difference measurement result.

[0132] When using the second phase detection signal (imaginary part) for calculation, for multiple measurement points sampled, the root mean square is used to limit the second phase detection signal, which can obtain an accurate directed connection, thereby enabling accurate calculation of the phase difference measurement result.

[0133] Step S106B, if the input signal is a QPSK signal, the phase detection formula includes:

[0134] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0135] ata2 ps =ATAN(|I ps | / |Q ps |), ata2=[0,π / 2];

[0136] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ), ats = [-π / 2, π / 2];

[0137] Among them, ata ps The phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata is the value of the phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, and ata2 is the value of the phase amplitude difference between the first phase detection signal and the output signal. ps The phase amplitude difference between the other symbol signal of the QPSK signal and the output signal is denoted as x, where ata is the value of the phase amplitude difference between the other symbol signal of the QPSK signal and the output signal. ps The phase difference measurement result between the QPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0138] Please see Figure 8This application provides a phasor diagram for QPSK signal phase rotation. Since the phase adjustment range of the directed connection represented by the measurement point is [-π / 2, π / 2], there are only two rotations less than π / 2: clockwise and counterclockwise. The phase angles of the four ideal points in the diagram are -3π / 4, -π / 4, π / 4, and 3π / 4, respectively. Since the QPSK signal is a quaternary phase shift keying signal, the data points correspond to four clusters of measurement points with corresponding rotation angles. The four cases in the diagram can actually be divided into two rotation cases. For example, the upper left-1 and upper right-1 in the diagram are actually clockwise rotations, indicating that the frequency offsets are both negative. The only difference is the selected measurement points. The upper left-1 measurement point is the corresponding measurement point in the first and third quadrants, and the upper right-1 measurement point is the measurement point in the second and fourth quadrants. The magnitude and direction of the measured phase difference are the same, only the values ​​are different. Therefore, in one feasible implementation, another calculation method can be used to verify the phase difference measurement results.

[0139] Phase detection formulas include:

[0140] ata ps =Q ps rms(Q ps ) = 1;

[0141] ata2 ps =I ps ,rms(I ps ) = 1;

[0142] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ), ats = [-π / 2, π / 2];

[0143] Among them, Q ps The second phase detection signal, I ps The first phase detection signal is denoted as rms, which is the root mean square operator.

[0144] Please see Figure 8 The directed line connecting the points in the upper left (-1) is in the first and third quadrants. Compared to ideal points in the first and third quadrants, the slope of the directed line is between [0, π / 4]. Therefore, the absolute value of I at the measurement point is greater than the absolute value of Q. If the signs of I and Q are introduced, the calculation in the third quadrant needs to consider the signs first and then determine the direction of rotation. Therefore, extracting the absolute value can reduce the amount of calculation. Since the sign bits of the first and third phase detection signals are both positive or both negative, the result of multiplication is always positive. Therefore, the phase difference measurement result calculated using the measurement points in the first and third quadrants is Q. ps -I ps(Q ps ps Similarly, the measurement point at the lower left (-2) also falls within the first and third quadrants, but the absolute value of I at the measurement point is less than the absolute value of Q. Therefore, the measurement result is Q. ps -I ps (Q ps >I ps In the figure, the measurement points at upper right -1 and lower right -2 are located in the second and fourth quadrants. The result of multiplying the sign bits is negative, and the calculated phase difference measurement result is -(Q). ps -I ps ).

[0145] Meanwhile, by limiting the values ​​of the first and second phase detection signals by the root mean square (RMS) value, the calculated phase difference measurement results can meet the accuracy requirements.

[0146] Step S107: The phase difference measurement result is converted using a calibration factor to obtain the frequency offset measurement result. The calibration factor is an adjustable value.

[0147] The calibration factor is the value used for shifting operations. In one round of phase-locked loop calculation, the value of the calibration factor remains unchanged until the phase result is converted into the frequency result after the next round of phase detection, at which point the corresponding value of the calibration factor changes according to the phase difference measurement result.

[0148] In one feasible implementation, to save multiplier resources, the scaling factor includes: KD = 2^N2, N2 = [1, 2, 3, ..., 16];

[0149] Where KD is the scaling factor and N2 is the value of the multiplier that performs the shift operation.

[0150] For example, with default values ​​N2=14 and KD=16384, the angle can be changed to a value with frequency correction through a shift operation, unaffected by other factors.

[0151] Step S108: Perform second-order loop filtering on the frequency offset measurement results to obtain the error correction signal.

[0152] The second-order loop filter is used to filter out rapidly changing phase errors caused by noise in the input signal and to smooth the high-frequency components of the phase detector, so that the original signal can be accurately estimated at the output of the subsequent second-order loop filter. The error correction signal is the signal after the second-order loop filter, which enables the numerically controlled oscillator to adjust the frequency of the output signal accordingly based on the error correction signal, so that the output signal can track the input signal and the phase-locked loop can enter the locked state.

[0153] ​Step S109: Adjust the frequency offset of the output signal based on the error correction signal until the frequency of the output signal can track and synchronize with the frequency of the input signal.

[0154] Frequency offset adjustment is the process by which a numerically controlled oscillator adjusts the generated sine or cosine output signal based on the frequency offset measured by the error correction signal, thereby enabling frequency tracking between the output and input signals.

[0155] In another embodiment of the satellite navigation signal carrier loop tracking method of this application, the steps are described in detail: the second-order loop filter can adaptively select the IIR filter structure, which can achieve faster and more accurate tracking under both large and small frequency offset conditions.

[0156] Please see Figure 9 This is a schematic diagram of a BPSK / QPSK signal carrier Costas loop filter provided in an embodiment of this application. The diagram illustrates the specific process of phase-locked loop tracking. The I / Q signals of the input signal are multiplied by the SIN / COS signals of the output signal of the carrier NCO, respectively. Phase detection is then performed according to the signal modulation method. The phase offset error of the phase difference measurement result is then converted into the frequency offset error of the frequency offset measurement result. After second-order loop IIR filtering, the carrier NCO is controlled to adjust the frequency of the output signal so that the carrier loop can achieve frequency tracking of the input signal.

[0157] Step S201: Demodulate the input signal to obtain the first in-phase signal and the first quadrature signal.

[0158] Step S202: Perform SIN / COS mapping processing on the output signal of the numerically controlled oscillator to obtain the second in-phase signal and the second quadrature signal.

[0159] Step S203: Multiply the first in-phase signal and the second in-phase signal to obtain the first phase detection signal, and multiply the first quadrature signal and the second quadrature signal to obtain the second phase detection signal.

[0160] Step S204: Extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal.

[0161] Step S205: Obtain the absolute value of the phase amplitude of the first phase detection signal and the absolute value of the phase amplitude of the second phase detection signal.

[0162] Step S206: Based on the absolute value of the sign bit and corresponding phase amplitude of the first phase detection signal and the absolute value of the sign bit and corresponding phase amplitude of the second phase detection signal, the phase difference measurement result between the input signal and the output signal is calculated using the phase detection formula.

[0163] Step S207: The phase difference measurement result is converted using a calibration factor to obtain the frequency offset measurement result. The calibration factor is an adjustable value.

[0164] Steps S201 to S207 have been described in detail in the above embodiments and will not be repeated here.

[0165] Step S208: Perform second-order loop filtering on the frequency offset measurement results to obtain the error correction signal.

[0166] In one feasible implementation, it is determined whether the frequency offset of the frequency offset measurement result is less than a set threshold, and a second-order loop filter with the appropriate structure is selected based on the determination result.

[0167] The frequency offset range of the system can be roughly estimated during reception. For example, the maximum operating speed of the main body and the performance of the crystal oscillator determine the magnitude of the frequency offset after the system starts operating. Therefore, the frequency offset can be roughly estimated before the communication system starts operating.

[0168] In one feasible implementation, when the system chip rate fc is greater than 256Kpc, the set threshold is set to 6kHz, the frequency offset deft greater than or equal to 6kHz is determined as a large frequency offset, and the frequency offset deft less than 6kHz is determined as a small frequency offset.

[0169] In practice, the threshold settings vary between different systems. The threshold setting can be determined based on the calculation results of detf / fc. The larger the calculation result, the greater the frequency deviation.

[0170] Step S208A: If the frequency offset of the frequency offset measurement result is less than the set threshold, then select the second-order loop filter of the first structure.

[0171] The structural formula of the second-order loop filter of the first structure is:

[0172]

[0173] Among them, y ps The error correction signal is given by c1 and c2, which are the parameters of the second-order loop filter in the first structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the first structure, and τ1 and τ2 are time constants.

[0174] Please see Figure 10This is a schematic diagram of the first structure of a second-order loop filter provided in an embodiment of this application. It consists of an accumulator, two adders, and two multipliers that multiply coefficients. The specific values ​​of c1 and c2 are preset by the DSP according to different code rates, and can adopt a 1 / 2^N structure. Therefore, it can be implemented by shifting left and right using a shift register. The value range of N is [1, 2, 3, ..., 16], so the value range of c1 and c2 is [1 / 32768, ..., 1 / 4, 1 / 2]. Please refer to [link to relevant documentation]. Figure 11 and Figure 12 The figures show simulation diagrams of the second-order loop filter of the first structure under small and large frequency offset conditions. It can be clearly seen from the figures that the filtering tracking speed of the first structure is significantly better than that of the second structure under small frequency offset conditions. At the same time, the fluctuation amplitude of the frequency after tracking the frequency offset shows that the filtering effect of the first structure is significantly better than that of the second structure under small frequency offset conditions. This verifies that the second-order loop filter of the first structure can achieve faster and more accurate tracking under small frequency offset conditions.

[0175] Step S208B: If the frequency offset of the frequency offset measurement result is greater than or equal to the set threshold, then select the second-order loop filter of the second structure.

[0176] The structural formula of the second-order loop filter of the second structure is:

[0177]

[0178] Among them, y ps The signal is the error correction signal, c1 and c2 are the parameters of the second-order loop filter of the second structure, and x is the error correction signal. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the second structure, and τ1 and τ2 are time constants.

[0179] Please see Figure 13 This is a schematic diagram of the second structure of a second-order loop filter provided in an embodiment of this application. The second-order loop filter adjusts the positional relationship between the unit time delay and the c2 coefficient multiplier, thereby enabling it to adapt to frequency tracking with large frequency offsets. Please refer to [link to relevant documentation]. Figure 14 and Figure 15 These are simulation diagrams of the second-order loop filter of the second structure under small and large frequency offset conditions. From the perspectives of tracking rate and tracking effect, the tracking time for large frequency offset is shorter than that for small frequency offset. Therefore, the second-order loop filter of the second structure has a faster tracking rate under large frequency offset. The frequency fluctuation range after achieving frequency offset tracking with large frequency offset is smaller than that after achieving frequency offset tracking with small frequency offset. Therefore, the second-order loop filter of the second structure has a better tracking effect under large frequency offset.

[0180] Based on the actual tests of the two structural schemes, the second-order loop filter of the first structure is used when the frequency offset is small, while the second-order loop filter of the second structure is used when the frequency offset is large.

[0181] Step S209: Adjust the frequency offset of the output signal based on the error correction signal until the frequency of the output signal can track and synchronize with the frequency of the input signal.

[0182] Please see Figure 16 This is a diagram of the internal structure of a DDS provided in an embodiment of this application. It is implemented using a carrier NCO sampling direct frequency synthesizer (DDS) with a local frequency source. The input signal θ(k) is the phase control signal at the input of the phase control register, and the other is the frequency offset measurement result Δf from the output of the second-order loop filter. k After accumulation, cosθ(n) and sinθ(n) are obtained by looking up the address through the sine and cosine lookup table. This output can provide the digital coherent carrier required for BPSK / QPSK digital quadrature coherent demodulation.

[0183] To verify the demodulation effect of the method provided in this application at low SNR, a low SNR BPSK signal was demodulated. Please refer to [link to relevant documentation]. Figure 17 and Figure 18 When SNR=1dB, the demodulated constellation diagram and frequency offset measurement diagram show that the present application still has a good frequency offset measurement effect under low signal-to-noise ratio.

[0184] The following are embodiments of the apparatus of this application, which can be used to execute the embodiments of the method of this application. For details not disclosed in the embodiments of the apparatus of this application, please refer to the embodiments of the method of this application.

[0185] Please see Figure 19 This illustration shows a schematic diagram of a carrier loop tracking device for satellite navigation signals provided in an exemplary embodiment of this application. The device can be implemented entirely or partially through software, hardware, or a combination of both. The device includes an input signal modulation module 10, an output signal mapping module 20, a mixing module 30, a quadrant extraction module 40, a phase amplitude acquisition module 50, a phase difference calculation module 60, a phase difference conversion module 70, a loop filtering module 80, and a frequency offset adjustment module 90.

[0186] The input signal modulation module 10 is used to demodulate the input signal to obtain a first in-phase signal and a first quadrature signal;

[0187] The output signal mapping module 20 is used to perform SIN / COS mapping processing on the output signal of the numerically controlled oscillator to obtain the second in-phase signal and the second quadrature signal.

[0188] The mixing module 30 is used to multiply the first in-phase signal and the second in-phase signal to obtain the first phase detection signal, and to multiply the first quadrature signal and the second quadrature signal to obtain the second phase detection signal.

[0189] Quadrant extraction module 40 is used to extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal;

[0190] The phase amplitude acquisition module 50 is used to acquire the absolute value of the phase amplitude of the first phase detection signal and the absolute value of the phase amplitude of the second phase detection signal.

[0191] The phase difference calculation module 60 is used to calculate the phase difference measurement result between the input signal and the output signal based on the absolute value of the sign bit and the corresponding phase amplitude of the first phase detection signal and the absolute value of the sign bit and the corresponding phase amplitude of the second phase detection signal, using a phase detection formula.

[0192] The phase difference conversion module 70 is used to convert the phase difference measurement results using a calibration factor to obtain the frequency offset measurement results. The calibration factor is an adjustable value.

[0193] The loop filter module 80 is used to perform second-order loop filtering on the frequency offset measurement results to obtain the error correction signal;

[0194] The frequency offset adjustment module 90 is used to adjust the frequency offset of the output signal based on the error correction signal until the frequency of the output signal can be synchronously tracked with the frequency of the input signal.

[0195] Optionally, the phase difference calculation module 60 may also include a BPSK phase detection unit, a first simplified unit, a QPSK phase detection unit, and a second simplified unit.

[0196] The BPSK phase detector unit is used to determine the phase detection formula if the input signal is a BPSK signal.

[0197] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0198] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0199] Among them, ata ps The phase amplitude difference between the BPSK signal and the output signal is represented by ATAN, which is the inverse shear value operator. ps| is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase-detector signal, ata represents the value of the phase amplitude difference between the BPSK signal and the output signal, and x represents the value of the phase amplitude difference between the two signals. ps The phase difference measurement result between the BPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0200] The first simplified unit, used in the phase detection formula, includes:

[0201] ata ps =Q ps rms(Q ps ) = 1;

[0202] x ps =Sign(I ps )·Sign(Q ps )·ata ps , ats = [-π / 2, π / 2];

[0203] Among them, Q ps The second phase detection signal is rms, which is the root mean square operator.

[0204] The QPSK phase detector unit, used to detect phases when the input signal is a QPSK signal, includes the following formulas:

[0205] ata ps =ATAN(|Q ps | / |I ps |), ata = [0, π / 2];

[0206] ata2 ps =ATAN(|I ps | / |Q ps |), ata2=[0,π / 2];

[0207] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ), ats = [-π / 2, π / 2];

[0208] Among them, ata ps The phase amplitude difference between one of the symbol signals and the output signal in a QPSK signal, where ATAN is the inverse shear value operator, |Q ps| is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata is the value of the phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, and ata2 is the value of the phase amplitude difference between the first symbol signal and the output signal. ps x represents the phase amplitude difference between the other symbol signal and the output signal in the QPSK signal. ata is the value of this phase amplitude difference between the other symbol signal and the output signal in the QPSK signal. ps The phase difference measurement result between the QPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

[0209] The second simplified unit, used for the phase detection formula, includes:

[0210] ata ps =Q ps rms(Q ps ) = 1;

[0211] ata2 ps =I ps ,rms(I ps ) = 1;

[0212] x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ), ats = [-π / 2, π / 2];

[0213] Among them, Q ps The second phase detection signal, I ps is the first phase detection signal, and rms is the root mean square operator.

[0214] Optionally, the phase difference conversion module 70 may also include a scaling factor conversion unit.

[0215] The scaling factor conversion unit is used to convert scaling factors, including:

[0216] KD=2^N2, N2=[1, 2, 3,...,16];

[0217] Where KD is the scaling factor and N2 is the value of the multiplier that performs the shift operation.

[0218] Optionally, the loop filter module 80 may also include a frequency offset judgment unit, a small frequency offset filter unit, and a large frequency offset filter unit.

[0219] The frequency offset judgment unit is used to determine whether the frequency offset of the frequency offset measurement result is less than the set threshold, and selects a second-order loop filter with the appropriate structure based on the judgment result.

[0220] The small frequency offset filtering unit is used to select the second-order loop filter of the first structure if the frequency offset of the frequency offset measurement result is less than the set threshold.

[0221] The structural formula of the second-order loop filter of the first structure is:

[0222]

[0223] Among them, y ps The error correction signal is given by c1 and c2, which are the parameters of the second-order loop filter in the first structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the first structure, and τ1 and τ2 are time constants.

[0224] The large frequency offset filtering unit is used to select a second-order loop filter with the second structure if the frequency offset of the frequency offset measurement result is greater than or equal to the set threshold.

[0225] The structural formula of the second-order loop filter of the second structure is:

[0226]

[0227] Among them, y ps The signal is the error correction signal, c1 and c2 are the parameters of the second-order loop filter of the second structure, and x is the error correction signal. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the second structure, and τ1 and τ2 are time constants.

[0228] It should be noted that the above embodiments of the apparatus are only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided above belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0229] This application also provides a computer storage medium that can store multiple instructions, which are adapted to be loaded and executed by a processor as described above. Figures 1-19 The carrier loop tracking method for satellite navigation signals described in the illustrated embodiment can be further explained in the following steps: Figures 1-19 The specific details of the illustrated embodiments will not be elaborated here.

[0230] This application also discloses an electronic device. (See reference...) Figure 20 , Figure 20 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of this application. The electronic device 2000 may include: at least one processor 2001, at least one network interface 2004, a user interface 2003, a memory 2005, and at least one communication bus 2002.

[0231] The communication bus 2002 is used to realize the connection and communication between these components.

[0232] The user interface 2003 may include a display screen and a camera. Optionally, the user interface 2003 may also include a standard wired interface and a wireless interface.

[0233] The network interface 2004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0234] The processor 2001 may include one or more processing cores. The processor 2001 connects to various parts of the server using various interfaces and lines, and performs various server functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 2005, and by calling data stored in the memory 2005. Optionally, the processor 2001 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 2001 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor 2001.

[0235] The memory 2005 may include random access memory (RAM) or read-only memory. Optionally, the memory 2005 may include a non-transitory computer-readable storage medium. The memory 2005 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 2005 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 2005 may also be at least one storage device located remotely from the aforementioned processor 2001. (Refer to...) Figure 20 The memory 2005, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program for carrier loop tracking of satellite navigation signals.

[0236] exist Figure 20 In the illustrated electronic device 2000, the user interface 2003 is mainly used to provide an input interface for the user and to acquire user input data; while the processor 2001 can be used to call an application program for carrier loop tracking of a satellite navigation signal stored in the memory 2005. When executed by one or more processors 2001, the electronic device 2000 performs one or more of the methods described in the above embodiments. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0237] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0238] In the various embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some service interface; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0239] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0240] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0241] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0242] The above description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and the disclosure of practical truths.

[0243] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A carrier loop tracking method for satellite navigation signals, characterized in that, The method includes: The input signal is demodulated to obtain the first in-phase signal and the first quadrature signal; The output signal of the numerically controlled oscillator is processed by SIN / COS mapping to obtain the second in-phase signal and the second quadrature signal; The first in-phase signal and the second in-phase signal are multiplied to obtain the first phase detection signal, and the first quadrature signal and the second quadrature signal are multiplied to obtain the second phase detection signal. Extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal; Obtain the absolute value of the phase amplitude of the first phase-detecting signal and the absolute value of the phase amplitude of the second phase-detecting signal; calculate the phase difference measurement result between the input signal and the output signal using the phase detection formula based on the sign bit of the first phase-detecting signal and the corresponding absolute value of the phase amplitude, and the sign bit of the second phase-detecting signal and the corresponding absolute value of the phase amplitude. The phase difference measurement result is converted using a calibration factor to obtain the frequency offset measurement result. The value of the calibration factor is an adjustable value. The frequency offset measurement results are subjected to second-order loop filtering to obtain an error correction signal; The frequency offset of the output signal is adjusted based on the error correction signal until the frequency of the output signal can track and synchronize with the frequency of the input signal.

2. The method according to claim 1, characterized in that, If the input signal is a BPSK signal, the phase detection formula includes: thread ps =ATAN(|Q ps | / |I ps |),ata=[0,π / 2]; x ps =Sign(I ps )·Sign(Q ps )·ata ps ,ats=[-π / 2,π / 2]; Among them, ata ps The phase amplitude difference between the BPSK signal and the output signal is given by ATAN, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata represents the value of the phase amplitude difference between the BPSK signal and the output signal, and x represents the value of the phase amplitude difference between the BPSK signal and the output signal. ps The phase difference measurement result between the BPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

3. The method according to claim 2, characterized in that, The phase detection formula includes: ata ps =Q ps ,rms(Q ps )=1; x ps =Sign(I ps )·Sign(Q ps )·ata ps ,ats=[-π / 2,π / 2]; Among them, Q ps The second phase detection signal is rms, which is the root mean square operator.

4. The method according to claim 1, characterized in that, If the input signal is a QPSK signal, the phase detection formula includes: thread ps =ATAN(|Q ps | / |I ps |),then = [0,π / 2]; ata2 ps =ATAN(|I ps | / |Q ps |),ata2=[0,π / 2]; x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ),ats=[-π / 2,π / 2]; Among them, ata ps The phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, where ATAN is the inverse shear value operator, and |Q ps | is the absolute value of the phase amplitude of the second phase detection signal, |I ps | represents the absolute value of the phase amplitude of the first phase detection signal, ata is the value of the phase amplitude difference between one of the symbol signals of the QPSK signal and the output signal, and ata2 is the value of the phase amplitude difference between the first phase detection signal and the output signal. ps The phase amplitude difference between the other symbol signal of the QPSK signal and the output signal is denoted as x, where ata is the value of the phase amplitude difference between the other symbol signal of the QPSK signal and the output signal. ps The phase difference measurement result between the QPSK signal and the output signal, Sign(I) ps ) represents the sign bit of the first phase detection signal, Sign(Q) ps ) represents the sign bit of the second phase detection signal, and ats represents the phase adjustment range of the phase difference measurement result.

5. The method according to claim 4, characterized in that, The phase detection formula includes: ata ps =Q ps ,rms(Q ps )=1; ata2 ps =I ps ,rms(I ps )=1; x ps =Sign(I ps )·Sign(Q ps )·(ata ps -ata2 ps ),ats=[-π / 2,π / 2]; Among them, Q ps The second phase detection signal, I ps The first phase detection signal is denoted as rms, which is the root mean square operator.

6. The method according to claim 1, characterized in that, The scaling factors include: KD=2^N2, N2=[1, 2, 3,...,16]; Where KD is the scaling factor and N2 is the value of the multiplier that performs the shift operation.

7. The method according to claim 1, characterized in that, The step of performing second-order loop filtering on the frequency offset measurement result to obtain an error correction signal includes: Determine whether the frequency offset of the frequency offset measurement result is less than the set threshold, and select a second-order loop filter with the appropriate structure based on the determination result.

8. The method according to claim 7, characterized in that, The step of determining whether the frequency offset of the frequency offset measurement result is less than a set threshold, and selecting a second-order loop filter with a corresponding structure based on the determination result, includes: If the frequency offset of the frequency offset measurement result is less than the set threshold, then the second-order loop filter of the first structure is selected. The structural formula of the second-order loop filter of the first structure is: Among them, y ps The error correction signal is given by c1 and c2, which are the parameters of the second-order loop filter in the first structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the first structure, and τ1 and τ2 are time constants.

9. The method according to claim 7, characterized in that, The step of determining whether the frequency offset of the frequency offset measurement result is less than a set threshold, and selecting a second-order loop filter with a corresponding structure based on the determination result, includes: If the frequency offset of the frequency offset measurement result is greater than or equal to the set threshold, then the second-order loop filter of the second structure is selected. The structural formula of the second-order loop filter is as follows: Among them, y ps The error correction signal is given, and c1 and c2 are the parameters of the second-order loop filter in the second structure. ps The result is the frequency offset measurement result. ΔT is the signal input interval of the second-order loop filter of the second structure, and τ1 and τ2 are time constants.

10. A carrier loop tracking device for satellite navigation signals, characterized in that, The device includes: The input signal modulation module (10) is used to demodulate the input signal to obtain a first in-phase signal and a first quadrature signal; the output signal mapping module (20) is used to perform SIN / COS mapping processing on the output signal of the numerically controlled oscillator to obtain a second in-phase signal and a second quadrature signal. The mixing module (30) is used to multiply the first in-phase signal and the second in-phase signal to obtain the first phase detection signal, and to multiply the first quadrature signal and the second quadrature signal to obtain the second phase detection signal. Quadrant extraction module (40) is used to extract the sign bit of the first phase detection signal and the sign bit of the second phase detection signal; The phase amplitude acquisition module (50) is used to acquire the absolute value of the phase amplitude of the first phase detection signal and the absolute value of the phase amplitude of the second phase detection signal. The phase difference calculation module (60) is used to calculate the phase difference measurement result between the input signal and the output signal based on the absolute value of the sign bit and the corresponding phase amplitude of the first phase detection signal and the absolute value of the sign bit and the corresponding phase amplitude of the second phase detection signal, using a phase detection formula. The phase difference conversion module (70) is used to perform a conversion operation on the phase difference measurement result using a calibration factor to obtain the frequency offset measurement result. The value of the calibration factor is an adjustable value. The loop filtering module (80) is used to perform second-order loop filtering on the frequency offset measurement result to obtain an error correction signal; The frequency offset adjustment module (90) is used to adjust the frequency offset of the output signal based on the error correction signal until the frequency of the output signal can be synchronously tracked with the frequency of the input signal.

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