Data processing circuit, data processing method and memory

Abstract

The disclosed embodiments provide a data processing circuit, a data processing method, and a memory. The data processing circuit includes: a preprocessing module for sampling a first data signal according to a clock signal to obtain a first intermediate data signal; and sampling at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by shifting the first data signal; a driving module for driving the first intermediate data signal to generate a first target data signal; and driving the at least one second intermediate data signal to generate at least one second target data signal; wherein the at least one second target data signal is used to compensate the first target data signal to form a target data signal. The disclosed embodiments can ensure the accuracy of data signals and improve the high-speed performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a data processing circuit, a data processing method, and a memory. Background Art

[0002] With the continuous advancement of semiconductor technology, people are placing increasingly higher demands on data transmission speeds when manufacturing and using devices such as computers. To achieve faster data transmission speeds, a series of memory devices such as DDR4 and DDR5 chips have emerged, capable of transmitting data at double the data rate (DDR).

[0003] Compared to DDR4 chips, the maximum data speed of DDR5 chips has been increased from 3200 megabits per second (Mbps) to 6400Mbps. However, during the transmission of high-speed signals, inter-symbol interference (ISI) is very likely to occur, causing signal distortion. Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a data processing circuit, comprising a preprocessing module and a driving module, wherein an output terminal of the preprocessing module is connected to an input terminal of the driving module, wherein:

[0005] The pre-processing module is configured to receive a first data signal and at least one second data signal; sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal;

[0006] The driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal; perform driving processing on the first intermediate data signal to generate a first target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

[0007] The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

[0008] In some embodiments, the preprocessing module includes a first data selection module and at least one second data selection module, and the at least one second data selection module corresponds one-to-one to the at least one second data signal. The first data signal and the second data signal each include M parallel sub-data, and the clock signal includes M clock sub-signals, wherein:

[0009] the first data selection module is configured to receive the M clock sub-signals and the M sub-data in the first data signal, and sample the M sub-data in the first data signal according to the M clock sub-signals to generate the first intermediate data signal;

[0010] the second data selection module is configured to receive the M clock sub-signals and the corresponding M sub-data in the second data signal, and sample the M sub-data in the second data signal according to the M clock sub-signals to generate the corresponding second intermediate data signal;

[0011] The M clock sub-signals and the M sub-data correspond one to one.

[0012] In some embodiments, the data selection module includes: a clock generation module, M D flip-flops, and M switch units, wherein one D flip-flop and one switch unit are connected in series; the data selection module represents any one of the first data selection module and at least one second data selection module, wherein:

[0013] The clock generation module is configured to receive the M clock sub-signals and generate M target clock sub-signals according to the M clock sub-signals, wherein the target clock sub-signals are frequency-multiplied signals of the clock sub-signals;

[0014] the yth D flip-flop, configured to receive the yth sub-data and the yth clock sub-signal, and sample the yth sub-data according to the yth clock sub-signal to obtain the yth sampled sub-data;

[0015] the yth switching unit is configured to receive the yth target clock sub-signal and the yth sampled sub-data, and output the yth sampled sub-data as the yth intermediate sub-data when the yth target clock sub-signal is in a valid state;

[0016] Wherein, y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constitute an intermediate data signal, and the intermediate data signal represents any one of the first data signal and the at least one second data signal.

[0017] In some embodiments, the driving module includes a pull-up driving module and a pull-down driving module, wherein:

[0018] The pull-up driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-up target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-up target data signal;

[0019] The pull-down driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-down target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-down target data signal;

[0020] The first target data signal includes the first pull-up target data signal and / or the first pull-down target data signal, and the at least one second target data signal includes the at least one second pull-up target data signal and / or the at least one second pull-down target data signal.

[0021] In some embodiments, the pull-up driving module includes a pull-up driving main module and a pull-up driving compensation module, the pull-up driving compensation module includes at least one pull-up compensation sub-module, and the at least one pull-up compensation sub-module corresponds one-to-one to the at least one second intermediate data signal, wherein:

[0022] The pull-up driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-up target data signal;

[0023] The pull-up compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-up target data signal;

[0024] The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation submodule.

[0025] In some embodiments, the pull-down driving module includes a pull-down driving main module and a pull-down driving compensation module, the pull-down driving compensation module includes at least one pull-down compensation submodule, and the at least one pull-down compensation submodule corresponds one-to-one to the at least one second intermediate data signal, wherein:

[0026] The pull-down driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-down target data signal;

[0027] The pull-down compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-down target data signal;

[0028] The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation submodule.

[0029] In some embodiments, the pull-up compensation submodule includes a pre-driver module and a first main driver module, wherein:

[0030] The pre-driving module is configured to receive the corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal;

[0031] The first main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-up target data signal.

[0032] In some embodiments, the pre-driver module is connected to the first main driver module; wherein:

[0033] The pre-driving module is further configured to receive a pull-up compensation control signal and determine a compensation coefficient of the first main driving module according to the pull-up compensation control signal.

[0034] In some embodiments, the first main driving module includes a pull-up driving unit and a multiplier, wherein:

[0035] The pull-up driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-up driving signal;

[0036] The multiplier is configured to perform compensation processing on the pull-up driving signal to obtain the second pull-up target data signal;

[0037] The multiplier is used to control the compensation coefficient of the first main driving module.

[0038] In some embodiments, the pull-down compensation submodule includes a pre-driver module and a second main driver module, wherein:

[0039] The pre-driving module is configured to receive the corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal;

[0040] The second main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-down target data signal.

[0041] In some embodiments, the pre-driver module is connected to the second main driver module; wherein:

[0042] The pre-driving module is further configured to receive a pull-down compensation control signal and determine a compensation coefficient of the second main driving module according to the pull-down compensation control signal.

[0043] In some embodiments, the second main driving module includes a pull-down driving unit and a multiplier, wherein:

[0044] The pull-down driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-down driving signal;

[0045] The multiplier is configured to perform compensation processing on the pull-down driving signal to obtain the second pull-down target data signal;

[0046] The multiplier is used to control the compensation coefficient of the second main driving module.

[0047] In some embodiments, the data processing circuit further includes a shift register module, wherein:

[0048] The shift register module is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain the at least one second data signal.

[0049] In some embodiments, the shift register module includes at least one shift register, and the number of the at least one shift register and the at least one second data signal is N, where N is an integer greater than 0, wherein:

[0050] When N is equal to 1, the shift register is used to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain the second data signal;

[0051] When N is greater than 1, the first shift register is configured to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain a first second data signal;

[0052] The i-th shift register is used to receive the i-1-th second data signal and the clock signal, and shift the i-1-th second data signal according to the clock signal to obtain the i-th second data signal; wherein i is an integer greater than 1 and less than or equal to N.

[0053] In a second aspect, an embodiment of the present disclosure provides a data processing method, including:

[0054] receiving a first data signal and at least one second data signal through a preprocessing module; sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal;

[0055] receiving the first intermediate data signal and the at least one second intermediate data signal through a driving module; performing driving processing on the first intermediate data signal to generate a first target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

[0056] The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

[0057] In a third aspect, an embodiment of the present disclosure provides a memory comprising the data processing circuit described in any one of the first aspects.

[0058] The present disclosure provides a data processing circuit, a data processing method, and a memory. The data processing circuit includes: a preprocessing module and a driving module, wherein an output end of the preprocessing module is connected to an input end of the driving module, wherein: the preprocessing module is configured to receive a first data signal and at least one second data signal; sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by shifting the first data signal; and the driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal; drive the first intermediate data signal to generate a first target data signal, and drive the at least one second intermediate data signal to generate at least one second target data signal; wherein the first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form the target data signal. In this way, by predistorting the signal, the accuracy of the signal received by the controller after transmission through the channel is guaranteed, signal distortion is improved, and the high-speed performance of the memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A schematic diagram of the structure of a data processing circuit provided in an embodiment of the present disclosure Figure 1 ;

[0060] Figure 2 A schematic diagram of the structure of a data processing circuit provided in an embodiment of the present disclosure Figure 2 ;

[0061] Figure 3A A schematic diagram of the structure of a data selection module provided in an embodiment of the present disclosure Figure 1 ;

[0062] Figure 3B A schematic diagram of the structure of a data selection module provided in an embodiment of the present disclosure Figure 2 ;

[0063] Figure 4 A signal timing diagram provided in an embodiment of the present disclosure Figure 1 ;

[0064] Figure 5 Schematic diagram 3 of the structure of a data processing circuit provided in an embodiment of the present disclosure;

[0065] Figure 6 A schematic diagram of the structure of a data processing circuit provided in an embodiment of the present disclosure Figure 4 ;

[0066] Figure 7 A schematic diagram of the structure of a pull-up drive module provided in an embodiment of the present disclosure Figure 1 ;

[0067] Figure 8 A schematic diagram of the structure of a pull-down drive module provided in an embodiment of the present disclosure Figure 1 ;

[0068] Figure 9 A schematic diagram of the structure of a pull-up drive module provided in an embodiment of the present disclosure Figure 2 ;

[0069] Figure 10 A schematic diagram of the structure of a pull-up compensation submodule provided in an embodiment of the present disclosure Figure 1 ;

[0070] Figure 11 A schematic diagram of the structure of a pull-up compensation submodule provided in an embodiment of the present disclosure Figure 2 ;

[0071] Figure 12 A schematic diagram of the structure of a pull-down drive module provided in an embodiment of the present disclosure Figure 2 ;

[0072] Figure 13 A schematic diagram of the structure of a pull-down compensation submodule provided in an embodiment of the present disclosure Figure 1 ;

[0073] Figure 14 A schematic diagram of the structure of a pull-down compensation submodule provided in an embodiment of the present disclosure Figure 2 ;

[0074] Figure 15 A schematic diagram of the structure of a data processing circuit provided in an embodiment of the present disclosure Figure 5 ;

[0075] Figure 16 A schematic diagram of the structure of a data processing circuit provided in an embodiment of the present disclosure Figure 6 ;

[0076] Figure 17 A signal timing diagram provided in an embodiment of the present disclosure Figure 2 ;

[0077] Figure 18 A third signal timing diagram provided in an embodiment of the present disclosure;

[0078] Figure 19 A flowchart of a data processing method provided in an embodiment of the present disclosure;

[0079] Figure 20 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure;

[0080] Figure 21 A schematic diagram of the structure of a storage system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0083] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0084] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0085] For dynamic random access memory (DRAM), DDR5 increases data speeds from 3200Mbps to 6400Mbps compared to DDR4. While the DDR5 interface (including the transmitter and receiver) can achieve high speeds, the internal operating speed of DDR5 is half that of DDR4. When the transmitter sends high-speed signals to the DRAM controller through the channel, ISI (interference signal interference) (ISI) occurs, causing signal distortion and impacting performance.

[0086] Based on this, an embodiment of the present disclosure provides a data processing circuit, which includes: a preprocessing module and a driving module, and the output end of the preprocessing module is connected to the input end of the driving module, wherein: the preprocessing module is used to receive a first data signal and at least one second data signal; samples the first data signal according to a clock signal to obtain a first intermediate data signal, and samples the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by shifting the first data signal; the driving module is used to receive the first intermediate data signal and at least one second intermediate data signal; drives the first intermediate data signal to generate a first target data signal, and drives the at least one second intermediate data signal to generate at least one second target data signal; wherein the first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

[0087] In this way, by shifting the first data signal to be transmitted, at least one second data signal is obtained. The first data signal and the at least one second data signal are then driven to obtain a first target data signal and at least one second target data signal. The first target data signal is then compensated by the at least one second target data signal to form a target data signal. This achieves pre-distortion processing of the signal, ensuring the accuracy of the signal received by the controller after transmission through the channel, thereby improving the high-speed performance of the memory.

[0088] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0089] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a data processing circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the data processing circuit 10 includes a pre-processing module 11 and a driving module 12, and the output end of the pre-processing module 11 is connected to the input end of the driving module 12, wherein:

[0090] The preprocessing module 11 is configured to receive a first data signal and at least one second data signal; sample the first data signal according to a clock signal to obtain a first intermediate data signal; and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal;

[0091] The driving module 12 is configured to receive a first intermediate data signal and at least one second intermediate data signal; perform driving processing on the first intermediate data signal to generate a first target data signal, and perform driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

[0092] The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and at least one second target data signal is used to compensate the first target data signal to form a target data signal.

[0093] It should be noted that the data processing circuit 10 can be located at the transmitting end of the DRAM and is used to perform pre-distortion processing on the data signal, so as to ensure that the distortion caused by the channel transmission can be "offset" during the data signal transmission in the channel. Then, when the signal reaches the DRAM controller, the impact of ISI on the signal is improved, the distortion of the data signal is reduced, and the performance is improved.

[0094] It should also be noted that, in the embodiment of the present disclosure, the first data signal is the data signal to be transmitted. Taking the number of the second data signals as N as an example (N is an integer greater than 0), as Figure 1 As shown, the N second data signals include: second data signal 1, second data signal 2, ..., second data signal N. Each of the N second data signals is obtained by shifting the first data signal. More specifically, the first data signal is shifted to obtain second data signal 1, the second data signal 1 is shifted to obtain second data signal 2, ..., and the second data signal N-1 is shifted to obtain second data signal N.

[0095] The pre-processing module 11 samples the first data signal and at least one second data signal according to the clock signal to obtain a first intermediate data signal and at least one second intermediate data signal. Figure 1 As shown, corresponding to the N second data signals, the number of second intermediate data signals is also N, wherein the second data signal 1 is sampled to obtain the second intermediate data signal 1, the second data signal 2 is sampled to obtain the second intermediate data signal 2, ..., and the second data signal N is sampled to obtain the second intermediate data signal N.

[0096] The first data signal may be a parallel data signal, and the at least one second data signal obtained by shifting the first data signal is also a parallel data signal. Correspondingly, sampling the data signal may mean sampling each data element in the parallel data signal using a clock signal so as to output the data sequentially in time order, thereby converting the parallel data signal into a serial data signal. Compared to parallel data signals, serial data signals can be transmitted at a higher rate. It is understood that the first intermediate data signal and the at least one second intermediate data signal obtained by sampling may both be serial data signals.

[0097] The output of preprocessing module 11 is connected to the input of driver module 12. Preprocessing module 11 transmits a first intermediate data signal and at least one second intermediate data signal to driver module 12. Driver module 12 drives and processes the first intermediate data signal and the at least one second intermediate data signal to obtain a first target data signal and at least one second target data signal, respectively. Corresponding to the N second intermediate data signals, the number of second target data signals is also N. Here, second intermediate data signal 1 is driven to obtain second target data signal 1, second intermediate data signal 2 is driven to obtain second target data signal 2, ..., and second intermediate data signal N is driven to obtain second target data signal N.

[0098] It should also be noted that the N second target data signals are used to compensate the first target data signal, and the first target data signal and the N second target data signals are combined to form the target data signal. That is, the voltage value of the target data signal is the superposition of the voltage values ​​of the first target data signal and the N second target data signals. Figure 1 As shown, the driving module 12 outputs a target data signal composed of a first target data signal and N second target data.

[0099] That is, when transmitting a data signal, this embodiment adds compensation processing (or pre-distortion processing) to the transmitted data signal to compensate for signal distortion during transmission in the channel. If compensation processing is not added, only the first data signal is sampled to obtain a first intermediate data signal, and the first intermediate data signal is driven and processed to obtain a first target data signal as the target data signal, and sent to the controller through the channel; in this case, ISI will exist, causing the target data signal received by the controller to be distorted. This embodiment, based on processing the first data signal to obtain the first target data signal, also processes at least one second data signal obtained by shifting the first data signal to obtain at least one second target data signal, and uses the at least one second target data signal to compensate for the first target data signal to obtain the target data signal, thereby implementing pre-distortion processing of the signal before entering the channel, thereby reducing the impact of inter-symbol interference and ensuring the reliability of the signal reaching the controller after transmission through the channel.

[0100] When driving the N second intermediate data signals, corresponding compensation coefficients can be set for each signal, so that the voltage value of the second target data signal is the product of the voltage value / logic voltage value of the corresponding second intermediate data signal and the corresponding compensation coefficient. The specific value of the compensation coefficient can be set based on the specific channel environment and is not specifically limited.

[0101] See also Figure 2 , which shows a schematic diagram of the structure of a data processing circuit provided by an embodiment of the present disclosure Figure 2 .like Figure 2 As shown, in some embodiments, the preprocessing module 11 includes a first data selection module 111 and at least one second data selection module 112, and the at least one second data selection module 112 corresponds to at least one second data signal. The first data signal and the second data signal each include M parallel sub-data, and the clock signal includes M clock sub-signals, wherein:

[0102] A first data selection module 111 is configured to receive M clock sub-signals and M sub-data in a first data signal, and sample and process the M sub-data in the first data signal according to the M clock sub-signals to generate a first intermediate data signal;

[0103] The second data selection module 112 is configured to receive M clock sub-signals and M sub-data in the corresponding second data signal, sample the M sub-data in the second data signal according to the M clock sub-signals, and generate a corresponding second intermediate data signal;

[0104] The M clock sub-signals correspond to the M sub-data in a one-to-one manner.

[0105] It should be noted that the first data selection module 111 and the second data selection module 112 can have the same structure to realize the parallel-to-serial processing of the data signal. For the convenience of description, the first data selection module 111 or any of the second data selection modules 112 can be referred to as the data selection module 113. Taking the first data selection module 111 as an example, Figure 2 As shown, the signals received by the first data selection module 111 are the first data signal and the clock signal, that is, M parallel sub-data and M clock sub-signals are received, wherein there is a time delay between the M clock sub-signals in sequence.

[0106] The following briefly describes the working mode of the data selection module 113. Figure 3A , which shows a schematic diagram of the composition structure of a data selection module provided by an embodiment of the present disclosure Figure 1 .like Figure 3A As shown, in some embodiments, the data selection module 113 may include: a clock generation module 1131, M D flip-flops (DFF1, DFF2, ..., DFFM), M switch units (S1, S2, ..., SM), and one D flip-flop and one switch unit are connected in series; wherein:

[0107] The clock generation module 1131 is configured to receive M clock sub-signals and generate M target clock sub-signals based on the M clock sub-signals, where the target clock sub-signals are frequency-multiplied signals of the clock sub-signals.

[0108] a yth D flip-flop, configured to receive the yth sub-data and the yth clock sub-signal, and sample the yth sub-data according to the yth clock sub-signal to obtain the yth sampled sub-data;

[0109] a yth switching unit, configured to receive the yth target clock sub-signal and the yth sampled sub-data, and output the yth sampled sub-data as the yth intermediate sub-data when the yth target clock sub-signal is in a valid state;

[0110] Wherein, y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constitute an intermediate data signal, and the intermediate data signal represents any one of the first data signal and at least one second data signal.

[0111] It should be noted that the “valid state” may be a high-level logic 1 or a low-level logic 0. In the embodiment of the present disclosure, the “valid state” may be a high-level logic 1 as an example for description.

[0112] Furthermore, the data selection module 131 may also include a data enhancement module 1132, such as Figure 3AAs shown, the data enhancement module 1132 may include an even number of inverters (NOT, Figure 3A 2 are shown in FIG), which are used to enhance the intermediate data signal.

[0113] Taking M equal to 4 as an example, the data selection module may include a four-to-one data selector (4-1MUX). Figure 3B , which shows a schematic diagram of the composition structure of a data selection module provided by an embodiment of the present disclosure Figure 2 ,like Figure 3B As shown, the data selection module 113 may include: a clock generation module 1131, four D flip-flops: DFF1, DFF2, DFF3 and DFF4, and four switch units: S1, S2, S3 and S4; wherein:

[0114] The clock generation module is used to receive the first clock sub-signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK and the fourth clock sub-signal QBCLK, and generate the first target clock sub-signal ICLK_N, the second target clock sub-signal QCLK_N, the third target clock sub-signal IBCLK_N and the fourth target clock sub-signal QBCLK_N.

[0115] Figure 4 The corresponding signal timing diagram is shown. Figure 3B and Figure 4 As shown, the clock signal includes four clock sub-signals: a first clock sub-signal ICLK, a second clock sub-signal QCLK, a third clock sub-signal IBCLK and a fourth clock sub-signal QBCLK, and there are time delays in sequence. The phases of the four clock sub-signals can be 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively; the first data signal includes four sub-data: first sub-data Data_0 (including data D0 and data D4), second sub-data Data_1 (including data D1 and data D5), third sub-data Data_2 (including data D2 and data D6) and fourth sub-data Data_3 (including data D3 and data D7).

[0116] The clock generation module 1131 can generate a first target clock sub-signal ICLK_N, a second target clock sub-signal QCLK_N, a third target clock sub-signal IBCLK_N and a fourth target clock sub-signal QBCLK according to the first clock sub-signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK and the fourth clock sub-signal QBCLK. These target clock sub-signals are collectively referred to as target clock signals. Figure 4As shown, the high-level pulse width of each clock sub-signal is H1, and the high-level pulse width of each target clock sub-signal is H2. The clock generation module generates the first target clock sub-signal ICLK_N based on the rising edge of the first clock sub-signal ICLK, generates the second target clock sub-signal QCLK_N based on the rising edge of the second clock sub-signal QCLK, generates the third target clock sub-signal IBCLK_N based on the rising edge of the third clock sub-signal IBCLK, and generates the fourth target clock sub-signal QBCLK_N based on the rising edge of the fourth clock sub-signal QBCLK. The pulse width of the target clock sub-signal is smaller than the pulse width of the corresponding clock sub-signal. Clock generation module 1131 can be implemented by a clock signal generator.

[0117] The data selection module 113 samples and latches the first sub-data Data_0 at the rising edge of the first clock sub-signal ICLK. Specifically, Figure 4 The data D0 is sampled and latched on the first rising edge shown, and the data D4 is sampled and latched on the next rising edge; during the first high level pulse of the first target clock sub-signal ICLK_N, the sampled data D0 is output, and during the next high level pulse, the sampled data D4 is output. Figure 3B Taking the circuit structure shown as an example, DDF1 samples and latches D0 on the rising edge of the first clock sub-signal ICLK, and turns on the switch unit S1 when the first target clock sub-signal ICLK_N is in a high-level state, and the remaining switch units are not turned on, thereby outputting the sampled data during the high-level pulse of the first target clock sub-signal ICLK_N, and further enhancing and / or delaying the signal through two NOT gates NOT.

[0118] The same processing method is used for the remaining clock sub-signals and the corresponding sub-data, which will not be described here.

[0119] In this way, after being processed by the first data selection module 111 and the second data selection module 112 , the parallel first data signal and the parallel second data signal are converted into a serial first intermediate data signal and a serial second intermediate data signal respectively.

[0120] See also Figure 5 , which shows a structural diagram of a data processing circuit provided by an embodiment of the present disclosure. Figure 5As shown, in a specific implementation, at least one second data selection module includes a first data selection submodule MUX-1, a second data selection submodule MUX-2, a third data selection submodule MUX-3, and a fourth data selection submodule MUX-4, and at least one second data signal includes a first sub-data signal Data_Z1<3:0>, a second sub-data signal Data_Z2<3:0>, a third sub-data signal Data_Z3<3:0>, and a fourth sub-data signal Data_Z4<3:0>, wherein:

[0121] a first data selection submodule MUX-1, configured to receive M clock sub-signals and M sub-data in the first sub-data signal Data_Z1<3:0>, sample the M sub-data in the first sub-data signal according to the M clock sub-signals, and generate a serial first intermediate sub-data signal;

[0122] a second data selection submodule MUX-2, configured to receive M clock sub-signals and M sub-data in the second sub-data signal Data_Z2<3:0>, sample and process the M sub-data in the second sub-data signal according to the M clock sub-signals, and generate a serial second intermediate sub-data signal;

[0123] a third data selection submodule MUX-3, configured to receive M clock sub-signals and M sub-data in the third sub-data signal Data_Z3<3:0>, sample and process the M sub-data in the third sub-data signal according to the M clock sub-signals, and generate a serial third intermediate sub-data signal;

[0124] a fourth data selection submodule MUX-4, configured to receive the M clock sub-signals and the M sub-data in the fourth sub-data signal Data_Z4<3:0>, sample the M sub-data in the fourth sub-data signal according to the M clock sub-signals, and generate a serial fourth intermediate sub-data signal;

[0125] The at least one second intermediate data signal includes a first intermediate sub-data signal Mid_Z1 , a second intermediate sub-data signal Mid_Z2 , a third intermediate sub-data signal Mid_Z3 and a fourth intermediate sub-data signal Mid_Z4 .

[0126] It should be noted that if Figure 5As shown, Main-MUX represents the first data processing module. Taking the data signal to be transmitted as a data sequence composed of 8-bit sub-data as an example, the 8-bit sub-data are: data <0> 、data <1> 、data <2> 、data <3> 、data <4> 、data <5> 、data <6> and data <7> , combined and recorded as data<7:0>. Taking the data selection module including a 4-1 MUX as an example, in this case, M is equal to 4, meaning that both the first and second data signals include four sub-data. The first data signal Data_Z1<3:0> is data<3:0>, and for each of the second data signals: the first sub-data signal Data_Z1<3:0> is data<4:1>, the second sub-data signal Data_Z2<3:0> is data<5:2>, the third sub-data signal Data_Z3<3:0> is data<6:3>, and the fourth sub-data signal Data_Z4<3:0> is data<7:4>.

[0127] For the working mode of each data selection submodule, please refer to the above Figure 3B And related descriptions can be understood, and no further details are given here.

[0128] It should also be noted that this embodiment is used for pre-distortion / pre-distortion processing of the transmitted data signal before channel transmission. Therefore, the entire data processing circuit can also be called a Feed Forward Equalization (FFE) circuit or FFE architecture. The traditional FFE architecture is generally implemented through digital circuits, and the main driving circuit often adopts a differential structure; the output of DRAM adopts a single-ended structure, so the FFE architecture of DRAM must consider both the pre-distortion effect on the signal and the output impedance requirements of the DRAM standard; in order to meet the above requirements, this embodiment divides the transmitting end of the FFE into an FFE module (i.e., a pre-processing module 11) and an output driving module (i.e., a driving module 12); in Figure 5 In the specific implementation shown, the FFE module of the DRAM is composed of five four-select-one MUXs, and the 4-bit signals sent to the five MUXs are low-speed signals that are successively delayed.

[0129] Regarding the driving module 12, in some embodiments, as Figure 2 As shown, the driving module 12 includes a pull-up driving module 121 and a pull-down driving module 122, wherein:

[0130] The pull-up driving module 121 is configured to receive a first intermediate data signal and at least one second intermediate data signal, drive the first intermediate data signal to generate a first pull-up target data signal, and drive the at least one second intermediate data signal to generate at least one second pull-up target data signal.

[0131] The pull-down driving module 122 is configured to receive a first intermediate data signal and at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-down target data signal, and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-down target data signal.

[0132] The first target data signal includes a first pull-up target data signal and / or a first pull-down target data signal, and the at least one second target data signal includes at least one second pull-up target data signal and / or at least one second pull-down target data signal.

[0133] It should be noted that since DRAM uses a single-ended output structure, controlling the impedance of the DRAM driver module is particularly important. Therefore, the DRAM driver module 12 is divided into two parts: a pull-up driver module 121 (pull-up) and a pull-down driver module 122 (pull-down). The pull-up driver module 121 is used to perform pull-up processing on the received signal, while the pull-down driver module 122 is used to perform pull-down processing on the received signal.

[0134] exist Figure 2 In the implementation shown, the input terminals of the pull-up driving module 121 and the pull-down driving module 122 are both connected to the output terminal of the pre-processing module 11, and the pre-processing module 11 simultaneously provides the first intermediate data signal and at least one second intermediate data signal to the pull-up driving module 121 and the pull-down driving module 122. In another implementation, see Figure 6 , which shows a schematic diagram of the structure of a data processing circuit provided by an embodiment of the present disclosure Figure 4 .like Figure 6 As shown, the data processing circuit 10 may include two pre-processing modules, namely a pull-up pre-processing module 11A and a pull-down pre-processing module 11B, wherein the pull-up pre-processing module 11A and the pull-down pre-processing module 11B are both connected to the Figure 2 The preprocessing modules 11 shown have the same structure and function. The output end of the pull-up preprocessing module 11A is connected to the input end of the pull-up driving module 121, providing the first intermediate data signal and at least one second intermediate data signal to the pull-up driving module 121. The output end of the pull-down preprocessing module 11B is connected to the input end of the pull-down driving module 122, providing the first intermediate data signal and at least one second intermediate data signal to the pull-down driving module 122. The implementation of the preprocessing modules is not specifically limited herein.

[0135] It should also be noted that, depending on the level of the received signal, one of the pull-up driver module 121 and the pull-down driver module 122 is in an operating state to implement pull-up drive processing or pull-down drive processing of the signal. Here, the following examples are used to illustrate that when the signal is in a first level state, the pull-up driver module 121 is in an operating state and the pull-down driver module 122 is not operating; and when the signal is in a second level state, the pull-up driver module 121 is not operating and the pull-down driver module 122 is in an operating state. The first level state can represent a high-level logic 1, and the second level state can represent a low-level logic 0; or the first level state can represent a low-level logic 0, and the second level state can represent a high-level logic 1, etc., and the specific configuration is based on the circuit structure and is not specifically limited here.

[0136] For the first intermediate data signal, when the pull-up driving module 121 is in operation, the pull-up driving module 121 performs a pull-up driving process on the first intermediate data signal to obtain a first pull-up target data signal. When the pull-down driving module 122 is in operation, the pull-down driving module 122 performs a pull-down driving process on the first intermediate data signal to obtain a first pull-down target data signal. In other words, at a certain data point, the first target data signal is either the first pull-up target data signal or the first pull-down target data signal. Thus, the first pull-up target data signal and the first pull-down target data signal constitute the first target data signal. In other words, the first target data signal includes the first pull-up target data signal and / or the first pull-down target data signal.

[0137] For any second intermediate data signal, when the pull-up driving module 121 is in operation, it performs a pull-up driving process on the second intermediate data signal according to the corresponding compensation coefficient to obtain a second pull-up target data signal. When the pull-down driving module 122 is in operation, it performs a pull-down driving process on the second intermediate data signal according to the corresponding compensation coefficient to obtain a second pull-down target data signal. Thus, the voltage value (logical voltage value) of the second pull-up target data signal is the product of the voltage value (logical voltage value) of the second intermediate data signal and the corresponding compensation coefficient.

[0138] It should be noted that since the driver module 12 is divided into a pull-up driver module 121 and a pull-down driver module 122, corresponding compensation coefficients are set in the pull-up driver module 121 and the pull-down driver module 122, respectively, for the N second intermediate data signals. For example, the N compensation coefficients corresponding to the N second intermediate data signals in the pull-up driver module 121 are pull-up compensation coefficient 1, pull-up compensation coefficient 2, ..., pull-up compensation coefficient N, respectively; and the N compensation coefficients corresponding to the N second intermediate data signals in the pull-down driver module 122 are pull-down compensation coefficient 1, pull-down compensation coefficient 2, ..., pull-down compensation coefficient N, respectively. The values ​​of the compensation coefficients can be the same or different, and can be positive or negative. Furthermore, the pull-up compensation coefficient i and the pull-down compensation coefficient i can be the same or different, where i is an integer greater than or equal to 1 and less than or equal to N.

[0139] Similar to the first target data signal, at a certain data point, the second target data signal is a second pull-up target data signal or a second pull-down target data signal, so that the second pull-up target data signal and the second pull-down target data signal constitute the second target data signal, that is, the second target data signal includes the second pull-up target data signal and / or the second pull-down target data signal.

[0140] In addition, for the convenience of description, Figure 2 In the embodiment, the first pull-up target data signal and the N second pull-up target data signals are combined to form a pull-up target data signal, and the first pull-down target data signal and the N second pull-down target data signals are combined to form a pull-down target data signal.

[0141] Further, see Figure 7 , which shows a schematic diagram of the structure of a pull-up drive module provided by an embodiment of the present disclosure Figure 1 .like Figure 7 As shown, in some embodiments, the pull-up driving module 121 includes a pull-up driving main module 1211 and a pull-up driving compensation module 1212, wherein:

[0142] The pull-up driving main module 1211 is configured to receive a first intermediate data signal, perform driving processing on the first intermediate data signal, and generate a first pull-up target data signal;

[0143] The pull-up driving compensation module 1212 is configured to receive at least one second intermediate data signal, perform driving processing on the at least one second intermediate data signal, and generate at least one second pull-up target data signal.

[0144] It should be noted that the pull-up drive main module 1211 is the default module in the DRAM that performs pull-up processing on the data signal; the pull-up drive compensation module 1212 is a compensation module newly added in this embodiment to achieve pre-distortion of the signal. The pull-up drive compensation module 1212 can also be called a pull-up FFE module or FFE output drive (pull-up).

[0145] The function of the pull-up drive compensation module 1212 is to increase or decrease a small current based on the original default output current, so that the voltage of the output signal can be increased or decreased, thereby achieving pre-distortion processing of the signal and ensuring the reliability of the signal transmitted through the channel.

[0146] like Figure 7 As shown, in some embodiments, the pull-up driving compensation module 1212 includes at least one pull-up compensation submodule, and the at least one pull-up compensation submodule corresponds to at least one second intermediate data signal, wherein:

[0147] a pull-up compensation submodule, configured to receive a corresponding second intermediate data signal, drive the second intermediate data signal, and generate a corresponding second pull-up target data signal;

[0148] The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation submodule.

[0149] It should be noted that if Figure 7 As shown, corresponding to the N second intermediate data signals, the pull-up driving compensation module 1212 includes N pull-up compensation sub-modules, namely: pull-up compensation sub-module 1, pull-up compensation sub-module 2, ..., pull-up compensation sub-module N. Each pull-up compensation sub-module is provided with its own compensation coefficient to implement driving processing on the received second intermediate data signal according to the compensation coefficient.

[0150] The pull-up compensation submodule 1 drives and processes the second intermediate data signal 1, and the obtained voltage value of the second pull-up target data signal 1 is the product of the voltage value of the second intermediate data signal 1 and the compensation coefficient of the pull-up compensation submodule 1,..., the pull-up compensation submodule N drives and processes the second intermediate data signal N, and the obtained voltage value of the second pull-up target data signal N is the product of the voltage value of the second intermediate data signal N and the compensation coefficient of the pull-up compensation submodule N.

[0151] Similar to the structure of the pull-up drive module 121, see Figure 8 , which shows a schematic diagram of the structure of a pull-down driving module provided by an embodiment of the present disclosure Figure 1 .like Figure 8As shown, in some embodiments, the pull-down driving module 122 includes a pull-down driving main module 1221 and a pull-down driving compensation module 1222, wherein:

[0152] The pull-down driving main module 1221 is configured to receive a first intermediate data signal, perform driving processing on the first intermediate data signal, and generate a first pull-down target data signal;

[0153] The pull-down driving compensation module 1222 is configured to receive at least one second intermediate data signal, perform driving processing on the at least one second intermediate data signal, and generate at least one second pull-down target data signal.

[0154] It should be noted that the pull-down drive main module 1221 is the default module in the DRAM that performs pull-down processing on the data signal; the pull-down drive compensation module 1222 is a compensation module newly added in this embodiment to achieve pre-distortion of the signal. The pull-down drive compensation module 1222 can also be called a pull-down FFE module or FFE output drive (pull-up).

[0155] The function of the pull-down drive compensation module 1222 is to increase or decrease a small current based on the original default output current, so that the voltage of the output signal can be increased or decreased, thereby achieving pre-distortion processing of the signal and ensuring the reliability of the signal transmitted through the channel.

[0156] like Figure 8 As shown, in some embodiments, the pull-down driving compensation module 1222 includes at least one pull-down compensation submodule, and the at least one pull-down compensation submodule corresponds to the at least one second intermediate data signal, wherein:

[0157] a pull-down compensation submodule, configured to receive a corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate a corresponding second pull-down target data signal;

[0158] The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation submodule.

[0159] It should be noted that if Figure 8 As shown, corresponding to the N second intermediate data signals, the pull-down driving compensation module 1212 includes N pull-down compensation sub-modules, namely: pull-down compensation sub-module 1, pull-down compensation sub-module 2, ..., pull-down compensation sub-module N. Each pull-down compensation sub-module is provided with its own compensation coefficient to implement driving processing on the received second intermediate data signal according to the compensation coefficient.

[0160] The pull-down compensation submodule 1 drives and processes the second intermediate data signal 1, and the obtained voltage value of the second pull-down target data signal 1 is the product of the voltage value of the second intermediate data signal 1 and the compensation coefficient of the pull-down compensation submodule 1, ..., the pull-down compensation submodule N drives and processes the second intermediate data signal N, and the obtained voltage value of the second pull-down target data signal N is the product of the voltage value of the second intermediate data signal N and the compensation coefficient of the pull-down compensation submodule N.

[0161] Further, see Figure 9 , which shows a schematic diagram of the structure of a pull-up drive module provided by an embodiment of the present disclosure Figure 2 .like Figure 9 As shown, in some embodiments, at least one pull-up compensation submodule includes a first pull-up compensation submodule 1212A, a second pull-up compensation submodule 1212B, a third pull-up compensation submodule 1212C, and a fourth pull-up compensation submodule 1212D, and an input terminal of the first pull-up compensation submodule 1212A is connected to the output terminal of the first data selection submodule MUX-1, an input terminal of the second pull-up compensation submodule 1212B is connected to the output terminal of the second data selection submodule MUX-2, an input terminal of the third pull-up compensation submodule 1212C is connected to the output terminal of the third data selection submodule MUX-3, and an input terminal of the fourth pull-up compensation submodule 1212D is connected to the output terminal of the fourth data selection submodule MUX-4; wherein:

[0162] A first pull-up compensation submodule 1212A is configured to receive a first intermediate sub-data signal (FFE_tap_0), drive and process the first intermediate sub-data signal, and generate a first pull-up sub-target data signal (FFE_up_0); a voltage value of the first pull-up sub-target data signal is the product of the voltage value of the first intermediate sub-data signal and a compensation coefficient of the first pull-up compensation submodule 1212A;

[0163] The second pull-up compensation submodule 1212B is configured to receive the second intermediate sub-data signal (FFE_tap_1), drive and process the second intermediate sub-data signal, and generate a second pull-up sub-target data signal (FFE_up_1); the voltage value of the second pull-up sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-up compensation submodule 1212B;

[0164] a third pull-up compensation submodule 1212C configured to receive a third intermediate sub-data signal (FFE_tap_2), drive and process the third intermediate sub-data signal, and generate a third pull-up sub-target data signal (FFE_up_2); a voltage value of the third pull-up sub-target data signal being the product of the voltage value of the third intermediate sub-data signal FFE_tap_2 and a compensation coefficient of the third pull-up compensation submodule 1212C;

[0165] a fourth pull-up compensation submodule 1212D, configured to receive the fourth intermediate sub-data signal (FFE_tap_3), drive and process the fourth intermediate sub-data signal, and generate a fourth pull-up sub-target data signal (FFE_up_3); a voltage value of the fourth pull-up sub-target data signal being the product of the voltage value of the fourth intermediate sub-data signal FFE_tap_3 and a compensation coefficient of the fourth pull-up compensation submodule 1212D;

[0166] The at least one second pull-up target data signal includes a first pull-up sub-target data signal, a second pull-up sub-target data signal, a third pull-up sub-target data signal and a fourth pull-up sub-target data signal.

[0167] It should be noted that, in the embodiments of the present disclosure, Figure 9 As shown, taking a four-tap (4-tap) as an example, there are four pull-up compensation submodules, namely: a first pull-up compensation submodule 1212A, a second pull-up compensation submodule 1212B, a third pull-up compensation submodule 1212C and a fourth pull-up compensation submodule 1212D, which respectively implement drive processing for each intermediate data signal to obtain a corresponding second pull-up target data signal.

[0168] For each pull-up compensation submodule, Figure 9 For example, in some embodiments, the pull-up compensation submodule includes a pre-driver module (PRE_DRV) and a first main driver module (Main_DRV1), wherein:

[0169] a pre-driving module, configured to receive a corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal;

[0170] The first main driving module is configured to receive a corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain a corresponding second pull-up target data signal.

[0171] It should be noted that in the pull-up compensation submodule, the pre-driver module (in Figure 9 PRE_DRV (represented by PRE_DRV, which is the abbreviation of Predrive) is used to pre-drive the received second intermediate data signal to perform pre-drive enhancement on the second intermediate data signal. Its specific structure and working method can refer to the structure of existing DRAM and will not be elaborated here.

[0172] It should also be noted that the compensation coefficient (also called tap coefficient or FFE coefficient) of the pull-up compensation submodule specifically refers to the first main driver module (in Figure 9The compensation coefficient of the first main driver module (denoted as Main_DRV1 in the figure, short for Maindriver, and numbered with 1 to distinguish it from the second main driver module in the pull-down compensation submodule) can be determined by the number of resistors connected in parallel within it. Furthermore, the first main driver module can include one Main_DRV1 (similar to the first pull-up driver main module 1211A in the pull-up driver main module 1211), but can also consist of more Main_DRV1s connected in parallel, for example, two Main_DRV1s connected in parallel (see second pull-up driver main module 1211B).

[0173] In the pull-up driving module 121, the first main driving module is formed in the form of a P-type metal oxide field effect transistor (Positive channel Metal Oxide Semiconductor, PMOS tube) + resistor. Figure 9 The pull-up driving main module 1211 shown in FIG. 1 includes a first pull-up driving main module 1211A and three second pull-up driving main modules 1211B, which receive four control signals Default_DR respectively. <0> 、Default_DR <1> 、Default_DR <2> and Default_DR <3> , to adjust the number of parallel resistors in the first main driver module, thereby adjusting the driving capability of the first main driver module. The first pull-up driver main module 1211A and the second pull-up driver main module 1211B also simultaneously receive the first intermediate data signal and drive it to generate a first pull-up target data signal (Default_up_out). Wherein, Data_up_out represents the pull-up target data signal.

[0174] The pull-up driving compensation module 1212 increases / decreases a small current based on the original default output current, thereby raising / lowering the voltage across the resistor in the first main driving module, thereby increasing / lowering the output signal voltage.

[0175] Furthermore, for the compensation coefficient of the first main driving module (denoted as the pull-up compensation coefficient), see Figure 10 , which shows a schematic diagram of the composition structure of a pull-up compensation submodule provided by an embodiment of the present disclosure Figure 1 .like Figure 10 As shown, in one implementation, the pre-driver module (PRE_DRV) is connected to the first main driver module (Main_DRV1); wherein:

[0176] The pre-driving module 201 is further configured to receive a pull-up compensation control signal and determine a compensation coefficient of the first main driving module 202 according to the pull-up compensation control signal.

[0177] It should be noted that in Figure 10 In the embodiment, the first main driving module 202 is composed of a PMOS tube + a resistor. Figure 10 As shown, for any pull-up compensation submodule i, the pre-driver module 201 changes the number of parallel resistors in the first main driver module 202 according to the received pull-up compensation control signal i, thereby changing the output impedance of the first main driver module 202 and, in turn, changing the compensation coefficient of the first main driver module 202. When driving the second intermediate data signal i, the voltage value of the final output second pull-up target data signal i is the product of the voltage value of the second intermediate data signal i and the corresponding pull-up compensation coefficient i. Here, i is an integer greater than or equal to 1 and less than or equal to N.

[0178] In this way, the disclosed embodiment can utilize the pull-up compensation control signal to determine the compensation coefficient of the corresponding first main driver module, thereby enabling driving processing of the corresponding second intermediate data signal according to the compensation coefficient, and ultimately compensating the first target data signal to improve ISI and enhance the high-speed performance of the data signal. The pull-up compensation signal can be, for example, a zone qualifier (ZQ) calibration code.

[0179] See also Figure 11 , which shows a schematic diagram of the composition structure of a pull-up compensation submodule provided by an embodiment of the present disclosure Figure 2 .like Figure 11 As shown, in another implementation, the first main driving module 202 includes a pull-up driving unit 2021 and a multiplier 2022, wherein:

[0180] The pull-up driving unit 2021 is configured to perform driving processing on the second intermediate driving signal to obtain a pull-up driving signal;

[0181] a multiplier 2022 for performing compensation processing on the pull-up driving signal to obtain a second pull-up target data signal;

[0182] The multiplier 2022 is used to control the compensation coefficient of the first main driving module 202 .

[0183] It should be noted that the embodiment of the present disclosure can also use a multiplier to control the compensation coefficient of the first main driving module 202. In this implementation, Figure 11 As shown, for any pull-up compensation submodule i, the pre-driving module 201 receives the corresponding second intermediate data signal i, performs pre-driving processing on it to obtain the corresponding second intermediate driving signal i, and the pull-up driving unit 2021 is composed of a PMOS tube + resistor, which has the same Figure 10The pull-up driving unit 2021 drives the second intermediate driving signal i to obtain a pull-up driving signal i, which is then multiplied by the corresponding pull-up compensation coefficient i through the multiplier 2022 to obtain a corresponding second pull-up target data signal i. Wherein, i is an integer greater than or equal to 1 and less than or equal to N.

[0184] In this way, the embodiment of the present disclosure can also use the multiplier to control the compensation coefficient of the first main driving module, thereby achieving pre-distortion processing of the signal.

[0185] See also Figure 12 , which shows a schematic diagram of the structure of a pull-down driving module provided by an embodiment of the present disclosure Figure 2 .like Figure 12 As shown, in some embodiments, at least one pull-down compensation submodule includes a first pull-down compensation submodule 1222A, a second pull-down compensation submodule 1222B, a third pull-down compensation submodule 1222C, and a fourth pull-down compensation submodule 1222D, and an input terminal of the first pull-down compensation submodule 1222A is connected to the output terminal of the first data selection submodule MUX-1, an input terminal of the second pull-down compensation submodule 1222B is connected to the output terminal of the second data selection submodule MUX-2, an input terminal of the third pull-down compensation submodule 1222C is connected to the output terminal of the third data selection submodule MUX-3, and an input terminal of the fourth pull-down compensation submodule 1222D is connected to the output terminal of the fourth data selection submodule MUX-4; wherein:

[0186] The first pull-down compensation submodule 1222A is configured to receive the first intermediate sub-data signal (FFE_tap_0), drive and process the first intermediate sub-data signal, and generate a first pull-down sub-target data signal (FFE_down_0); the voltage value of the first pull-down sub-target data signal is the product of the voltage value of the first intermediate sub-data signal and the compensation coefficient of the first pull-down compensation submodule;

[0187] The second pull-down compensation submodule 1222B is configured to receive the second intermediate sub-data signal (FFE_tap_1), drive and process the second intermediate sub-data signal, and generate a second pull-down sub-target data signal (FFE_down_1); the voltage value of the second pull-down sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-down compensation submodule;

[0188] a third pull-down compensation submodule 1222C configured to receive a third intermediate sub-data signal (FFE_tap_2), drive and process the third intermediate sub-data signal, and generate a third pull-down sub-target data signal (FFE_down_2); a voltage value of the third pull-down sub-target data signal being the product of the voltage value of the third intermediate sub-data signal and a compensation coefficient of the third pull-down compensation submodule;

[0189] a fourth pull-down compensation submodule 1222D configured to receive a fourth intermediate sub-data signal (FFE_tap_3), drive and process the fourth intermediate sub-data signal, and generate a fourth pull-down sub-target data signal (FFE_down_3); a voltage value of the fourth pull-down sub-target data signal being the product of the voltage value of the fourth intermediate sub-data signal and a compensation coefficient of the fourth pull-down compensation submodule;

[0190] The at least one second pull-down target data signal includes a first pull-down sub-target data signal, a second pull-down sub-target data signal, a third pull-down sub-target data signal, and a fourth pull-down sub-target data signal.

[0191] It should be noted that, in the embodiments of the present disclosure, Figure 12 As shown, taking four-tap (4-tap) as an example, the number of pull-down compensation sub-modules is four, namely: a first pull-down compensation sub-module 1222A, a second pull-down compensation sub-module 1222B, a third pull-down compensation sub-module 1222C and a fourth pull-down compensation sub-module 1222D, which respectively implement drive processing for each intermediate data signal to obtain a corresponding second pull-down target data signal.

[0192] For each pull-down compensation submodule, Figure 12 For example, in some embodiments, the pull-down compensation submodule includes a pre-driver module (PRE_DRV) and a second main driver module (Main_DRV2), wherein:

[0193] a pre-driving module, configured to receive a corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal;

[0194] The second main driving module is configured to receive a corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain a corresponding second pull-down target data signal.

[0195] It should be noted that within the pull-down compensation submodule, the pre-driver module (PRE_DRV) is used to pre-drive the received second intermediate data signal. Its specific structure and operating mode can refer to the structure of existing DRAMs and will not be elaborated on in detail here. Furthermore, the pre-driver module in the pull-up compensation submodule can have the same or different structures as the pre-driver module in the pull-down compensation submodule. When the structures are different, for easier distinction, the pre-driver module in the pull-up compensation submodule can be referred to as the first pre-driver module, and the pre-driver module in the pull-down compensation submodule can be referred to as the pre-driver module.

[0196] It should also be noted that the compensation coefficient (also known as the tap coefficient or FFE coefficient) of the pull-down compensation submodule specifically refers to the compensation coefficient of the second main driver module. The compensation coefficient of the second main driver module can be determined by the number of resistors connected in parallel within the second main driver module. Furthermore, the second main driver module can include a single Main_DRV2 (similar to the first pull-down driver main module 1221A in the pull-down driver main module 1221), but can also include a larger number of Main_DRV2s connected in parallel, for example, two Main_DRV2s connected in parallel (see second pull-down driver main module 1221B).

[0197] In the pull-down driving module 121, the second main driving module is composed of an N-type metal oxide semiconductor field effect transistor (NMOS transistor + resistor). Figure 12 The pull-down driving main module 1221 shown in FIG. 1 includes a first pull-down driving main module 1221A and three second pull-down driving main modules 1221B, which receive four control signals Default_DR respectively. <0> 、Default_DR <1> 、Default_DR <2> and Default_DR <3> , to adjust the number of parallel resistors in the second main driver module, thereby adjusting the driving capability of the second main driver module. The first pull-down driver main module 1211A and the second pull-down driver main module 1211B also simultaneously receive the first intermediate data signal and drive it to generate a first pull-down target data signal (Default_down_out). Wherein, Data_down_out represents the pull-down target data signal.

[0198] The pull-down driving compensation module 1222 increases / decreases a small current based on the original default output current, thereby raising / lowering the voltage across the resistor in the second main driving module, thereby increasing / lowering the output signal voltage.

[0199] Furthermore, for the compensation coefficient of the second driving main module (recorded as the pull-down compensation coefficient), see Figure 13, which shows a schematic diagram of the structure of a pull-down compensation submodule provided by an embodiment of the present disclosure Figure 1 .like Figure 13 As shown, in one implementation, the pre-driver module (PRE_DRV) is connected to the second main driver module (Main_DRV2); wherein:

[0200] The pre-driving module 201 is further configured to receive a pull-down compensation control signal and determine a compensation coefficient of the second main driving module 203 according to the pull-down compensation control signal.

[0201] It should be noted that in Figure 13 In the embodiment, the second main driving module 203 is composed of an NMOS tube + a resistor. Figure 13 As shown, for any pull-down compensation submodule i, the pre-driver module 201 changes the number of parallel resistors in the second main driver module 203 according to the received pull-down compensation control signal i, thereby changing the output impedance of the second main driver module 203 and, in turn, the compensation coefficient of the second main driver module 203. When driving the second intermediate data signal i, the voltage value of the final output second pull-down target data signal i is the product of the voltage value of the second intermediate data signal i and the corresponding pull-down compensation coefficient i. Here, i is an integer greater than or equal to 1 and less than or equal to N.

[0202] In this way, the disclosed embodiments can utilize the pull-down compensation control signal to determine the compensation coefficient of the corresponding second main driver module, thereby enabling driving processing of the corresponding second intermediate data signal according to the compensation coefficient, and ultimately compensating the first target data signal to improve ISI and enhance the high-speed performance of the data signal. The pull-down compensation signal can be, for example, a ZQ calibration code.

[0203] See also Figure 14 , which shows a schematic diagram of the structure of a pull-down compensation submodule provided by an embodiment of the present disclosure Figure 2 .like Figure 14 As shown, in another implementation, the second main driving module 203 includes a pull-down driving unit 2031 and a multiplier 2032, wherein:

[0204] The pull-down driving unit 2031 is configured to perform driving processing on the second intermediate driving signal to obtain a pull-down driving signal;

[0205] a multiplier 2032 for performing compensation processing on the pull-down driving signal to obtain a second pull-down target data signal;

[0206] The multiplier 2032 is used to control the compensation coefficient of the second main driving module 2031 .

[0207] It should be noted that the embodiment of the present disclosure can also use a multiplier to control the compensation coefficient of the second main driving module 203. In this implementation, Figure 14 As shown, for any pull-down compensation submodule i, the pre-driving module 201 receives the corresponding second intermediate data signal i, performs pre-driving processing on it to obtain the corresponding second intermediate driving signal i, and the pull-down driving unit 2021 is composed of an NMOS tube + resistor, which has the same Figure 13 The pull-down driving unit 2021 drives the second intermediate driving signal i to obtain a pull-down driving signal i, which is then multiplied by the corresponding pull-down compensation coefficient i through the multiplier 2032 to obtain the corresponding second pull-down target data signal i. Here, i is an integer greater than or equal to 1 and less than or equal to N.

[0208] In this way, the embodiment of the present disclosure can also use the multiplier to control the compensation coefficient of the second main driving module, thereby achieving pre-distortion processing of the signal.

[0209] See also Figure 15 , which shows a schematic diagram of the structure of a data processing circuit provided by an embodiment of the present disclosure Figure 5 .like Figure 15 As shown, in some embodiments, the data processing circuit 10 further includes a shift register module 13, wherein:

[0210] The shift register module 13 is configured to receive a first data signal and a clock signal, and perform shift processing on the first data signal according to the clock signal to obtain at least one second data signal.

[0211] Specifically, if Figure 15 As shown, the shift register module 13 includes at least one shift register, and the number of the at least one shift register and the at least one second data signal is N, where N is an integer greater than 0, wherein:

[0212] When N is equal to 1, the shift register is used to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain the second data signal;

[0213] When N is greater than 1, the first shift register is used to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain the first second data signal;

[0214] The i-th shift register is used to receive the i-1-th second data signal and the clock signal, and shift the i-1-th second data signal according to the clock signal to obtain the i-th second data signal; wherein i is an integer greater than 1 and less than or equal to N.

[0215] It should be noted that in Figure 15 In the embodiment, still taking 4-tap as an example, the shift register module 13 may include four shift registers, wherein the shift registers may be implemented by DFFs. Therefore, the four shift registers are respectively recorded as DFF-1, DFF-2, DFF-3 and DFF-4.

[0216] Among them, DFF-1 shifts the first data signal Data_Z0<3:0> (including four sub-data D0_Z0, D1_Z0, D2_Z0 and D3_Z0) according to the clock signal (including the first clock sub-signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK and the fourth clock sub-signal QBCLK) to obtain the first sub-data signal Data_Z1<3:0> (including four sub-data D0_Z1, D1_Z1, D2_Z1). Z1 and D3_Z1), and sends the first sub-data signal to MUX-1, and also sends the first sub-data to DFF-2; DFF-2 shifts the first sub-data signal Data_Z1<3:0> (including four sub-data D0_Z1, D1_Z1, D2_Z1 and D3_Z1) according to the clock signal to obtain the second sub-data signal Data_Z2<3:0> (including four sub-data D0_Z2, D1_Z2, D2_Z2 and D3_Z2) and sends the second sub-data signal to MUX-2, and also sends the first sub-data to DFF-3; DFF-3 shifts the second sub-data signal Data_Z2<3:0> (including four sub-data D0_Z2, D1_Z2, D2_Z2 and D3_Z2) according to the clock signal to obtain the third sub-data signal Data_Z3<3:0> (including four sub-data D0_Z3, D1_Z3, D2_Z3 and D3_Z3), and sends the third sub-data signal The signal is sent to MUX-3, and the first sub-data is also sent to DFF-4; DFF-4 shifts the third sub-data signal Data_Z3<3:0> (including four sub-data D0_Z3, D1_Z3, D2_Z3 and D3_Z3) according to the clock signal to obtain the fourth sub-data signal Data_Z4<3:0> (including four sub-data D0_Z4, D1_Z4, D2_Z4 and D3_Z4), and sends the fourth sub-data signal to MUX-4.

[0217] The working modes of the pre-processing module 11 and the driving module 12 are not described in detail here.

[0218] In addition, with Figure 6 For corresponding Figure 16 , which shows a schematic diagram of the structure of a data processing circuit provided by an embodiment of the present disclosure Figure 6 ,exist Figure 16In the embodiment, the register module is divided into a pull-up register module 13A and a pull-down register module 13B, wherein the pull-up register module 13A and the pull-down register module 13B have the same Figure 15 The register module 13 has the same structure and function as shown, and will not be described in detail here.

[0219] It should be noted that, combined with Figure 9 and Figure 12 As shown, the difference between the pull-up driver module 121 and the pull-down driver module 122 lies in the difference in the main driver stage (Main_DRV1 and Main_DRV2). The main driver of the pull-up driver module 121 is composed of PMOS + resistor, while the main driver of the pull-down driver module 122 is composed of NMOS + resistor. Under normal circumstances, the main driver stage needs to ensure that the resistance of an internal resistor is 240Ω under different process, voltage, and temperature (PVT). PRE_DRV is the secondary driver stage of the DRAM. It mainly plays the role of adjusting the DRAM output impedance in different situations according to the standard (SPEC) requirements. The function of the FFE output driver (pull-up driver compensation module and pull-down driver compensation module) is to increase / decrease a small current based on the original default output current, thereby raising / lowering the voltage across the resistor, thereby increasing / lowering the output signal voltage.

[0220] Furthermore, the default output driver (i.e., pull-up driver main module 1211 and pull-down driver main module 1221) uses an on-die termination (ODT) calibration unit to control the DRAM output impedance at different PVTs. The FFE fine-tunes the number of MOSFETs in Main_DRV to select different resistance values. (Each MOSFET has a series resistor that controls its on / off state, effectively controlling the combined resistance of all resistors.)

[0221] See also Figure 17 , which shows a signal timing diagram provided by an embodiment of the present disclosure Figure 2 , where (a), (b), (c) and (d) respectively show the generation methods of the high-speed signals corresponding to Data_Z1<3:0>, Data_Z2<3:0>, Data_Z3<3:0> and Data_Z4<3:0>. For a description of the specific generation methods, please refer to Figure 3B and Figure 4 And related descriptions can be understood, and no further details are given here.

[0222] See also Figure 18, which shows a signal timing diagram provided by the embodiment of the present disclosure. It takes the 4-tap FFE signal superimposed on the output driver module as an example to illustrate the basic principle of the embodiment of the present disclosure. Table 1 takes the sequence 001110100001 as an example to further illustrate the principle of DRAM FFE through specific voltage values ​​(corresponding to Figure 18 the first 13 bits of ).

[0223] Table 1

[0224] Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 Main driver 0.00 0.00 1.00 1.00 1.00 0.00 1.00 0.00 0.00 0.00 0.00 0.00 1.00 Shift 1 bit 0.00 0.00 0.00 1.00 1.00 1.00 0.00 1.00 0.00 0.00 0.00 0.00 0.00 Tap 1 0.00 0.00 0.00 0.30 0.30 0.30 0.00 0.30 0.00 0.00 0.00 0.00 0.00 Shift 2bit 0.00 0.00 0.00 0.00 1.00 1.00 1.00 0.00 1.00 0.00 0.00 0.00 0.00 Tap 2 0.00 0.00 0.00 0.00 -0.20 -0.20 -0.20 0.00 -0.20 0.00 0.00 0.00 0.00 Shift 3bit 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 0.00 1.00 0.00 0.00 0.00 Tap 3 0.00 0.00 0.00 0.00 0.00 0.17 0.17 0.17 0.00 0.17 0.00 0.00 0.00 Shift 4bit 0.00 0.00 0.00 0.00 0.00 0.00 1.00 1.00 1.00 0.00 1.00 0.00 0.00 Tap 4 0.00 0.00 0.00 0.00 0.00 0.00 -0.08 -0.08 -0.08 0.00 -0.08 0.00 0.00 DQ OUT 0.00 0.00 1.00 1.30 1.10 0.27 0.89 0.39 -0.28 0.17 -0.08 0.00 1.00

[0225] In Table 1 and Figure 18 In the figure, data is displayed in serial format for ease of description. Main represents the first intermediate data signal, which is obtained by performing parallel-to-serial processing on the transmitted first data signal; Shift bit 1 represents the first intermediate sub-data signal, which is obtained by shifting the first data signal by 1 bit to obtain the first sub-data signal and then performing parallel-to-serial processing; Shift bit 2 represents the second intermediate sub-data signal, which is obtained by shifting the first sub-data signal by 1 bit to obtain the second sub-data signal and then performing parallel-to-serial processing; Shift bit 3 represents the third intermediate sub-data signal, which is obtained by shifting the second sub-data signal by 1 bit to obtain the third sub-data signal and then performing parallel-to-serial processing; and Shift bit 4 represents the fourth intermediate sub-data signal, which is obtained by shifting the third sub-data signal by 1 bit to obtain the fourth sub-data signal and then performing parallel-to-serial processing. DQ_OUT represents the target data signal.

[0226] Assume that the compensation coefficients corresponding to the four pull-up compensation submodules in the pull-up drive compensation module 1212 and the four pull-down compensation submodules in the pull-down drive compensation module 1222 are 0.3, -0.2, 0.17, and -0.08, respectively. In other words, the compensation coefficient for compensating the first intermediate sub-data signal is 0.3, the compensation coefficient for compensating the second intermediate sub-data signal is -0.2, the compensation coefficient for compensating the third intermediate sub-data signal is 0.17, and the compensation coefficient for compensating the fourth intermediate sub-data signal is -0.08.

[0227] In this way, Figure 18 As shown in the figure, the waveform of the signal originally to be transmitted is shown as Main, and the waveform of the signal entering the channel after compensation processing is shown as DQ OUT. During transmission through the channel, the influence of ISI can be reduced, so that after passing through the channel, the waveform of the signal finally transmitted to the memory controller is basically consistent with the waveform of the original transmitted signal, reducing signal distortion and ensuring signal reliability.

[0228] In short, this embodiment introduces a four-tap DFF in the DDR5 DRAM data (DQ) transmitter, optimizing signal integrity when it reaches the controller. Using pull-up and pull-down driver modules to regulate output current also meets Joint Electron Device Engineering Council (JEDEC) specifications, enabling FFE to adapt to the higher speeds of the DRAM market.

[0229] Among them, the output resistance includes the default resistance (the resistance of the main driving stage in the pull-up driving main module and the resistance of the main driving stage in the pull-down driving main module) and the FFE resistance (the resistance of the main driving stage in the pull-down driving compensation module and the resistance of the main driving stage in the pull-down driving compensation module). The default resistance adopts the traditional DRAM output circuit structure. The FFE resistance is controlled by the Tap-1 / Tap-2 / Tap-3 / Tap-4 coefficient value (compensation coefficient). Among them, the FFE resistance and the traditional default resistance can be connected in parallel. The output resistance composed of the FFE resistance and the traditional default resistance should be as close to SPEC as possible, but a small range of deviation is allowed. In addition, the FFE driving circuit structure is a single-ended output, and its output resistance is very important and must meet SPEC.

[0230] This embodiment relates to memory, particularly high-speed memory such as DDR5. A DDR5 transmitter sends data signals to a DRAM controller. Due to the high signal rate and significant channel attenuation, signal integrity at the controller can be poor. To address this issue and ensure signal integrity at the DRAM controller, this embodiment proposes a 4-tap FFE circuit to pre-distort the signal before sending it to the controller. This enables the DDR5 transmitter to achieve higher data rates.

[0231] In another embodiment of the present disclosure, Figure 19 , which shows a flow chart of a data processing method provided by an embodiment of the present disclosure, such as Figure 19 As shown, the method includes:

[0232] S191: Receive a first data signal and at least one second data signal through a preprocessing module; sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein, the at least one second data signal is obtained by shifting the first data signal.

[0233] S192: Receive a first intermediate data signal and at least one second intermediate data signal through a driving module, drive the first intermediate data signal to generate a first target data signal; and drive the at least one second intermediate data signal to generate at least one second target data signal.

[0234] The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and at least one second target data signal is used to compensate the first target data signal to form a target data signal.

[0235] In some embodiments, the clock signal includes M clock sub-signals, and step S191 includes:

[0236] receiving, through a first data selection module, M clock sub-signals and M sub-data in the first data signal, and selecting and processing the M sub-data in the first data signal according to the M clock sub-signals to generate a first intermediate data signal;

[0237] receiving, through a second data selection module, M clock sub-signals and M sub-data in the corresponding second data signal, and selecting and processing the M sub-data in the second data signal according to the M clock sub-signals to generate a corresponding second intermediate data signal;

[0238] The M clock sub-signals correspond to the M sub-data in a one-to-one manner.

[0239] In some embodiments, the data selection module selects and processes the data signal to generate an intermediate data signal, including:

[0240] The clock generation module receives M clock sub-signals and generates M target clock sub-signals according to the M clock sub-signals, where the target clock sub-signals are frequency-multiplied signals of the corresponding clock sub-signals;

[0241] receiving the yth sub-data and the yth clock sub-signal through the yth D flip-flop, sampling the yth sub-data according to the yth clock sub-signal, and obtaining the yth sampled sub-data;

[0242] receiving the yth target clock sub-signal and the yth sampled sub-data through the yth switch unit, and outputting the yth sampled sub-data as the yth intermediate sub-data when the yth target clock sub-signal is in a valid state;

[0243] Wherein, y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constitute an intermediate data signal, and the intermediate data signal represents any one of the first data signal and at least one second data signal.

[0244] In some embodiments, sampling at least one second data signal to obtain at least one second intermediate data signal includes:

[0245] receiving, by a first data selection submodule, M clock sub-signals and M sub-data in the first sub-data signal, and performing selection processing on the M sub-data in the first sub-data signal according to the M clock sub-signals, to generate a serial first intermediate sub-data signal;

[0246] receiving, through a second data selection submodule, M clock sub-signals and M sub-data in the second sub-data signal, and performing selection processing on the M sub-data in the second sub-data signal according to the M clock sub-signals, to generate a serial second intermediate sub-data signal;

[0247] receiving, through a third data selection submodule, M clock sub-signals and M sub-data in the third sub-data signal, and performing selection processing on the M sub-data in the third sub-data signal according to the M clock sub-signals, to generate a serial third intermediate sub-data signal;

[0248] receiving, through a fourth data selection submodule, M clock sub-signals and M sub-data in the fourth sub-data signal, and selecting and processing the M sub-data in the fourth sub-data signal according to the M clock sub-signals to generate a serial fourth intermediate sub-data signal;

[0249] The at least one second intermediate data signal includes a first intermediate sub-data signal, a second intermediate sub-data signal, a third intermediate sub-data signal, and a fourth intermediate sub-data signal.

[0250] In some embodiments, step S192 includes:

[0251] S1921: Receive, by a pull-up driving module, a first intermediate data signal and at least one second intermediate data signal, drive the first intermediate data signal to generate a first pull-up target data signal; and drive the at least one second intermediate data signal to generate at least one second pull-up target data signal.

[0252] S1922: Receive, by a pull-down driving module, a first intermediate data signal and at least one second intermediate data signal, drive the first intermediate data signal to generate a first pull-down target data signal; and drive the at least one second intermediate data signal to generate at least one second pull-down target data signal.

[0253] The first target data signal includes a first pull-up target data signal and / or a first pull-down target data signal, and the at least one second target data signal includes at least one second pull-up target data signal and / or at least one second pull-down target data signal.

[0254] In some embodiments, step S1921 includes:

[0255] receiving a first intermediate data signal through a pull-up driving main module, performing driving processing on the first intermediate data signal, and generating a first pull-up target data signal;

[0256] At least one second intermediate data signal is received through the pull-up driving compensation module, and driving processing is performed on the at least one second intermediate data signal to generate at least one second pull-up target data signal.

[0257] In some embodiments, step S1922 includes:

[0258] receiving a first intermediate data signal through a pull-down driving main module, performing driving processing on the first intermediate data signal, and generating a first pull-down target data signal;

[0259] At least one second intermediate data signal is received through the pull-down driving compensation module, and driving processing is performed on the at least one second intermediate data signal to generate at least one second pull-down target data signal.

[0260] In some embodiments, receiving at least one second intermediate data signal through a pull-up drive compensation module, performing drive processing on the at least one second intermediate data signal, and generating at least one second pull-up target data signal include:

[0261] receiving the corresponding second intermediate data signal through the pull-up compensation submodule, driving and processing the second intermediate data signal, and generating a corresponding second pull-up target data signal;

[0262] The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation submodule.

[0263] In some embodiments, receiving at least one second intermediate data signal through a pull-up drive compensation module, performing drive processing on the at least one second intermediate data signal, and generating at least one second pull-up target data signal include:

[0264] The first pull-up compensation submodule receives the first intermediate sub-data signal and drives the first intermediate sub-data signal to generate a first pull-up sub-target data signal; the voltage value of the first pull-up sub-target data signal is the product of the voltage value of the first intermediate sub-data signal and the compensation coefficient of the first pull-up compensation submodule;

[0265] The second pull-up compensation submodule receives the second intermediate sub-data signal and drives the second intermediate sub-data signal to generate a second pull-up sub-target data signal; the voltage value of the second pull-up sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-up compensation submodule;

[0266] The third pull-up compensation submodule receives the third intermediate sub-data signal and drives the third intermediate sub-data signal to generate a third pull-up sub-target data signal; the voltage value of the third pull-up sub-target data signal is the product of the voltage value of the third intermediate sub-data signal and the compensation coefficient of the third pull-up compensation submodule;

[0267] The fourth pull-up compensation submodule receives the fourth intermediate sub-data signal and drives the fourth intermediate sub-data signal to generate a fourth pull-up sub-target data signal; the voltage value of the fourth pull-up sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal and the compensation coefficient of the fourth pull-up compensation submodule;

[0268] The at least one second pull-up target data signal includes a first pull-up sub-target data signal, a second pull-up sub-target data signal, a third pull-up sub-target data signal and a fourth pull-up sub-target data signal.

[0269] In some embodiments, receiving at least one second intermediate data signal through a pull-down drive compensation module, performing drive processing on the at least one second intermediate data signal, and generating at least one second pull-down target data signal include:

[0270] receiving the corresponding second intermediate data signal through the pull-down compensation submodule, driving and processing the second intermediate data signal, and generating a corresponding second pull-down target data signal;

[0271] The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation submodule.

[0272] In some embodiments, receiving at least one second intermediate data signal through a pull-down drive compensation module, performing drive processing on the at least one second intermediate data signal, and generating at least one second pull-down target data signal include:

[0273] The first pull-down compensation submodule receives the first intermediate sub-data signal and drives the first intermediate sub-data signal to generate a first pull-down sub-target data signal; the voltage value of the first pull-down sub-target data signal is the product of the voltage value of the first intermediate sub-data signal and the compensation coefficient of the first pull-down compensation submodule;

[0274] The second pull-down compensation submodule receives the second intermediate sub-data signal and drives the second intermediate sub-data signal to generate a second pull-down sub-target data signal; the voltage value of the second pull-down sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-down compensation submodule;

[0275] The third pull-down compensation submodule receives the third intermediate sub-data signal and drives the third intermediate sub-data signal to generate a third pull-down sub-target data signal; the voltage value of the third pull-down sub-target data signal is the product of the voltage value of the third intermediate sub-data signal and the compensation coefficient of the third pull-down compensation submodule;

[0276] The fourth pull-down compensation submodule receives the fourth intermediate sub-data signal and drives the fourth intermediate sub-data signal to generate a fourth pull-down sub-target data signal; the voltage value of the fourth pull-down sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal and the compensation coefficient of the fourth pull-down compensation submodule;

[0277] The at least one second pull-down target data signal includes a first pull-down sub-target data signal, a second pull-down sub-target data signal, a third pull-down sub-target data signal, and a fourth pull-down sub-target data signal.

[0278] In some embodiments, receiving the corresponding second intermediate data signal through the pull-up compensation submodule, and performing drive processing on the second intermediate data signal to obtain the corresponding second pull-up target data signal include:

[0279] receiving a corresponding second intermediate data signal through a pre-driving module, performing pre-driving processing on the second intermediate data signal, and generating a corresponding second intermediate driving signal;

[0280] The corresponding second intermediate driving signal is received by the first main driving module, and a compensation driving process is performed on the second intermediate driving signal to obtain a corresponding second pull-up target data signal.

[0281] In some embodiments, the method further comprises:

[0282] The pre-driving module is further configured to receive a pull-up compensation control signal and determine a compensation coefficient of the first main driving module according to the pull-up compensation control signal.

[0283] In some embodiments, receiving the corresponding second intermediate driving signal through the first main driving module, performing compensation driving processing on the second intermediate driving signal, and obtaining the corresponding second pull-up target data signal includes:

[0284] receiving a second intermediate driving signal through a pull-up driving unit, and performing driving processing on the second intermediate driving signal to obtain a pull-up driving signal;

[0285] receiving the pull-up driving signal through a multiplier, performing compensation processing on the pull-up driving signal, and obtaining a second pull-up target data signal;

[0286] The multiplier is used to control the compensation coefficient of the first main driving module.

[0287] In some embodiments, receiving the corresponding second intermediate data signal through the pull-down compensation submodule, and performing drive processing on the second intermediate data signal to obtain the corresponding second pull-down target data signal include:

[0288] receiving a corresponding second intermediate data signal through a pre-driving module, performing pre-driving processing on the second intermediate data signal, and generating a corresponding second intermediate driving signal;

[0289] The corresponding second intermediate driving signal is received by the second main driving module, and a compensation driving process is performed on the second intermediate driving signal to obtain a corresponding second pull-down target data signal.

[0290] In some embodiments, the method further comprises:

[0291] The pull-down compensation control signal is received by the pre-driving module, and a compensation coefficient of the second main driving module is determined according to the pull-down compensation control signal.

[0292] In some embodiments, receiving the corresponding second intermediate driving signal through the second main driving module, performing compensation driving processing on the second intermediate driving signal, and obtaining the corresponding second pull-down target data signal includes:

[0293] receiving a second intermediate driving signal through a pull-down driving unit, and performing driving processing on the second intermediate driving signal to obtain a pull-down driving signal;

[0294] receiving a pull-down driving signal through a multiplier, performing compensation processing on the pull-down driving signal, and obtaining a second pull-down target data signal;

[0295] The multiplier is used to control the compensation coefficient of the second main driving module.

[0296] In some embodiments, the method further comprises:

[0297] The first data signal and the clock signal are received by the shift register module, and the first data signal is shifted according to the clock signal to obtain at least one second data signal.

[0298] In some embodiments, the number of the at least one shift register and the number of the at least one second data signal are both N, where N is an integer greater than 0, wherein:

[0299] When N is equal to 1, a first data signal and a clock signal are received by a shift register module, and the first data signal is shifted according to the clock signal to obtain at least one second data signal, including:

[0300] receiving a first data signal and a clock signal through a shift register, and performing shift processing on the first data signal according to the clock signal to obtain a second data signal;

[0301] When N is greater than 1, receiving a first data signal and a clock signal through a shift register module, shifting the first data signal according to the clock signal to obtain at least one second data signal, including:

[0302] receiving a first data signal and a clock signal through a first shift register, and performing shift processing on the first data signal according to the clock signal to obtain a first second data signal;

[0303] The i-1th second data signal and the clock signal are received by the i-th shift register, and the i-1th second data signal is shifted according to the clock signal to obtain the i-th second data signal; wherein i is an integer greater than 1 and less than or equal to N.

[0304] It should be noted that this method is applied to the data processing circuit 10 of the aforementioned embodiment. For details and specific descriptions not disclosed in the embodiment of this disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0305] The disclosed embodiments provide a data processing method that performs a shift process on a first data signal to be transmitted to obtain at least one second data signal. The first data signal and the at least one second data signal are then driven to obtain a first target data signal and at least one second target data signal. The at least one second target data signal is then used to compensate the first target data signal to form a target data signal. This method implements predistortion processing on the signal, ensuring the accuracy of the signal received by the controller after transmission through the channel.

[0306] In another embodiment of the present disclosure, see Figure 20 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 20 As shown, the memory 200 may at least include the data processing circuit 10 described in any one of the aforementioned embodiments.

[0307] In some embodiments, the memory 10 is a semiconductor memory, such as a DRAM chip.

[0308] In the embodiments of the present disclosure, DRAM chips can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5, without any limitation.

[0309] Since the memory 200 includes the data processing circuit 10, the memory can improve the adverse effects of ISI on the signal, ensure the transmission performance of the signal, and help improve the high-speed performance of the memory.

[0310] In another embodiment of the present disclosure, see Figure 21 , which shows a schematic diagram of the composition structure of a storage system provided by an embodiment of the present disclosure. Figure 21 As shown, the memory system 400 includes the memory 200 and the memory controller 300 in the aforementioned embodiment, wherein the memory 200 and the memory controller 300 are connected via a channel.

[0311] For the storage system 400, since the memory 200 includes the aforementioned data processing circuit 10, when the signal is transmitted to the memory controller 300 via the channel, the predistortion effect and the channel distortion cancel each other out, thereby improving the impact of ISI on the signal and ensuring the reliability of the signal.

[0312] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0313] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0314] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0315] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0316] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0317] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0318] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data processing circuit, characterized in that: include: A pre-processing module and a driving module, wherein the output end of the pre-processing module is connected to the input end of the driving module, wherein: The pre-processing module is configured to receive a first data signal and at least one second data signal; sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal; The driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal; perform driving processing on the first intermediate data signal to generate a first target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second target data signal; The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

2. The data processing circuit according to claim 1, wherein: The preprocessing module includes a first data selection module and at least one second data selection module, and the at least one second data selection module corresponds one-to-one to the at least one second data signal. The first data signal and the second data signal each include M parallel sub-data, and the clock signal includes M clock sub-signals, wherein: the first data selection module is configured to receive the M clock sub-signals and the M sub-data in the first data signal, and sample the M sub-data in the first data signal according to the M clock sub-signals to generate the first intermediate data signal; the second data selection module is configured to receive the M clock sub-signals and the corresponding M sub-data in the second data signal, and sample the M sub-data in the second data signal according to the M clock sub-signals to generate the corresponding second intermediate data signal; The M clock sub-signals and the M sub-data correspond one to one.

3. The data processing circuit according to claim 2, wherein: The data selection module includes: a clock generation module, M D flip-flops, and M switch units, wherein one D flip-flop and one switch unit are connected in series; the data selection module represents any one of the first data selection module and the at least one second data selection module, wherein: The clock generation module is configured to receive the M clock sub-signals and generate M target clock sub-signals according to the M clock sub-signals, wherein the target clock sub-signals are frequency-multiplied signals of the clock sub-signals; the yth D flip-flop, configured to receive the yth sub-data and the yth clock sub-signal, and sample the yth sub-data according to the yth clock sub-signal to obtain the yth sampled sub-data; the yth switching unit is configured to receive the yth target clock sub-signal and the yth sampled sub-data, and output the yth sampled sub-data as the yth intermediate sub-data when the yth target clock sub-signal is in a valid state; Wherein, y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constitute an intermediate data signal, and the intermediate data signal represents any one of the first data signal and the at least one second data signal.

4. The data processing circuit according to claim 1, wherein: The driving module includes a pull-up driving module and a pull-down driving module, wherein: The pull-up driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-up target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-up target data signal; The pull-down driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-down target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-down target data signal; The first target data signal includes the first pull-up target data signal and / or the first pull-down target data signal, and the at least one second target data signal includes the at least one second pull-up target data signal and / or the at least one second pull-down target data signal.

5. The data processing circuit according to claim 4, characterized in that: The pull-up driving module includes a pull-up driving main module and a pull-up driving compensation module. The pull-up driving compensation module includes at least one pull-up compensation submodule. The at least one pull-up compensation submodule corresponds to the at least one second intermediate data signal in a one-to-one manner. The pull-up driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-up target data signal; The pull-up compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-up target data signal; The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation submodule.

6. The data processing circuit according to claim 4, wherein: The pull-down driving module includes a pull-down driving main module and a pull-down driving compensation module. The pull-down driving compensation module includes at least one pull-down compensation submodule. The at least one pull-down compensation submodule corresponds to the at least one second intermediate data signal in a one-to-one manner. The pull-down driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-down target data signal; The pull-down compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-down target data signal; The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation submodule.

7. The data processing circuit according to claim 5, characterized in that: The pull-up compensation submodule includes a pre-driver module and a first main driver module, wherein: The pre-driving module is configured to receive the corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal; The first main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-up target data signal.

8. The data processing circuit according to claim 7, wherein: The pre-driver module is connected to the first main driver module; wherein: The pre-driving module is further configured to receive a pull-up compensation control signal and determine a compensation coefficient of the first main driving module according to the pull-up compensation control signal.

9. The data processing circuit according to claim 7, wherein: The first main driving module includes a pull-up driving unit and a multiplier, wherein: The pull-up driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-up driving signal; The multiplier is configured to perform compensation processing on the pull-up driving signal to obtain the second pull-up target data signal; The multiplier is used to control the compensation coefficient of the first main driving module.

10. The data processing circuit according to claim 6, wherein: The pull-down compensation submodule includes a pre-driver module and a second main driver module, wherein: The pre-driving module is configured to receive the corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal; The second main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-down target data signal.

11. The data processing circuit according to claim 10, wherein: The pre-driver module is connected to the second main driver module; wherein: The pre-driving module is further configured to receive a pull-down compensation control signal and determine a compensation coefficient of the second main driving module according to the pull-down compensation control signal.

12. The data processing circuit according to claim 10, wherein: The second main driving module includes a pull-down driving unit and a multiplier, wherein: The pull-down driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-down driving signal; The multiplier is configured to perform compensation processing on the pull-down driving signal to obtain the second pull-down target data signal; The multiplier is used to control the compensation coefficient of the second main driving module.

13. The data processing circuit according to any one of claims 1 to 12, characterized in that: The data processing circuit further includes a shift register module, wherein: The shift register module is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain the at least one second data signal.

14. The data processing circuit according to claim 13, wherein: The shift register module includes at least one shift register, and the number of the at least one shift register and the at least one second data signal is N, where N is an integer greater than 0, wherein: When N is equal to 1, the shift register is used to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain the second data signal; When N is greater than 1, the first shift register is configured to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain a first second data signal; The i-th shift register is used to receive the i-1-th second data signal and the clock signal, and shift the i-1-th second data signal according to the clock signal to obtain the i-th second data signal; wherein i is an integer greater than 1 and less than or equal to N.

15. A data processing method, characterized in that: The method comprises: receiving a first data signal and at least one second data signal through a preprocessing module; sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal; receiving the first intermediate data signal and the at least one second intermediate data signal through a driving module; performing driving processing on the first intermediate data signal to generate a first target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second target data signal; The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

16. A memory, characterized in that: The data processing circuit comprises the data processing circuit according to any one of claims 1 to 14.

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