A method of polishing a silicon carbide wafer and a method of polishing a semiconductor wafer

Abstract

The present application relates to the technical field of silicon carbide processing, and particularly relates to a polishing method of a silicon carbide wafer and a polishing method of a semiconductor wafer. The present application provides a silicon carbide wafer after rough grinding or fine grinding, carries out alkali corrosion on the silicon carbide wafer, takes a photo under a microscope to obtain a gray scale diagram after placing the silicon carbide wafer after alkali corrosion under the microscope, adjusts a threshold value of the gray scale diagram, obtains a dislocation diagram, carries out dislocation characterization and statistics on the dislocation diagram, and finally carries out subsequent polishing processing on the silicon carbide wafer after the dislocation characterization and statistics. The present application carries out alkali corrosion on the silicon carbide wafer after rough grinding or fine grinding in the processing process. Since the depth of the dislocation corrosion pits and the depth of the corrosion pits formed by the processing damage are different, the contrast of the dislocation corrosion pits and the processing damage corrosion pits is also different. By adjusting the threshold value of the gray scale diagram, the corrosion pits formed by the processing damage are excluded, so that all the dislocation corrosion pits are in the dislocation diagram, which is beneficial to the computer software to read the picture information to distinguish and count the dislocation types.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide processing technology, and particularly to a polishing method for silicon carbide wafers and a polishing method for semiconductor wafers. Background Technology

[0002] Silicon carbide (SiC) is a high-performance, wide-bandgap semiconductor material with broad application prospects. In the application of SiC devices, wafer defects are a crucial indicator affecting device performance, with dislocations being one of the most densely populated defect types. Therefore, dislocation density is an important indicator for SiC wafers. However, current methods primarily characterize dislocations on SiC wafers. Conventional non-destructive testing methods for SiC wafers, such as ultraviolet fluorescence, cannot clearly identify dislocation types. While synchrotron radiation can accurately identify dislocation types, it requires a synchrotron radiation source, resulting in high costs and limiting its mass production. Conventional alkaline etching creates pits on the SiC wafer surface, using the shape characteristics of these pits to distinguish and statistically analyze dislocations. However, as a destructive method, conventional alkaline etching targets SiC wafers after CMP (chemical mechanical polishing), increasing costs and hindering data acquisition for each individual SiC wafer. Summary of the Invention

[0003] To address the problem of dislocation statistics in each silicon carbide wafer, this invention provides a polishing method for silicon carbide wafers, comprising:

[0004] We provide coarsely or finely ground silicon carbide wafers;

[0005] The silicon carbide wafer is subjected to alkaline etching to obtain a silicon carbide wafer with etching pits.

[0006] A grayscale image of a silicon carbide wafer with etched pits is obtained by taking a picture under a microscope.

[0007] Adjusting the threshold of the grayscale image yields a dislocation map;

[0008] The dislocation map is then used to distinguish and statistically analyze dislocation types.

[0009] After the dislocation types are distinguished and statistically analyzed, the silicon carbide wafers are then subjected to subsequent polishing processes.

[0010] Optionally, the silicon carbide wafer is a 4H silicon carbide wafer or a 6H silicon carbide wafer.

[0011] Optionally, the alkaline corrosion is molten alkaline corrosion or alkaline vapor corrosion.

[0012] Optionally, the step of molten alkali etching of the silicon carbide wafer includes: taking a certain amount of strong alkali solid and placing it in a crucible and heating it to a set temperature so that the strong alkali solid forms molten alkali; immersing the silicon carbide wafer in the molten alkali to perform alkali etching on the silicon carbide wafer, forming etching pits on the silicon surface of the silicon carbide wafer; and cleaning and drying the silicon carbide wafer after alkali etching.

[0013] Optionally, the strong base solid is potassium hydroxide or sodium hydroxide.

[0014] Optionally, the set temperature range for forming molten alkali in the crucible is 450℃~600℃.

[0015] Optionally, the corrosion time range for alkaline corrosion is 5 minutes to 90 minutes.

[0016] Optionally, the threshold of the grayscale image obtained from the coarsely ground silicon carbide wafer can be adjusted in the range of 30-60.

[0017] Optionally, the threshold of the grayscale image obtained from the finely ground silicon carbide wafer can be adjusted in the range of 85-95.

[0018] The present invention also provides a method for polishing a semiconductor wafer, comprising:

[0019] Provides semiconductor wafers that have been coarsely or finely ground;

[0020] The semiconductor wafer is subjected to alkaline etching to obtain a semiconductor wafer with etching pits;

[0021] A grayscale image is obtained by taking a picture of a semiconductor wafer with etched pits under a microscope.

[0022] Adjusting the threshold of the grayscale image yields a dislocation map;

[0023] The dislocation map is then used to distinguish and statistically analyze dislocation types.

[0024] The semiconductor wafer, after dislocation characterization and statistical analysis, undergoes subsequent polishing processing.

[0025] In summary, the advantages and beneficial effects of the present invention are as follows:

[0026] This invention provides a polishing method for silicon carbide wafers and a polishing method for semiconductor wafers. A silicon carbide wafer, after rough or fine grinding, is provided. The silicon carbide wafer is then subjected to alkaline etching. The alkaline-etched silicon carbide wafer is photographed under a microscope to obtain a grayscale image. After adjusting the threshold of the grayscale image, a dislocation map is obtained. The dislocation map is then used to distinguish and statistically analyze dislocation types. Finally, the silicon carbide wafer with dislocation characterization and statistical analysis is subjected to subsequent polishing processes. This invention utilizes alkaline etching of silicon carbide wafers after rough or fine grinding during processing. The depth of dislocation etching pits on the silicon carbide wafer surface differs from the depth of etching pits formed by processing damage, resulting in varying contrast between the two types of pits. Dislocation etching pits have higher contrast, while processing damage pits have lower contrast. By adjusting the threshold of the grayscale image, low-contrast processing damage pits are eliminated through image processing, leaving only high-contrast dislocation etching pits. This ensures that the resulting dislocation image consists entirely of dislocation etching pits, facilitating manual identification and enabling computer software to read image information for dislocation type differentiation and statistical analysis. Adding an alkaline etching step to the silicon carbide wafer processing flow allows for accurate dislocation density statistics for each silicon carbide wafer without adding extra processing steps or increasing processing costs, enabling mass production and improving efficiency. Attached Figure Description

[0027] Figure 1 The diagram shows a flowchart of a polishing method for a silicon carbide wafer according to an embodiment of the present invention.

[0028] Figure 2 The diagram shown is a schematic diagram of a silicon carbide wafer after alkaline etching, representing a polishing method for silicon carbide wafers according to an embodiment of the present invention.

[0029] Figure 3 The diagram shown is a schematic of the silicon carbide wafer after alkaline etching, as part of a polishing method for a silicon carbide wafer in another embodiment.

[0030] Figure 4 The image shown is a grayscale diagram of a polishing method for a silicon carbide wafer according to an embodiment of the present invention.

[0031] Figure 5 The image shown is a grayscale image of a polishing method for a silicon carbide wafer in another embodiment;

[0032] Figure 6 The diagram shows a flowchart of a semiconductor wafer polishing method according to an embodiment of the present invention. Detailed Implementation

[0033] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0034] This invention provides a method for polishing silicon carbide wafers; please refer to [the relevant documentation]. Figure 1 ,include:

[0035] Step S10: Provide a silicon carbide wafer after coarse or fine grinding;

[0036] Step S20: The silicon carbide wafer is subjected to alkaline etching to obtain a silicon carbide wafer with etching pits.

[0037] Step S30: Place the silicon carbide wafer with etched pits under a microscope to take a picture and obtain a grayscale image;

[0038] Step S40: After adjusting the threshold of the grayscale image, a dislocation map is obtained;

[0039] Step S50: Dislocation type differentiation and statistics are performed on the dislocation map;

[0040] Step S60: The silicon carbide wafer after dislocation characterization and statistical analysis is subjected to subsequent polishing processing.

[0041] Specifically, step S10 is performed to provide a silicon carbide wafer after rough or fine grinding;

[0042] In this embodiment, the silicon carbide wafer is a 4H silicon carbide wafer or a 6H silicon carbide wafer.

[0043] In this embodiment, a finely ground silicon carbide wafer is provided; in other embodiments, a coarsely ground silicon carbide wafer is provided.

[0044] Step S20 is performed to etch the silicon carbide wafer with alkaline etching to obtain a silicon carbide wafer with etching pits.

[0045] In this embodiment, the alkaline corrosion is molten alkaline corrosion; in other embodiments, the alkaline corrosion is alkaline vapor corrosion.

[0046] In this embodiment, the step of molten alkali etching of the silicon carbide wafer includes: taking a certain amount of strong alkali solid and placing it in a crucible and heating it to a set temperature so that the strong alkali solid melts to form molten alkali; taking a silicon carbide wafer and immersing it in the molten alkali to perform alkali etching on the silicon carbide wafer, forming etching pits on the silicon surface of the silicon carbide wafer; and finally cleaning and drying the alkali-etched silicon carbide wafer.

[0047] In this embodiment, the strong alkali solid is potassium hydroxide; in other embodiments, the strong alkali solid is sodium hydroxide.

[0048] In this embodiment, the crucible is a nickel crucible.

[0049] The set temperature range for the formation of molten alkali in the crucible is 450℃~600℃, and the alkali corrosion time range is 5 minutes~90 minutes.

[0050] In this embodiment, the set temperature for forming the molten alkali is 550°C, and the alkali corrosion time is 15 minutes.

[0051] In other embodiments, the step of alkali vapor etching of the silicon carbide wafer includes: placing a certain amount of strong alkali solid at the bottom of a crucible; placing the silicon carbide wafer above the strong alkali solid in the crucible; heating the crucible to form alkali vapor from the strong alkali solid, and alkali vapor etching of the silicon carbide wafer to form corrosion pits on the surface of the silicon carbide wafer; and finally cleaning and drying the alkali-etched silicon carbide wafer.

[0052] After alkaline etching, corrosion pits are formed on the silicon surface of the silicon carbide wafer. The corrosion pits formed by dislocations and those formed by processing damage have different shapes, which is helpful for the dislocation statistics on the surface of the silicon carbide wafer.

[0053] In this embodiment, the etched silicon carbide wafer is cleaned and dried. The specific steps include rinsing the silicon carbide wafer repeatedly with deionized water and then drying the silicon carbide wafer with a nitrogen gun.

[0054] After alkaline etching is completed, the silicon carbide wafer is repeatedly rinsed with deionized water to remove any molten alkali residue adhering to the surface of the silicon carbide wafer.

[0055] In step S30, the silicon carbide wafer with etched pits is placed under a microscope to take a picture and obtain a grayscale image.

[0056] In this embodiment, please refer to Figure 2 After the finely ground silicon carbide wafer undergoes alkaline etching, based on the different shapes and depths of the etching pits, through-type screw dislocations, through-type edge dislocations, base plane dislocations, and processing damage can be clearly distinguished. Among them, large black etching pits are through-type screw dislocations, small black etching pits are through-type edge dislocations, etching pits with black edges and bright bottoms are base plane dislocations, and linear morphology indicates processing damage.

[0057] In other embodiments, please refer to Figure 3 After the coarsely ground silicon carbide wafers are etched with alkali, the large black corrosion pits are through-type screw dislocations, the small black corrosion pits are through-type edge dislocations, the corrosion pits with seed-shaped black edges are base plane dislocations, and the circular shallow corrosion pits and linear morphologies are processing damage.

[0058] After performing step S40, the threshold of the grayscale image is adjusted to obtain the dislocation image.

[0059] Adjust the threshold range of the grayscale image, which is 0-255.

[0060] In this embodiment, the silicon carbide wafer with a rough surface is a coarsely ground silicon carbide wafer, and the threshold value of the finely ground silicon carbide wafer is 85-95.

[0061] In other embodiments, the silicon carbide wafer with a rough surface is a finely ground silicon carbide wafer, and the threshold range of the coarsely ground silicon carbide wafer is 30-60.

[0062] In this embodiment, please refer to Figure 4 The threshold value of the grayscale image obtained from the finely ground silicon carbide wafer is specifically 90.

[0063] In other embodiments, please refer to Figure 5 The threshold value of the grayscale image obtained from the coarsely ground silicon carbide wafer is specifically 40.

[0064] After alkaline etching, both dislocations and processing damage form corrosion pits on the surface of silicon carbide wafers following rough or fine grinding. When directly using computers to distinguish and count dislocation types, the corrosion pits from processing damage significantly impact this process. Experiments have shown that the different depths of dislocation corrosion pits and processing damage corrosion pits on the silicon carbide wafer surface result in different contrasts: dislocation corrosion pits have higher contrast, while processing damage corrosion pits have lower contrast. By photographing the alkaline-etched silicon carbide wafer under a microscope to obtain a grayscale image, and then applying a threshold adjustment to this image, a corresponding dislocation map is obtained. The threshold adjustment eliminates low-contrast corrosion pits formed by processing damage, leaving only high-contrast dislocation corrosion pits in the resulting dislocation map. This ensures that all corrosion pits in the obtained dislocation map are indeed dislocation corrosion pits, facilitating manual identification and enabling computer software to read image information for dislocation type distinction and statistics.

[0065] Step S50 is executed to distinguish and count the dislocation types in the dislocation map.

[0066] Existing technologies utilize automated sample stages to obtain a large number of wafer images, then distinguish dislocation types and quantities to ultimately obtain the dislocation density distribution on the wafer. Statistical analysis of a single wafer can reach 30×30 or even 50×50 pixels, resulting in a massive data volume that cannot be manually processed and must rely on computer software. This invention achieves accurate type differentiation and statistical analysis of dislocations in silicon carbide wafers by adjusting the threshold of the grayscale image.

[0067] Step S60: The silicon carbide wafer after dislocation characterization and statistical analysis is subjected to subsequent polishing processing.

[0068] The depth of the etch pits on the surface of the silicon carbide wafer is in the range of a few micrometers, which is within the removal range of the standard polishing process. Therefore, the etch pits on the surface of the silicon carbide wafer can be completely removed in the subsequent polishing process, resulting in a smooth silicon carbide wafer, which can then be directly processed in subsequent steps.

[0069] In this embodiment, the finely ground silicon carbide wafer is directly subjected to CMP processing. In other embodiments, the coarsely ground silicon carbide wafer is first finely ground and then subjected to CMP processing.

[0070] Adding an alkaline etching step to the silicon carbide wafer processing flow allows for accurate dislocation density statistics for each silicon carbide wafer without adding extra processing steps or increasing processing costs, enabling mass production and improving efficiency.

[0071] This invention also provides a method for polishing semiconductor wafers; please refer to [reference needed]. Figure 6 ,include:

[0072] Step S100: Provide a semiconductor wafer after rough grinding or fine grinding;

[0073] Step S200: The semiconductor wafer is subjected to alkaline etching to obtain an alkaline etched semiconductor wafer;

[0074] Step S300: Place the alkaline-etched semiconductor wafer under a microscope to take a picture and obtain a grayscale image;

[0075] Step S400: Adjust the threshold of the grayscale image to obtain a dislocation map;

[0076] Step S500: Perform dislocation characterization and statistics on the dislocation map;

[0077] Step S600 involves performing subsequent polishing processing on the semiconductor wafer after dislocation characterization and statistical analysis.

[0078] In this embodiment of the invention, the semiconductor wafer is a silicon carbide wafer; in other embodiments, the semiconductor wafer is a silicon wafer, a sapphire wafer, or other suitable semiconductor wafer.

[0079] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the device structure and the technical solutions of the embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the device structure and the embodiments of the present invention.

Claims

1. A method of polishing a silicon carbide wafer, characterized by, The method comprises the following steps: providing a rough or fine ground silicon carbide wafer; alkali etching the silicon carbide wafer to obtain a silicon carbide wafer with etching pits; photographing the silicon carbide wafer with etching pits under a microscope to obtain a gray-scale image, the depth of dislocation etching pits on the surface of the silicon carbide wafer is different from the depth of etching pits formed by processing damage, so that the contrast of the dislocation etching pits and the processing damage etching pits is also different, the contrast of the dislocation etching pits is relatively high, and the contrast of the processing damage etching pits is relatively low; adjusting the threshold value of the gray-scale image to obtain a dislocation image, wherein, after the threshold value is adjusted, the etching pits with low contrast are excluded, and the dislocation etching pits with high contrast are left, so that all the etching pits in the obtained dislocation image are dislocation etching pits; carrying out dislocation type differentiation and statistics on the dislocation image, and realizing accurate dislocation density statistics of each silicon carbide wafer; carrying out subsequent polishing processing on the silicon carbide wafer after the dislocation type differentiation and statistics.

2. The method of claim 1 wherein the polishing composition further comprises a pH adjusting agent. The silicon carbide wafer is a 4H silicon carbide wafer or a 6H silicon carbide wafer.

3. The method of claim 1 wherein the polishing composition further comprises a pH adjuster. The alkali etching is molten alkali etching or alkali vapor etching.

4. The method of claim 3 wherein the polishing pad is a fixed abrasive pad. The step of molten alkali etching of the silicon carbide wafer comprises the following steps: taking a certain amount of strong alkali solid into a crucible and heating to a set temperature, so that the strong alkali solid forms a molten alkali; taking the silicon carbide wafer and immersing it in the molten alkali, alkali etching the silicon carbide wafer, and forming etching pits on the silicon surface of the silicon carbide wafer; and cleaning and drying the silicon carbide wafer after alkali etching.

5. A method of polishing a silicon carbide wafer as set forth in claim 4, wherein, The strong alkali solid is potassium hydroxide or sodium hydroxide.

6. The method of claim 4, wherein the polishing pad is a fixed abrasive pad. The set temperature for forming the molten alkali in the crucible ranges from 450 DEG C to 600 DEG C.

7. The method of claim 4 wherein the polishing composition further comprises a pH adjuster. The etching time of alkali etching ranges from 5 minutes to 90 minutes.

8. The method of claim 1 wherein the polishing composition further comprises a pH adjuster. The adjustment range of the threshold value of the gray-scale image obtained by rough grinding of the silicon carbide wafer is 30-60.

9. The method of claim 1 wherein the polishing composition further comprises a pH adjuster. The adjustment range of the threshold value of the gray-scale image obtained by fine grinding of the silicon carbide wafer is 85-95.

10. A method of polishing a semiconductor wafer, characterized by, The method comprises the following steps: providing a rough or fine ground semiconductor wafer; alkali etching the semiconductor wafer to obtain a semiconductor wafer with etching pits; photographing the semiconductor wafer with etching pits under a microscope to obtain a gray-scale image, the depth of dislocation etching pits on the surface of the semiconductor wafer is different from the depth of etching pits formed by processing damage, so that the contrast of the dislocation etching pits and the processing damage etching pits is also different, the contrast of the dislocation etching pits is relatively high, and the contrast of the processing damage etching pits is relatively low; adjusting the threshold value of the gray-scale image to obtain a dislocation image, wherein, after the threshold value is adjusted, the etching pits with low contrast are excluded, and the dislocation etching pits with high contrast are left, so that all the etching pits in the obtained dislocation image are dislocation etching pits; carrying out dislocation type differentiation and statistics on the dislocation image, and realizing accurate dislocation density statistics of each semiconductor wafer; carrying out subsequent polishing processing on the semiconductor wafer after the dislocation type differentiation and statistics.

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