Semiconductor element and method for producing the same

Abstract

This disclosure provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion, the second portion protruding from the first portion. The semiconductor device also includes a dielectric layer and a gate conductive layer, the dielectric layer being disposed on the second portion, and the second gate conductive layer being disposed on the dielectric layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 541,845 and 17 / 543,914 (i.e., priority dates of December 3, 2021 and December 7, 2021), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. In particular, it relates to a semiconductor device having a low gate height. Background Technology

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are commonly used in memory devices, including dynamic random-access memory (DRAM) devices. The fabrication technique of a MOSFET typically involves providing a gate structure on a semiconductor substrate to define a channel region; and forming source and drain regions on opposite sides of the channel region.

[0004] As DRAM device size shrinks, parasitic capacitances (such as peripheral capacitance, gate-to-thrust capacitance, and thrust-to-thrust capacitance) and parasitic resistances become significant, thus reducing device performance.

[0005] Furthermore, when reducing the channel length, a short-channel effect (such as a punch-through phenomenon) may occur. Due to the short-channel effect, a DRAM device may encounter problems with the gate not being able to fully control the on and off states of the channel region, and variations in electronic characteristics may occur.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion, the second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion; and a gate conductive layer disposed on the dielectric layer.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first surface and a second surface, the second surface protruding from the first surface of the substrate. The semiconductor device also includes a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate. The first spacer contacts the substrate and the gate oxide layer.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes disposing a dielectric layer on a substrate; disposing a gate conductive layer on the dielectric layer; and forming a surface of the substrate that is substantially coplanar with one side surface of the dielectric layer and one side surface of the gate conductive layer.

[0010] By forming a gate structure (including a gate conductive layer and a dielectric layer) on an elevated portion of a substrate, the height of the gate conductive layer is reduced, while the height of the gate structure remains substantially constant. Compared to an existing structure (e.g., where the gate structure is not elevated and the height of the gate conductive layer is large), this reduction in the height of the gate conductive layer avoids or reduces unnecessary parasitic capacitance. Furthermore, because the substrate has an elevated portion and the gate conductive layer is elevated, the effective channel length is increased and short-channel effects are reduced.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0013] Figure 1A This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0014] Figure 1B This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0015] Figure 1C This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0016] Figure 2A This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0017] Figure 2B This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0018] Figure 2C This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0019] Figure 2D This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0020] Figure 2E This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0021] Figure 2F This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0022] Figure 2G This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0023] Figure 2H This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0024] Figure 2I This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0025] Figure 2J This is a cross-sectional schematic diagram illustrating one or more stages in a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0026] Figure 3 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0027] The reference numerals in the attached figures are explained as follows:

[0028] 1: Semiconductor components

[0029] 1': Semiconductor element

[0030] 1”: Semiconductor components

[0031] 10: Base

[0032] 10a: Doped region

[0033] 10b: Doped region

[0034] 10c: Raised section

[0035] 11: Dielectric layer

[0036] 11': Dielectric layer

[0037] 12: Gate conductive layer

[0038] 12': Gate conductive layer

[0039] 12a: Sub-layer

[0040] 12b: Sublayer

[0041] 13: Covering layer

[0042] 14': Dielectric layer

[0043] 14: Spacer

[0044] 15: Gap element

[0045] 20': Hard mask

[0046] 20: Hard mask pattern

[0047] 30: Preparation method

[0048] 101: Surface

[0049] 101a: Part

[0050] 101b: Partial

[0051] 101c: Partial

[0052] 102: Surface

[0053] 111: Surface

[0054] 121: Surface

[0055] 131: Surface

[0056] H1: Height

[0057] H2: Height

[0058] S31: Steps

[0059] S32: Steps

[0060] S33: Steps

[0061] S34: Steps

[0062] S35: Steps

[0063] S36: Steps

[0064] S37: Steps Detailed Implementation

[0065] The various embodiments (or examples) of this disclosure described in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, are considered to be common practice for those skilled in the art to which this disclosure pertains. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0066] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0068] Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor element 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory (DRAM) cell.

[0069] In some embodiments, semiconductor element 1 may be or include part of an integrated circuit (IC) chip, which includes various passive or active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC elements, or combinations thereof.

[0070] When two MOSFETs are shown in the figure, it should be understood that semiconductor element 1 may be or include any suitable number of passive and active microelectronic elements as described.

[0071] As shown in FIG1, in some embodiments, the semiconductor element 1 may include a substrate 10, a dielectric layer 11, a gate conductive layer 12, a capping layer 13, and spacers 14 and 15.

[0072] In some embodiments, for example, the substrate 10 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (DOI) substrate.

[0073] Depending on the IC manufacturing stage, the substrate 10 may include different material layers (e.g., multiple dielectric layers, multiple semiconductor layers, and / or multiple conductive layers) configured to form IC features (e.g., multiple doped regions, multiple insulating features, multiple gate features, multiple source / drain features, multiple interconnect features, multiple other features, or combinations thereof).

[0074] For clarity, it has been simplified Figure 1A The base 10. It should be understood that additional features may be added to the base 10, and in other embodiments, some of the features described below may be replaced, modified, or eliminated.

[0075] In the described embodiments, the substrate 10 may include a surface 101 and a surface 102, with surface 102 disposed opposite to surface 101. In some embodiments, surface 101 may be an active surface, and surface 101 may be a rear surface of the substrate 10.

[0076] In some embodiments, surface 101 may include a portion 101a, a portion 101b, and a portion 101c. In some embodiments, portions 101a and 101c may not be coplanar. In some embodiments, portion 101a may protrude from portion 101c. In some embodiments, portion 101c may be recessed from portion 101a. In some embodiments, portions 101a and 101c may be generally parallel. In some embodiments, portion 101b may extend between portions 101a and 101c. In some embodiments, portion 101b may connect portions 101a and 101c. In some embodiments, portion 101b may be angled relative to portions 101a and / or 101c. In some embodiments, portion 101b may be generally perpendicular to portions 101a and / or 101c.

[0077] In some embodiments, surface 101 may define a stepped structure. For example, portions 101a, 101b, and 101c may define a stepped structure of substrate 10.

[0078] In some embodiments, portions 101a, 101b, and 101c may define a raised or elevated portion 10c of the substrate 10. In some embodiments, the raised portion 10c may be configured to raise or elevate a gate structure (including dielectric layer 11, gate conductive layer 12, and capping layer 13). For example, the gate structure (including dielectric layer 11, gate conductive layer 12, and capping layer 13) may be separated from a portion 101c of the surface 101 by the raised portion 10c.

[0079] In some embodiments, a channel region (not shown) may be formed in the substrate 10 beneath the dielectric layer 11, for example, in the raised portion 10c. In some embodiments, the channel region may be doped in the substrate 10. In some embodiments, the gate conductive layer 12 may be configured to influence or control a plurality of charge carriers in the channel region.

[0080] In some embodiments, the substrate 10 may have a doped region 10a and a doped region 10b disposed on or in the substrate 10. In some embodiments, the doped region 10a and the doped region 10b may be disposed on or near the surface 101 of the substrate 10.

[0081] In some embodiments, the doped region 10a may include a lightly doped region, such as a lightly doped drain (LDD) region. The doped region 10a may be adjacent to the channel region beneath the dielectric layer 11 and extend laterally away from the channel region. In some embodiments, for an NMOS device, the doped region 10a is doped with an N-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), and the channel region may be doped with a P-type dopant. In some other embodiments, for a PMOS device, the doped region 10a is doped with a P-type dopant (e.g., boron (B) or indium (In)), and the channel region may be doped with an N-type dopant.

[0082] In some embodiments, the doped region 10a may have a doping concentration lower than that of the doped region 10b. In some embodiments, the doped region 10a may be wider than the channel region beneath the dielectric layer 11. In some embodiments, the doped region 10a may reduce the electric field between the doped region 10b and the channel region and help minimize hot carrier effects.

[0083] In some embodiments, the doped region 10a may be at least partially exposed from the raised portion 10c of the substrate 10. For example, the doped region 10a may be at least partially exposed from portions 101a, 101b, and / or 101c of the surface 101 of the substrate 10.

[0084] In some embodiments, doped region 10b includes a heavily doped region. In some embodiments, doped region 10b may include a source region and / or a drain region. In some embodiments, doped region 10b may be disposed within doped region 10a. In some embodiments, doped region 10b may be surrounded by doped region 10a. In some embodiments, doped region 10b may be adjacent to doped region 10a. In some embodiments, the fabrication technique of doped region 10b may include implanting N-type (for NMOS devices) or P-type dopants (for PMOS devices) into substrate 10 by a doping degree significantly higher than that used for forming doped region 10a. Doped region 10a and doped region 10b may have the same doping type. In multiple regions where doped region 10b and doped region 10a overlap, the heavier doping degree of doped region 10b may overcome the lighter doping degree of doped region 10a. Therefore, a source region and / or a drain region may be formed in these overlapping regions.

[0085] In some embodiments, the doped region 10b may not be exposed from the raised portion 10c of the substrate 10, such as Figure 1A As shown. However, in some other embodiments, the doped region 10b may be at least partially exposed from the raised portion 10c of the substrate 10. For example, the doped region 10b may be at least partially exposed from portions 101a, 101b, and / or 101c of the surface 101 of the substrate 10.

[0086] In some embodiments, the dielectric layer 11 may be disposed on a portion 101a of the surface 101 of the substrate 10. For example, the dielectric layer 11 may contact the portion 101a of the surface 101 of the substrate 10. For example, the dielectric layer 11 may overlap with the portion 101a of the surface 101 of the substrate 10. In some embodiments, the dielectric layer 11 may be separated from the portion 101c of the surface 101 of the substrate 10. For example, the dielectric layer 11 may not contact the portion 101c of the surface 101 of the substrate 10.

[0087] In some embodiments, the dielectric layer 11 may have a surface (or one side surface) that is generally coplanar with a portion 101b of the surface 101 of the substrate 10.

[0088] In some embodiments, dielectric layer 11 may include a gate oxide layer. In some embodiments, for example, dielectric layer 11 may include hafnium silicate (HfSiO2). x Hafnium oxide (HfO2) and zirconium silicate (ZrSiO2) x The dielectric layer 11 may be a single layer, containing zirconium oxide (ZrO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxide (SiO2). In some embodiments, the dielectric layer 11 may have a single-layer structure. In some embodiments, the dielectric layer 11 may have a plurality of layers stacked thereon.

[0089] In some embodiments, the gate conductive layer 12 may be disposed on the dielectric layer 11. For example, the gate conductive layer 12 may contact the dielectric layer 11. In some embodiments, the gate conductive layer 12, the dielectric layer 11, and a portion 101a of the surface 101 of the substrate 10 may overlap. In some embodiments, the dielectric layer 11 may be disposed between the gate conductive layer 12 and a portion 101a of the surface 101 of the substrate 10. In some embodiments, the gate conductive layer 12 may be separated from a portion 101c of the surface 101 of the substrate 10. For example, the gate conductive layer 12 may not contact a portion 101c of the surface 101 of the substrate 10.

[0090] In some embodiments, the gate conductive layer 12 may have a surface (or one side surface) 121 that is generally coplanar with a portion 101b of the surface 101 of the substrate 10 and / or the surface 111 of the dielectric layer 11.

[0091] In some embodiments, the gate conductive layer 12 may include a gate electrode, a gate metal, or a gate conductor. In some embodiments, for example, the gate conductive layer 12 may include polysilicon (poly-Si), a metal (e.g., aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or a metal alloy. In some embodiments, for example, the gate conductive layer 12 may include a titanium-based material (e.g., titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), a tantalum-based material (e.g., tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or tantalum carbide (Ta2C)) or a silicide (e.g., PtSi, TiSi2, CoSi, NiSi, MoSi2, TaSi, WSi2, etc.). In some embodiments, the gate conductive layer 12 may include, for example, polysilicon (poly-Si), a metal (e.g., aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.). Figure 1A The structure shown is a single-layer structure or a multi-layer structure (which will be described below in relation to...) Figure 1B (Describe it).

[0092] In some embodiments, a capping layer 13 may be disposed on the gate conductive layer 12. For example, the capping layer 13 may contact the gate conductive layer 12. In some embodiments, the capping layer 12, the dielectric layer 11, and a portion 101a of the surface 101 of the substrate 10 may overlap. In some embodiments, the gate conductive layer 12 may be disposed between the dielectric layer 11 and the capping layer 13. In some instances, the capping layer 13 may be separated from a portion 101c of the surface 101 of the substrate 10. For example, the capping layer 13 may not contact a portion 101c of the surface 101 of the substrate 10.

[0093] In some embodiments, the cover layer 13 may have a surface (or a side surface) 131 that is generally coplanar with a portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11 and / or the surface 121 of the gate conductive layer 12.

[0094] In some embodiments, the capping layer 13 may include a gate-on-insulator. In some embodiments, for example, the capping layer 13 may include Si3N4, SiON, or SiO2. In some embodiments, for example, the capping layer 13 may include a titanium-based material (e.g., titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), a tantalum-based material (e.g., tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), or tantalum carbide (Ta2C)) or a silicide (e.g., PtSi, TiSi2, CoSi, NiSi, MoSi2, TaSi, WSi2, etc.).

[0095] In some embodiments, the spacer 14 may be disposed on a portion 101c of the surface 101 of the substrate 10. In some embodiments, the spacer 14 may contact the portion 101c of the surface 101 of the substrate 10, the portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11, the surface 121 of the gate conductive layer 12, and / or the surface 131 of the capping layer 13. In some embodiments, the spacer 14 may not contact the portion 101a of the surface 101 of the substrate 10.

[0096] In some embodiments, the spacer 14 may cover, seal, or encapsulate the gate structure (including dielectric layer 11, gate conductive layer 12, and capping layer 13) on the substrate 10. In some embodiments, the spacer 14 may extend between the capping layer 13 and a portion 101c of the surface 101 of the substrate 10.

[0097] In some embodiments, spacer 15 may be disposed on a portion 101c of the surface 101 of the substrate 10. In some embodiments, spacer 15 may contact a portion 101c of the surface 101 of the substrate 10. In some embodiments, spacer 15 may contact spacer 14.

[0098] In some embodiments, spacer 14 may be disposed between spacer 15 and a portion 101b of surface 101 of substrate 10. In some embodiments, spacer 14 may be disposed between spacer 15 and a portion 101a of surface 101 of substrate 10. In some embodiments, spacer 14 may be disposed between spacer 15 and surface 111 of dielectric layer 11. In some embodiments, spacer 14 may be disposed between spacer 15 and surface 121 of gate conductive layer 12. In some embodiments, spacer 14 may be disposed between spacer 15 and surface 131 of capping layer 13.

[0099] In some embodiments, for example, spacers 14 and 15 may comprise nitrides, oxides, or oxynitrides. Examples of spacer materials may include, but are not limited to, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxide (SiO2), tetraethyl orthosilicate (TEOS), carbonitride-doped elements, or carbonitride-doped elements without oxides.

[0100] In some embodiments, the gate conductive layer 12 may have a height H1. The height H1 can be measured in a direction that is generally perpendicular to a portion 101a of the surface 101 of the substrate 10. The height H1 may be defined between an upper surface (contact cap layer 13) of the gate conductive layer 12 and a lower surface (contact dielectric layer 11) of the gate conductive layer 12. The height H1 may be defined by the surface 12 of the gate conductive layer 12.

[0101] In some embodiments, the raised portion 10c of the substrate 10 may have a height H2. The height H2 can be measured in a direction that is substantially perpendicular to a portion 101a of the surface 101 of the substrate 10. The height H2 may be defined between the portion 101a and the portion 101c of the surface 101 of the substrate 10. The height H2 may be defined by a portion 101b of the surface 101 of the substrate 10.

[0102] In some embodiments, the height H1 of the gate conductive layer 12 may be different from the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the height H1 of the gate conductive layer 12 may be greater than the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the height H1 of the gate conductive layer 12 may be less than the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the ratio of height H1 to height H2 may be between approximately 3:2 and approximately 9:1.

[0103] When the size of DRAM devices (e.g., semiconductor device 1) is reduced, and parasitic capacitances (e.g., peripheral capacitance, gate-to-thrust capacitance, and thrust-to-thrust capacitance) and parasitic resistance become significant, device performance is reduced. Furthermore, when the channel length is reduced, short-channel effects (e.g., a punch-through phenomenon) may occur. Due to the short-channel effect, a DRAM device (e.g., a DRAM element) may encounter problems with insufficient control over the on / off states of the channel region via the gate (e.g., gate conductive layer 12), and variations in electronic characteristics may occur.

[0104] According to some embodiments of this disclosure, a gate structure (including a dielectric layer 11, a gate conductive layer 12, and a capping layer 13) is disposed on a raised portion 10c of a substrate 10. Therefore, the gate conductive layer 12 is raised, and the height H1 of the gate conductive layer 12 can be reduced, while the total height of the gate structure (e.g., the total height measured from a portion 101c of surface 101 to the uppermost surface of the gate structure) remains substantially constant.

[0105] Compared to an existing structure (e.g., the gate conductive layer is not raised and the height of the gate conductive layer is large), the reduced height of the gate conductive layer 12 can avoid or reduce unnecessary parasitic capacitance.

[0106] Furthermore, since the substrate 10 has a raised portion 10c and the gate conductive layer 12 is raised, the effective channel length in the channel region below the dielectric layer 11 is increased, and the short-channel effect can be eliminated.

[0107] Figure 1B This is a cross-sectional schematic diagram illustrating a semiconductor element 1' of some embodiments of the present disclosure. Figure 1B The semiconductor element 1' is similar to Figure 1A Semiconductor element 1, except for the differences described below.

[0108] exist Figure 1B In this semiconductor device 1', the gate conductive layer 12 may include a multilayer structure. For example, the gate conductive layer 12 of the semiconductor device 1' may include a sublayer 12a and a sublayer 12b.

[0109] In some embodiments, sublayer 12a may be disposed on sublayer 12b. For example, sublayer 12a may contact sublayer 12b. In some embodiments, sublayer 12a may be disposed between sublayer 12b and capping layer 13. In some embodiments, for example, sublayer 12a may include polysilicon.

[0110] In some embodiments, sublayer 12b may be disposed on dielectric layer 11. In some embodiments, sublayer 12b may contact dielectric layer 11. In some embodiments, sublayer 12b may be disposed between dielectric layer 11 and sublayer 12a. In some embodiments, for example, sublayer 12b may include a metal (e.g., Al, Mg, W, La, etc.) or a metal alloy.

[0111] In some embodiments, the height H1 of the gate conductive layer 12 (including sublayers 12a and 12b) may be different from the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the height H1 of the gate conductive layer 12 (including sublayers 12a and 12b) may be greater than the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the height H1 of the gate conductive layer 12 (including sublayers 12a and 12b) may be less than the height H2 of the raised portion 10c of the substrate 10. In some embodiments, the ratio of height H1 to height H2 may be between approximately 3:2 and approximately 9:1.

[0112] Figure 1C This is a cross-sectional schematic diagram illustrating a semiconductor element 1 according to some embodiments of the present disclosure. Figure 1C Semiconductor element 1” is similar to Figure 1A Semiconductor element 1, except for the differences described below.

[0113] exist Figure 1C In the semiconductor element 1”, the doped region 10a is separated from the raised portion 10c of the substrate 10. For example, the doped region 10a of the semiconductor element 1” is not exposed from portions 101a and / or 101b of the surface 101 of the substrate 10.

[0114] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J These are cross-sectional schematic diagrams illustrating various stages in the fabrication methods of semiconductor devices according to some embodiments of the present disclosure. At least some of these diagrams have been simplified to better understand the purposes of this disclosure. In some embodiments, in Figure 1A Semiconductor element 1 in Figure 1B Semiconductor element 1' in and in Figure 1C Semiconductor element 1 in the middle can be obtained by means of the corresponding following description Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J Manufactured.

[0115] Please refer to Figure 2A A substrate 10 is provided. In some embodiments, a plurality of shallow trench isolation (STI) regions (not shown) may be formed in the substrate 10, for example, using lithography, etching, deposition, and chemical mechanical planarization (CMP) processes, to electrically insulate them from the MOSFETs subsequently formed.

[0116] In some embodiments, a dielectric layer 11' may be disposed on the surface 101 of the substrate 10. In some embodiments, the fabrication technique of the dielectric layer 11' may include a thermal oxidation operation. In some other embodiments, for example, the dielectric layer 11' may be fabricated via chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), other feasible operations, or combinations thereof.

[0117] In some embodiments, a gate conductive layer 12' may be disposed on the dielectric layer 11'. In some embodiments, the gate conductive layer 12' may be a polysilicon layer, the fabrication technique of which includes depositing undoped polysilicon and then doping it with impurities by ion implantation. In some other embodiments, the gate conductive layer 12' may include a multilayer structure. For example, the fabrication technique of the gate conductive layer 12' may include atomic layer deposition (ALD), physical vapor deposition (PVD), CVD, a siliconization process, other feasible operations, or combinations thereof.

[0118] In some embodiments, a hard mask 20' may be deposited on the gate conductive layer 12'. In some embodiments, the hard mask 20' may include Si3N4, SiON, SiO2, or TiN. In some embodiments, for example, the hard mask 20' may be formed via CVD, LPCVD, PECVD, other feasible operations, or combinations thereof.

[0119] Please refer to Figure 2B The hard mask 20' can be patterned using lithography and etching processes to form a hard mask pattern 20. The dielectric layer 11' and the gate conductive layer 12' can be patterned sequentially by etching using the hard mask pattern 20 as an etching mask. Therefore, the dielectric layer 11 and the gate conductive layer 12 can be formed.

[0120] In some embodiments, the dielectric layer 11' and the gate conductive layer 12' may be etched anisotropically. In some embodiments, the dielectric layer 11' and the gate conductive layer 12' may be etched using the same operation. In some embodiments, the dielectric layer 11' and the gate conductive layer 12' may be etched using different operations. For example, the dielectric layer 11' and the gate conductive layer 12' may be etched using, for example, reactive ion etching (RIE) with different chemical properties.

[0121] In some embodiments, after the dielectric layer 11 and the gate conductive layer 12 are formed, the surface (or one side surface) 111 of the dielectric layer 11 may be coplanar with the surface (or one side surface) 121 of the gate conductive layer 12.

[0122] Please refer to Figure 2C The substrate 10 can be patterned by etching using a hard mask pattern 20 as an etching mask. Thus, the raised portion 10c can be formed.

[0123] In some embodiments, the substrate 10 may be anisotropically etched. In some embodiments, the substrate 10 may be different from... Figure 2A The dielectric layer 11' and the gate conductive layer 12' are etched using an operation. For example, the substrate 10 can be etched using a RIE having a chemical property different from that of the dielectric layer 11' and the gate conductive layer 12'.

[0124] In some embodiments, after the raised portion 10c is formed, a portion 101a of the surface 101 of the base 10 may protrude from the portion 101c of the surface 101 of the base 10.

[0125] In some embodiments, a portion 101b of the surface 101 of the substrate 10 may be substantially coplanar with the surface 111 of the dielectric layer 11 and / or the surface 121 of the gate conductive layer 12.

[0126] Please refer to Figure 2DFor example, the hard mask pattern 20 can be removed by an etching process.

[0127] Please refer to Figure 2E The capping layer 13 may be deposited on the gate conductive layer 12. In some other embodiments, the fabrication techniques of the capping layer 13 may include ALD, PVD, CVD, a siliconization process, other feasible operations, or combinations thereof. In some embodiments, for example, the capping layer 12 may be partially removed by an etching process.

[0128] In some embodiments, the surface (or one side surface) 131 of the cover layer 13 may be substantially coplanar with a portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11 and / or the surface 121 of the gate conductive layer 12.

[0129] Please refer to Figure 2F A dielectric layer 14' may be disposed on a gate structure (including a dielectric layer 11, a gate conductive layer 12, and a capping layer 13) on a substrate 10. In some embodiments, for example, the dielectric layer 14' may be formed via CVD, LPCVD, PECVD, other feasible operations, or combinations thereof. In some embodiments, the dielectric layer 14' may cover portions 101b and 101c of the surface 101 of the substrate 10. In some embodiments, the dielectric layer 14' may cover the surface 111 of the dielectric layer 11, the surface 121 of the gate conductive layer 12, and the surface 131 of the capping layer 13.

[0130] Please refer to Figure 2G A doped region 10a may be formed in the substrate 10. In some embodiments, for example, the fabrication technique of the doped region 10a may include an ion implantation operation, such as plasma-immersion ion implantation, solid-state diffusion, etc. In some embodiments, an annealing process may be performed to remove damage and / or lattice defects caused by implantation. In these embodiments, the dielectric layer 14' may prevent multiple dopants from penetrating into the substrate 10. Therefore, the doped region 10a may have a doping concentration lower than that of the subsequently formed doped region 10b.

[0131] In some other embodiments, a blanket light ion implantation operation may be performed to form the doped region 10a prior to the formation of the dielectric layer 14'.

[0132] Please refer to Figure 2H The dielectric layer 14' can be anisotropically etched to form spacers 14. After the etching operation, a portion 101c of the surface 101 of the capping layer 13 and the substrate 10 can be exposed.

[0133] Please refer to Figure 2I The spacer 15 may be disposed on a portion 101c of the surface 101 of the substrate 10. In some embodiments, for example, the fabrication technique of the spacer 15 may include CVD, LPCVD, PECVD, other feasible operations, or combinations thereof. Then, an etching operation (e.g., RIE) may be performed to remove a portion of the spacer 15 and expose a portion 101c of the surface 101 of the substrate 10.

[0134] Please refer to Figure 2J The doped region 10b may be formed in the substrate 10. In some embodiments, for example, the fabrication technique of the doped region 10b may include an ion implantation operation, such as plasma-immersion ion implantation, solid-state diffusion, etc. In some embodiments, the doped region 10b may be formed by etching using a spacer 15 as an ion implantation mask.

[0135] In some embodiments, the fabrication technique of the doped region 10b may include implanting an N-type (for NMOS devices) or P-type dopant (for PMOS devices) into the substrate 10 by means of a doping degree significantly higher than that used for forming the doped region 10a. In multiple regions where the doped region 10b overlaps with the doped region 10a, the heavier doping degree of the doped region 10b can overcome the lighter doping degree of the doped region 10a. Therefore, a source region and / or a drain region may be formed in these overlapping regions.

[0136] Figure 3 This is a flowchart illustrating a method 30 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0137] In some embodiments, the fabrication method 30 may include a step S31, which involves depositing a dielectric layer on a substrate. For example, such as Figure 2A As shown, the dielectric layer 11' can be disposed on the surface 101 of the substrate 10.

[0138] In some embodiments, the fabrication method 30 may include a step S32, which involves depositing a gate conductive layer on the dielectric layer. For example, such as Figure 2A As shown, the gate conductive layer 12' can be disposed on the dielectric layer 11'.

[0139] In some embodiments, the fabrication method 30 may include a step S33, forming a surface of the substrate so as to be coplanar with one side surface of the dielectric layer and one side surface of the gate conductive layer. For example, such as Figure 2C As shown, a portion 101b of the surface 101 of the substrate 10 may be substantially coplanar with the surface 111 of the dielectric layer 11 and / or the surface 121 of the gate conductive layer 12.

[0140] In some embodiments, the fabrication method 30 may include a step S34, which involves setting a first spacer on the surface of the substrate, the side surface of the dielectric layer, and the side surface of the gate conductive layer. For example, such as Figure 2H As shown, the spacer 14 can be disposed on the surface 111 of the dielectric layer 11, the surface 121 of the gate conductive layer 12, and the surface 131 of the capping layer 13.

[0141] In some embodiments, preparation method 30 may include a step S35, forming a lightly doped region in the substrate. For example, such as Figure 2G As shown, the doped region 10a can be formed in the substrate 10.

[0142] In some embodiments, the preparation method 30 may include a step S36, which involves providing a second spacer on the surface of the substrate. For example, such as Figure 2I As shown, the spacer 15 can be disposed on a portion 101c of the surface 101 of the substrate 10.

[0143] In some embodiments, preparation method 30 may include a step S37, forming a heavily doped region in the substrate. For example, such as Figure 2J As shown, the doped region 10b can be formed in the substrate 10.

[0144] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion, the second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion; and a gate conductive layer disposed on the dielectric layer.

[0145] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first surface and a second surface, the second surface protruding from the first surface of the substrate. The semiconductor device also includes a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate. The first spacer contacts the substrate and the gate oxide layer.

[0146] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes disposing a dielectric layer on a substrate; disposing a gate conductive layer on the dielectric layer; and forming a surface of the substrate that is substantially coplanar with one side surface of the dielectric layer and one side surface of the gate conductive layer.

[0147] By forming a gate structure (including a gate conductive layer and a dielectric layer) on an elevated portion of a substrate, the height of the gate conductive layer is reduced, while the height of the gate structure remains substantially constant. Compared to an existing structure (e.g., where the gate structure is not elevated and the height of the gate conductive layer is large), this reduction in the height of the gate conductive layer avoids or reduces unnecessary parasitic capacitance. Furthermore, because the substrate has an elevated portion and the gate conductive layer is elevated, the effective channel length is increased and short-channel effects are reduced.

[0148] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0149] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate having a surface, wherein the surface has a first portion, a second portion and a third portion, the second portion protruding from the first portion and the third portion extending between the first portion and the second portion; A dielectric layer is disposed on the second part; A gate conductive layer is disposed on the dielectric layer; as well as A first spacer contacts the third portion of the surface of the substrate.

2. The semiconductor element of claim 1, wherein the first portion and the second portion are substantially parallel.

3. The semiconductor device of claim 1, wherein one side surface of the dielectric layer is substantially coplanar with one side surface of the gate conductive layer.

4. The semiconductor element of claim 3, wherein the third portion is substantially coplanar with the side surface of the dielectric layer and the side surface of the gate conductive layer.

5. The semiconductor element of claim 4, wherein the first spacer further contacts the side surface of the dielectric layer and the side surface of the gate conductive layer.

6. The semiconductor element of claim 1, wherein the first spacer further contacts the first portion of the surface of the substrate.

7. The semiconductor device of claim 1 further includes a second spacer contacting the first spacer.

8. The semiconductor element of claim 7, wherein the second spacer further contacts the first portion of the surface of the substrate.

9. The semiconductor element of claim 7, wherein the first spacer is disposed between the third portion of the surface of the substrate and the second spacer.

10. The semiconductor device of claim 1 further includes a capping layer disposed on the gate conductive layer.

11. The semiconductor element of claim 10, wherein the first spacer extends between the capping layer and the first portion of the surface of the substrate.

12. The semiconductor device of claim 1, further comprising a lightly doped region partially exposed from the first portion of the surface of the substrate.

13. The semiconductor device of claim 12, further comprising a heavily doped region disposed in the lightly doped region and partially exposed from the first portion of the surface of the substrate.

14. A method for fabricating a semiconductor device, comprising: A dielectric layer is disposed on a substrate; A gate conductive layer is disposed on the dielectric layer; A surface of the substrate is formed to be substantially coplanar with one side surface of the dielectric layer and one side surface of the gate conductive layer; and A first spacer is deposited on the surface of the substrate, the side surface of the dielectric layer, and the side surface of the gate conductive layer.

15. The preparation method of claim 14 further includes depositing a capping layer on the gate conductive layer.

16. The preparation method of claim 14 further comprises forming a lightly doped region in the substrate.

17. The preparation method of claim 16, further comprising providing a second spacer on the surface of the substrate.

18. The preparation method of claim 17 further comprises forming a heavily doped region in the substrate.

19. A semiconductor element, comprising: A substrate having a first surface, a second surface and a third surface, the second surface protruding from the first surface of the substrate; A gate oxide layer is disposed on the second surface of the substrate; and A first spacer is disposed on the first surface of the substrate and contacts the substrate and the gate oxide layer. The third surface extends between the first surface and the second surface of the substrate, and the first spacer contacts the third surface of the substrate.

20. The semiconductor device of claim 19, wherein the gate oxide layer is separated from the first surface of the substrate.

21. The semiconductor device of claim 19, wherein the first surface of the substrate is substantially parallel to the second surface of the substrate.

22. The semiconductor device of claim 19, wherein one side surface of the gate oxide layer is substantially coplanar with a third surface of the substrate.

23. The semiconductor device of claim 19 further includes a gate conductive layer disposed on the gate oxide layer, wherein the first spacer also contacts the gate conductive layer.

24. The semiconductor device of claim 23, further comprising a capping layer disposed on the gate conductive layer, wherein the first spacer extends between the capping layer and the first surface of the substrate.

25. The semiconductor element of claim 19, further comprising a second spacer contacting the first spacer.

26. The semiconductor element of claim 25, wherein the second spacer is disposed on the first surface of the substrate.

27. The semiconductor device of claim 25, wherein the first spacer is disposed between the gate oxide layer and the second spacer.

28. The semiconductor device of claim 25, further comprising a lightly doped region exposed from the first surface portion of the substrate and contacting the first spacer and the second spacer.

29. The semiconductor device of claim 28, wherein the lightly doped region is exposed from the second surface portion of the substrate.

30. The semiconductor device of claim 28, further comprising a heavily doped region disposed in the lightly doped region and exposed from the first surface portion of the substrate.

31. A method for fabricating a semiconductor device, comprising: A substrate is provided having a first surface, a second surface and a third surface, the second surface protruding from the first surface of the substrate; A gate oxide layer is formed on the second surface of the substrate; and A first spacer is formed on the first surface of the substrate and contacts the substrate and the gate oxide layer. The third surface extends between the first surface and the second surface of the substrate, and the first spacer contacts the third surface of the substrate.

32. The preparation method of claim 31 further includes forming a gate conductive layer on the gate oxide layer, wherein the first spacer also contacts the gate conductive layer.

33. The preparation method of claim 32 further includes forming a capping layer on the gate conductive layer, wherein the first spacer extends between the capping layer and the first surface of the substrate.

34. The preparation method of claim 31 further includes forming a second spacer to contact the first spacer.

35. The preparation method of claim 34, wherein the second spacer is on the first surface of the substrate.

36. The preparation method of claim 34, wherein the first spacer is between the gate oxide layer and the second spacer.

37. The preparation method of claim 34, further comprising forming a lightly doped region that exposes and contacts the first spacer and the second spacer from the first surface portion of the substrate.

38. The preparation method of claim 37, further comprising forming a heavily doped region in the lightly doped region and exposing it from the first surface portion of the substrate.

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