GaN HEMT devices with substrate leakage suppression structure and fabrication method
By forming reverse PN junctions of P+ and N+ doped regions in the buffer layer, the leakage path is isolated, solving the leakage path problem of GaN HEMTs devices under high voltage and improving the reliability and performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2023-03-07
- Publication Date
- 2026-07-03
AI Technical Summary
GaN HEMTs devices have a buffer layer leakage channel problem under high voltage, which leads to increased leakage current and may cause premature device breakdown.
A first P+ type doped region and a first N+ type doped region are formed in the buffer layer to form a reverse PN junction to isolate the leakage channel. The reverse bias of the pn junction isolates the conductive channel and suppresses the conduction of the buffer layer below the drain.
It effectively suppresses the leakage current path of the buffer layer, avoids the aggravation of leakage current, improves the reliability of the device, prevents premature breakdown of the device, and enhances the performance of the device.
Smart Images
Figure CN116247094B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and more particularly to GaN HEMT devices and fabrication methods having a substrate leakage suppression structure. Background Technology
[0002] Gallium nitride (GaN) is known as a third-generation wide-bandgap semiconductor and a new generation of power semiconductors. Compared to the previous two generations of semiconductor materials, it has higher performance parameters and is more likely to meet the new requirements of high-power, high-temperature, and harsh environment applications. In power electronics applications, AlGaN / GaN heterostructures, due to their strong polarization effect, form quantum potential wells at the interface, generating a two-dimensional electron gas (2DEG) with high electron mobility and high density. The main characteristics of power semiconductor devices are high voltage withstand capability and high current. The current limitations of Si materials are not only in the high-frequency field, but also in high-voltage power devices, where its on-resistance is higher than that of materials such as GaN, thus greatly reducing power density and device switching characteristics. GaNHEMTs, on the other hand, exhibit better high-voltage and low-resistance characteristics under high voltage. Therefore, improving the stability of GaN HEMTs under high voltage is a key research issue.
[0003] Damage generated during crystal growth, such as nitrogen vacancies, line dislocations, and unintentionally introduced impurities like oxygen and silicon, can exist in the buffer layer of GaN HEMTs. When a large voltage is applied to the device drain, electrons can pass through the buffer layer under the influence of an increasingly strong vertical electric field, creating leakage current channels. This exacerbates the leakage current and can lead to premature device breakdown in severe cases.
[0004] Therefore, developing a novel GaN HEMT device that can suppress substrate leakage has become a key technical challenge that needs to be addressed by those skilled in the art. Summary of the Invention
[0005] This invention provides a GaN HEMT device and fabrication method with a substrate leakage current suppression structure to solve the problem of leakage current amplification caused by leakage channels generated in the buffer layer.
[0006] According to a first aspect of the present invention, a GaN HEMT device having a substrate leakage suppression structure is provided, comprising:
[0007] A substrate, and a buffer layer formed on the substrate;
[0008] A first P+ type doped region and a first N+ type doped region; wherein, the first P+ type doped region is formed in the buffer layer and does not contact the substrate; the first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region;
[0009] A GaN HEMT structure is formed at the top of the buffer layer; wherein the GaN HEMT structure includes a gate metal layer and a drain metal layer; the gate metal layer and the drain metal layer are arranged in a horizontal direction;
[0010] The first N+ type doped region covers the area below the drain metal layer and extends to the first doped region; the first doped region characterizes the area below the gate metal layer and the drain metal layer.
[0011] Optionally, the first P+ type doped region is doped with magnesium ions, and the first N+ type doped region is doped with silicon ions.
[0012] Optionally, the doping concentration in the first P+ type doped region is 1*102 17 ~2*10 17 cm⁻³; The doping concentration of the first N+ type doped region is 2*10⁻³ cm⁻³. 18 ~6*10 18 cm-3.
[0013] Optionally, the GaN HEMT structure further includes:
[0014] A channel layer and a barrier layer are formed sequentially on the buffer layer in a vertical direction; wherein the channel layer covers the first P+ type doped region, the first N+ type doped region, and part of the surface of the buffer layer.
[0015] A source metal layer and a first p-GaN layer are formed on the surface of the barrier layer. The source metal layer, the gate metal layer, and the drain metal layer are arranged sequentially in a horizontal direction. The first p-GaN layer is formed between the gate metal layer and the barrier layer to expose part of the barrier layer.
[0016] The first p-GaN layer is doped with magnesium ions, which are activated by annealing.
[0017] Optionally, only the first p-GaN layer includes magnesium ions activated by laser selective annealing.
[0018] Optionally, the GaN HEMT structure further includes:
[0019] A second p-GaN layer is formed on the exposed surface of the barrier layer; wherein the magnesium ions doped in the second p-GaN layer are not activated by laser annealing.
[0020] Optionally, GaN HEMT devices with substrate leakage suppression structures also include:
[0021] A gate metal interconnect layer, a source metal interconnect layer, and a drain metal interconnect layer; the gate metal interconnect layer, the source metal interconnect layer, and the drain metal interconnect layer are respectively formed on top of the gate metal layer, the source metal layer, and the drain metal layer;
[0022] A passivation layer is provided, which fills the voids between the gate metal interconnect layer, the source metal interconnect layer, and the drain metal interconnect layer.
[0023] A gate field plate is formed at the top of the passivation layer between the gate metal layer and the drain metal layer, and is connected to the gate metal interconnect layer.
[0024] Optionally, the GaN HEMT device with a substrate leakage suppression structure further includes:
[0025] A plurality of isolation layers; the plurality of isolation layers are formed on both sides of the GaN HEMT structure along the horizontal direction and penetrate the second p-GaN layer, the barrier layer, the channel layer and part of the buffer layer.
[0026] Optionally, the substrate is made of Si, the channel layer is made of GaN, the barrier layer is made of AlGaN, the passivation layer is made of Al2O3, and the buffer layer is made of AlGaN.
[0027] According to a second aspect of the present invention, a method for fabricating a GaN HEMT device having a substrate leakage suppression structure is provided, for fabricating the GaN HEMT device having a substrate leakage suppression structure as described in any one of the first aspects of the present invention, comprising:
[0028] Provide a substrate, and form the buffer layer on the substrate;
[0029] The first P+ type doped region and the first N+ type doped region are formed; wherein, the first N+ type doped region is formed in a portion of the buffer layer and does not contact the substrate; the first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region;
[0030] The GaN HEMT structure is formed at the top of the buffer layer; wherein the GaN HEMT structure includes a gate metal layer and a drain metal layer; the gate metal layer and the drain metal layer are arranged in a horizontal direction.
[0031] The first N+ type doped region covers the area below the drain metal layer and extends into the first doped region.
[0032] Optionally, forming the first P+ type doped region and the first N+ type doped region specifically includes:
[0033] A portion of the buffer layer is p-type heavily doped to form the first p+ type doped region;
[0034] A first hard mask layer is formed; the first hard mask layer covers the remaining undoped buffer layer and the surface of a portion of the first P+ type doped region to expose a portion of the first P+ type doped region beneath the drain metal layer;
[0035] The surface of the exposed first P+ type doped region is heavily doped with N-type to form the first P+ type doped region;
[0036] Remove the first hard mask layer.
[0037] Optionally, forming the GaN HEMT structure specifically includes:
[0038] The channel layer, the barrier layer, and the p-GaN material layer are formed; the channel layer, the barrier layer, and the p-GaN material layer are stacked sequentially on the surface of the buffer layer in a vertical direction, and cover the first P+ type doped region and the first N+ type doped region.
[0039] The first p-GaN layer, the source metal layer, and the drain metal layer are formed.
[0040] The gate metal layer is formed.
[0041] Optionally, forming the first p-GaN layer, the source metal layer, and the drain metal layer specifically includes:
[0042] The p-GaN material layer is etched at both ends along the horizontal direction to expose part of the barrier layer in order to form the first p-GaN layer;
[0043] The source metal layer and the drain metal layer are formed on the exposed surface of the barrier layer, and the source metal layer and the drain metal layer are sequentially formed on both sides of the first p-GaN layer along the horizontal direction.
[0044] Optionally, forming the first p-GaN layer, the source metal layer, and the drain metal layer specifically includes: performing laser selective annealing only on the p-GaN material layer in the gate region to form the first p-GaN layer, and forming the second p-GaN layer on the remaining portion of the p-GaN material layer;
[0045] The second p-GaN layer is etched in portions of the source and drain regions to form a first aperture and a second aperture;
[0046] The first opening is filled with metal material to form the source metal layer, and the second opening is filled with metal material to form the drain metal.
[0047] Optionally, when performing laser selective annealing on the p-GaN material layer in the gate region, the laser wavelength used is 300-600nm, the laser energy is 300W-1200W, and the laser spot size is 1µm-0.5mm.
[0048] Optionally, after forming the channel layer, the barrier layer, and the p-GaN material layer, the method further includes:
[0049] The plurality of isolation layers are formed; the plurality of isolation layers penetrate the p-GaN material layer, the barrier layer, the channel layer and the ends of part of the buffer layer.
[0050] Optionally, after forming the gate metal layer, the method further includes:
[0051] The gate metal interconnect layer, the source metal interconnect layer, the drain metal interconnect layer, and the passivation layer are formed.
[0052] The gate field plate is formed.
[0053] According to a third aspect of the present invention, a semiconductor device is provided, utilizing the GaN HEMT device having a substrate leakage suppression structure as described in any of the first aspects of the present invention.
[0054] According to a fourth aspect of the present invention, an electronic device is provided, comprising the semiconductor device described in the third aspect of the present invention.
[0055] According to a fifth aspect of the present invention, a method for fabricating a semiconductor device is provided, utilizing the method for fabricating a GaN HEMT device having a substrate leakage suppression structure as described in any of the second aspects of the present invention.
[0056] According to a sixth aspect of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing a semiconductor device as described in the fifth aspect of the present invention.
[0057] The technical solution provided by this invention forms a first P+ type doped region and a first N+ type doped region in a buffer layer. The first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region. The first N+ type doped region covers the area below the drain metal layer and extends to the first doped region, thereby burying a reverse-biased PN junction in the buffer layer below the drain. The reverse bias of the PN junction isolates the conductive channel, suppressing conduction in the buffer layer below the drain, thus improving device reliability. Therefore, the technical solution provided by this invention solves the problem of leakage current channels generated in the buffer layer when high voltage is applied to GaN HEMTs devices, avoiding the aggravation of leakage current and thus preventing premature device breakdown, thereby improving device performance. Attached Figure Description
[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0059] Figure 1 This is a schematic diagram of the device structure of a GaN HEMT device with a substrate leakage suppression structure provided in an embodiment of the present invention;
[0060] Figure 2 This is a schematic diagram of the device structure of a GaN HEMT device with a substrate leakage suppression structure provided in another embodiment of the present invention;
[0061] Figure 3 This is a schematic flowchart of a method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to an embodiment of the present invention;
[0062] Figure 4 This is a schematic diagram of the device structure at different process stages fabricated according to a method for fabricating a GaN HEMT device with a substrate leakage suppression structure, provided in an embodiment of the present invention. Figure 1 ;
[0063] Figure 5 This is a schematic diagram of the device structure at different process stages fabricated according to a method for fabricating a GaN HEMT device with a substrate leakage suppression structure, provided in an embodiment of the present invention. Figure 2 ;
[0064] Figure 6This is a schematic diagram of the device structure at different process stages fabricated according to a method for fabricating a GaN HEMT device with a substrate leakage suppression structure, provided in an embodiment of the present invention. Figure 3 ;
[0065] Figure 7 This is a schematic diagram of the device structure at different process stages fabricated according to a method for fabricating a GaN HEMT device with a substrate leakage suppression structure, provided in an embodiment of the present invention. Figure 4 ;
[0066] Explanation of reference numerals in the attached figures:
[0067] 101-Substrate;
[0068] 102-channel layer;
[0069] 103 - Barrier layer;
[0070] 104-p-GaN material layer;
[0071] 105 - Isolation layer;
[0072] 106-Source metal layer;
[0073] 107 - Drain metal layer;
[0074] 108-First p-GaN layer;
[0075] 109 - Gate metal layer;
[0076] 110 - Source metal interconnect layer;
[0077] 111 - Drain metal interconnect layer;
[0078] 112 - Gate field plate;
[0079] 113 - Passivation layer;
[0080] 114 - First N+ type doped region;
[0081] 115 - First P+ type doped region;
[0082] 116 - Buffer layer. Detailed Implementation
[0083] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0084] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0085] Gallium nitride (GaN) is known as a third-generation wide-bandgap semiconductor and a new generation of power semiconductors. Compared to the previous two generations of semiconductor materials, it has higher performance parameters and is more likely to meet the new requirements of high-power, high-temperature, and harsh environment applications. In power electronics applications, AlGaN / GaN heterostructures, due to their strong polarization effect, form quantum potential wells at the interface, generating a two-dimensional electron gas (2DEG) with high electron mobility and high density. The main characteristics of power semiconductor devices are high voltage withstand capability and high current. The current limitations of Si materials are not only in the high-frequency field, but also in high-voltage power devices, where its on-resistance is higher than that of materials such as GaN, which greatly reduces power density and device switching characteristics. GaN HEMTs, on the other hand, exhibit better high-voltage and low-resistance characteristics under high voltage. Therefore, improving the stability of GaN HEMTs under high voltage is a key research issue.
[0086] Damage generated during crystal growth, such as nitrogen vacancies, line dislocations, and unintentionally introduced impurities like oxygen and silicon, can exist in the buffer layer of GaN HEMTs. When a large voltage is applied to the device drain, electrons can pass through the buffer layer under the influence of an increasingly strong vertical electric field, creating leakage current channels. This exacerbates the leakage current and can lead to premature device breakdown in severe cases.
[0087] In view of this, the inventors of this application have improved the reliability of the device by burying a reverse-biased PN junction in the buffer layer below the drain and isolating the conductive channel through the reverse bias of the PN junction, thereby suppressing the conduction of the buffer layer below the drain.
[0088] As can be seen, the technical solution provided by this invention solves the problem of leakage current path generated in the buffer layer of GaN HEMTs power devices, avoids the aggravation of leakage current in the device, and thus avoids premature breakdown of the device.
[0089] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0090] Please refer to Figures 1-7 According to an embodiment of the present invention, a GaN HEMT device with a substrate leakage suppression structure is provided, such as... Figure 1 or Figure 2 As shown, it includes:
[0091] Substrate 101, and buffer layer 116 formed on said substrate 101;
[0092] A first P+ type doped region 115 and a first N+ type doped region 114; wherein, the first P+ type doped region 115 is formed in the buffer layer 116 and does not contact the substrate 101; the first N+ type doped region 114 is formed on the surface of a portion of the first P+ type doped region 115, and the first P+ type doped region 115 encloses the first N+ type doped region 114;
[0093] A GaN HEMT structure is formed at the top of the buffer layer 116; wherein the GaN HEMT structure includes a gate metal layer 109 and a drain metal layer 107; the gate metal layer 109 and the drain metal layer 107 are arranged in a horizontal direction;
[0094] The first N+ type doped region 114 covers the region below the drain metal layer 107 and extends to the first doped region; the first doped region characterizes the region below the gate metal layer 109 and the drain metal layer 107.
[0095] In GaN HEMT power devices, due to epitaxial quality issues with the buffer layer 116, electrons can pass through the buffer layer 116 under the influence of an increasingly strong vertical electric field, creating a leakage current channel. This exacerbates the leakage current and can lead to premature device breakdown in severe cases. Therefore, a first P+ type doped region 115 and a first N+ type doped region 114 are formed in the buffer layer 116 to create a reverse PN junction, thereby isolating the leakage current channel. Figure 1 The middle arrow indicates a leakage path generated in the buffer layer 116 when the first P+ doped region 115 and the first N+ doped region 114 are not provided. It should be understood that this leakage path is indicated by the arrow for ease of representation in prior art devices. Figure 1 China stated that Figure 1 The device itself does not have a leakage path.
[0096] The technical solution provided by this invention forms a first P+ type doped region and a first N+ type doped region in a buffer layer; wherein, the first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region; the first N+ type doped region covers the area below the drain metal layer and extends to the first doped region, so as to bury a reverse-biased PN junction in the buffer layer below the drain; the reverse bias of the PN junction isolates the conductive channel, suppressing the conduction of the buffer layer below the drain, thereby improving the device reliability.
[0097] As can be seen, the technical solution provided by the present invention solves the problem of leakage current path generated in the buffer layer 116 of GaN HEMTs power devices, avoids the aggravation of leakage current of the device, and thus avoids the phenomenon of premature breakdown of the device, thereby improving the device performance.
[0098] In one embodiment, the first P+ type doped region 115 is doped with magnesium ions, and the first N+ type doped region 114 is doped with silicon ions.
[0099] In one embodiment, the doping concentration in the first P+ type doped region 115 is:
[0100] 1*10 17 ~2*10 17 cm-3; the doping concentration of the first N+ type doped region 114 is 2*10 cm-3. 18 ~6*10 18 cm-3.
[0101] In one embodiment, the GaN HEMT structure further includes:
[0102] A channel layer 102 and a barrier layer 103 are formed sequentially on the buffer layer 116 in a vertical direction; wherein, the channel layer 102 covers the surface of the first P+ type doped region 115, the first N+ type doped region 114 and part of the surface of the buffer layer 116.
[0103] A source metal layer 106 and a first p-GaN layer 108 are formed on the surface of the barrier layer 103. The source metal layer 106, the gate metal layer 109, and the drain metal layer 107 are arranged sequentially in a horizontal direction. The first p-GaN layer 108 is formed between the gate metal layer 109 and the barrier layer 103 to expose a portion of the barrier layer 103.
[0104] The first p-GaN layer 108 is doped with magnesium ions, and the magnesium ions are activated by annealing.
[0105] In a preferred embodiment, only the first p-GaN layer 108 includes magnesium ions activated by laser selective annealing.
[0106] In one embodiment, the GaN HEMT structure further includes:
[0107] A second p-GaN layer is formed on the exposed surface of the barrier layer 103; wherein the magnesium ions doped in the second p-GaN layer are not activated by laser annealing.
[0108] By performing laser selective annealing on only the first p-GaN layer 108, compared to existing high-temperature annealing methods, the technical solution provided by this invention avoids the etching step of the p-GaN material layer 104, thus solving the problem of etching damage; it also avoids the damage to the drift region caused by etching, and prevents device degradation, such as... Figure 1 As shown.
[0109] Furthermore, the selective laser annealing method provided by this invention solves the problem of magnesium ion diffusion during thermal annealing, avoids the degradation of AlGaN / GaN heterojunction caused by magnesium ion diffusion into the barrier layer 103, and thus avoids the increase in device on-resistance.
[0110] In another embodiment, the first p-GaN layer 108 is formed by high-temperature annealing, retaining the under-gate p-GaN material layer 104, while the non-under-gate p-GaN material layer 104 is etched away, such as... Figure 2 As shown.
[0111] In one embodiment, the GaN HEMT device having a substrate leakage suppression structure further includes:
[0112] A gate metal interconnect layer, a source metal interconnect layer 110, and a drain metal interconnect layer 111 are formed on the top of the gate metal layer 109, the source metal layer 106, and the drain metal layer 107, respectively.
[0113] A passivation layer 113 is provided, which fills the gap between the gate metal interconnect layer, the source metal interconnect layer 110, and the drain metal interconnect layer 111.
[0114] A gate field plate 112 is formed at the top of the passivation layer 113 between the gate metal layer 109 and the drain metal layer 107, and is connected to the gate metal interconnect layer.
[0115] In one embodiment, the GaN HEMT device with a substrate leakage suppression structure further includes:
[0116] A plurality of isolation layers 105; when the first p-GaN layer 108 is formed by laser selective annealing, the plurality of isolation layers 105 are formed on both sides of the GaN HEMT structure along the horizontal direction and penetrate the second p-GaN layer, the barrier layer 103, the channel layer 102 and part of the buffer layer 116.
[0117] In one embodiment, the substrate 101 is made of Si, the channel layer 102 is made of GaN, the barrier layer 103 is made of AlGaN, the passivation layer 113 is made of Al2O3, and the buffer layer 116 is made of AlGaN. Of course, the aforementioned structural layers can also be made of other materials, and this invention is not limited thereto. Any implementation of the corresponding structural layer material is within the scope of protection of this invention. The buffer layer 116 is a compositionally graded structure or a superlattice structure. Other structures are also possible, and this invention is not limited thereto. Any implementation of the buffer layer 116 structure is within the scope of protection of this invention.
[0118] According to another embodiment of the present invention, a method for fabricating a GaN HEMT device with a substrate leakage suppression structure is also provided, and a schematic flowchart of the fabrication method is shown below. Figure 3 As shown, a GaN HEMT device with a substrate leakage suppression structure as described in any of the foregoing embodiments of the present invention includes:
[0119] S11: Provide a substrate 101, and form the buffer layer 116 on the substrate 101;
[0120] S12: Form the first P+ type doped region 115 and the first N+ type doped region 114; wherein, the first N+ type doped region 114 is formed in a portion of the buffer layer 116 and does not contact the substrate 101; the first N+ type doped region 114 is formed on the surface of a portion of the first P+ type doped region 115, and the first P+ type doped region 115 encloses the first N+ type doped region 114;
[0121] S13: Form the GaN HEMT structure; the GaN HEMT structure is formed at the top of the buffer layer 116; wherein, the GaN HEMT structure includes a gate metal layer 109 and a drain metal layer 107; the gate metal layer 109 and the drain metal layer 107 are arranged in a horizontal direction;
[0122] The first N+ type doped region 114 covers the area below the drain metal layer 107 and extends into the first doped region.
[0123] The technical solution provided by this invention forms a first P+ type doped region and a first N+ type doped region in the buffer layer to bury a reverse-biased PN junction in the buffer layer below the drain. The reverse bias of the PN junction isolates the conductive channel, suppressing conduction in the buffer layer below the drain, thereby improving device reliability. It is evident that the technical solution provided by this invention solves the problem of leakage channels generated in the buffer layer of GaN HEMTs power devices, avoiding the aggravation of leakage current and thus preventing premature device breakdown, thereby improving device performance.
[0124] In one embodiment, step S12 involves forming the first P+ type doped region 115 and the first N+ type doped region 114, as follows: Figure 4 As shown, the specific steps include: S121-S124:
[0125] S121: A portion of the buffer layer 116 is heavily p-type doped to form the first p+ type doped region 115;
[0126] S122: Form a first hard mask layer; the first hard mask layer covers the remaining undoped surface of the buffer layer 116 and part of the first P+ type doped region 115 to expose part of the first P+ type doped region 115 below the drain metal layer 107;
[0127] S123: The surface of the exposed first P+ type doped region 115 is heavily doped with N type to form the first P+ type doped region 115;
[0128] S124: Remove the first hard mask layer;
[0129] After the buffer layer 116 is heavily doped with P-type and N-type respectively, the doped ions in the buffer layer 116 need to be activated.
[0130] In one embodiment, step S13, forming the GaN HEMT structure, specifically includes steps S131-S133:
[0131] S131: Forming the channel layer 102, the barrier layer 103, and the p-GaN material layer 104; the channel layer 102, the barrier layer 103, and the p-GaN material layer 104 are sequentially stacked on the surface of the buffer layer 116 in a vertical direction, and cover the first P+ type doped region 115 and the first N+ type doped region 114, as shown. Figure 5 As shown;
[0132] In one embodiment, step S131, after forming the channel layer 102, the barrier layer 103, and the p-GaN material layer 104, further includes:
[0133] The plurality of isolation layers 105 are formed; the plurality of isolation layers 105 penetrate the p-GaN material layer 104, the barrier layer 103, the channel layer 102, and part of the end of the buffer layer 116, such as Figure 6 As shown.
[0134] S132: Form the first p-GaN layer 108, the source metal layer 106, and the drain metal layer 107;
[0135] In one embodiment, when the first p-GaN layer 108 is formed by high-temperature annealing, step S132, forming the first p-GaN layer 108, the source metal layer 106, and the drain metal layer 107, specifically includes steps S1321-S1322 (not shown in the figure):
[0136] Step S1321: Etch both ends of the p-GaN material layer 104 along the horizontal direction (i.e., etch the p-GaN material layer 104 at the non-gate position) to expose part of the barrier layer 103 to form the first p-GaN layer 108.
[0137] Step S1322: Form the source metal layer 106 and the drain metal layer 107; the source metal layer 106 and the drain metal layer 107 are formed on the exposed surface of the barrier layer 103, and the source metal layer 106 and the drain metal layer 107 are sequentially formed on both sides of the first p-GaN layer 108 along the horizontal direction.
[0138] In another embodiment, when the first p-GaN layer 108 is formed using laser selective annealing, step S132, forming the first p-GaN layer 108, the source metal layer 106, and the drain metal layer 107 specifically includes:
[0139] S1321: Laser selective annealing is performed only on the p-GaN material layer 104 in the gate region to form the first p-GaN layer 108, and the remaining portion of the p-GaN material layer 104 forms the second p-GaN layer;
[0140] S1322: Etch portions of the second p-GaN layer in the source and drain regions to form a first aperture and a second aperture;
[0141] S1323: Fill the first opening with metal material to form the source metal layer 106, and fill the second opening with metal material to form the drain metal, such as... Figure 7 As shown.
[0142] In one embodiment, when performing laser selective annealing on the p-GaN material layer 104 in the gate region, the laser wavelength used is 300-600nm, the laser energy is 300W-1200W, and the laser spot size is 1µm-0.5mm.
[0143] The laser annealing apparatus includes: a laser power controller, which controls and adjusts the laser power; a laser, which emits the original laser beam, wherein the energy distribution of the beam is Gaussian; collimating and expanding mirrors, reflecting mirrors, shaping lenses, etc., which shape the original beam with Gaussian energy distribution into a beam with uniform energy distribution; and a plano-convex cylindrical mirror, which is used to adjust the square spot into a linear or dotted spot to irradiate the sample for laser annealing of the sample surface.
[0144] When the p-GaN material layer 104 in the second region of a GaN HEMT device is selectively annealed using a laser annealing device, the material passes through the aforementioned device sequentially, thereby activating magnesium ions. The principle and specific operation of laser annealing are existing technologies and will not be elaborated upon here.
[0145] S133: Form the gate metal layer 109, such as Figure 7 As shown.
[0146] In one embodiment, step S133, after forming the gate metal layer 109, further includes:
[0147] The gate metal interconnect layer, the source metal interconnect layer 110, the drain metal interconnect layer 111, and the passivation layer 113 are formed.
[0148] Forming the gate field plate 112, as follows Figure 1 As shown.
[0149] Secondly, according to an embodiment of the present invention, a semiconductor device is also provided, which utilizes the GaN HEMT device with a substrate leakage suppression structure as described in any of the foregoing embodiments of the present invention.
[0150] Furthermore, according to an embodiment of the present invention, an electronic device is also provided, including the semiconductor device described in the foregoing embodiments of the present invention.
[0151] In addition, according to an embodiment of the present invention, a method for fabricating a semiconductor device is also provided, utilizing the method for fabricating a GaN HEMT device with a substrate leakage suppression structure as described in any of the foregoing embodiments of the present invention.
[0152] According to another embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing a semiconductor device as described in the foregoing embodiments of the present invention.
[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A GaN HEMT device with a substrate leakage suppression structure, characterized in that, include: A substrate, and a buffer layer formed on the substrate; A first P+ type doped region and a first N+ type doped region; wherein, the first P+ type doped region is formed in the buffer layer and does not contact the substrate; the first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region; A GaN HEMT structure is formed on the top of the buffer layer; wherein the GaN HEMT structure includes a gate metal layer, a drain metal layer, and a channel layer; the gate metal layer and the drain metal layer are arranged in a horizontal direction, and the channel layer covers the first P+ type doped region, the first N+ type doped region, and part of the surface of the buffer layer. The first N+ type doped region covers the area below the drain metal layer and extends to the first doped region; the first doped region characterizes the area below the gate metal layer and the drain metal layer.
2. The GaN HEMT device with a substrate leakage suppression structure according to claim 1, characterized in that, The first P+ type doped region is doped with magnesium ions, and the first N+ type doped region is doped with silicon ions.
3. A GaN HEMT device with a substrate leakage suppression structure according to claim 2, characterized in that, The doping concentration in the first P+ type doped region is 1*10 17 ~2*10 17 cm -3 The doping concentration of the first N+ type doped region is 2*10. 18 ~6*10 18 cm -3 .
4. A GaN HEMT device with a substrate leakage suppression structure according to claim 3, characterized in that, The GaN HEMT structure also includes: A barrier layer, wherein the channel layer and the barrier layer are sequentially formed on the buffer layer in a vertical direction; A source metal layer and a first p-GaN layer are formed on the surface of the barrier layer. The source metal layer, the gate metal layer, and the drain metal layer are arranged sequentially in a horizontal direction. The first p-GaN layer is formed between the gate metal layer and the barrier layer to expose part of the barrier layer. The first p-GaN layer is doped with magnesium ions, which are activated by annealing.
5. A GaN HEMT device with a substrate leakage suppression structure according to claim 4, characterized in that, Only the first p-GaN layer contains magnesium ions activated by laser selective annealing.
6. A GaN HEMT device with a substrate leakage suppression structure according to claim 5, characterized in that, The GaN HEMT structure also includes: A second p-GaN layer is formed on the exposed surface of the barrier layer; wherein the magnesium ions doped in the second p-GaN layer are not activated by laser annealing.
7. A GaN HEMT device with a substrate leakage suppression structure according to claim 6, characterized in that, GaN HEMT devices with substrate leakage suppression structures also include: A gate metal interconnect layer, a source metal interconnect layer, and a drain metal interconnect layer; the gate metal interconnect layer, the source metal interconnect layer, and the drain metal interconnect layer are respectively formed on top of the gate metal layer, the source metal layer, and the drain metal layer; A passivation layer is provided, which fills the voids between the gate metal interconnect layer, the source metal interconnect layer, and the drain metal interconnect layer. A gate field plate is formed at the top of the passivation layer between the gate metal layer and the drain metal layer, and is connected to the gate metal interconnect layer.
8. A GaN HEMT device with a substrate leakage suppression structure according to claim 7, characterized in that, The GaN HEMT device with a substrate leakage suppression structure further includes: A plurality of isolation layers; the plurality of isolation layers are formed on both sides of the GaN HEMT structure along the horizontal direction and penetrate the second p-GaN layer, the barrier layer, the channel layer and part of the buffer layer.
9. A GaN HEMT device with a substrate leakage suppression structure according to claim 8, characterized in that, The substrate is made of Si, the channel layer is made of GaN, the barrier layer is made of AlGaN, the passivation layer is made of Al2O3, and the buffer layer is made of AlGaN.
10. A method for fabricating a GaN HEMT device with a substrate leakage suppression structure, used to fabricate the GaN HEMT device with a substrate leakage suppression structure as described in any one of claims 1-9, characterized in that, include: Provide a substrate, and form the buffer layer on the substrate; The first P+ type doped region and the first N+ type doped region are formed; wherein, the first N+ type doped region is formed in a portion of the buffer layer and does not contact the substrate; the first N+ type doped region is formed on the surface of a portion of the first P+ type doped region, and the first P+ type doped region encloses the first N+ type doped region; The GaN HEMT structure is formed on the top of the buffer layer; wherein the GaN HEMT structure includes a gate metal layer, a drain metal layer and a channel layer; the gate metal layer and the drain metal layer are arranged in a horizontal direction, and the channel layer covers the first P+ type doped region, the first N+ type doped region and part of the surface of the buffer layer. The first N+ type doped region covers the area below the drain metal layer and extends into the first doped region.
11. The method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to claim 10, characterized in that, Forming the first P+ type doped region and the first N+ type doped region specifically includes: A portion of the buffer layer is p-type heavily doped to form the first p+ type doped region; A first hard mask layer is formed; the first hard mask layer covers the remaining undoped buffer layer and the surface of a portion of the first P+ type doped region to expose a portion of the first P+ type doped region beneath the drain metal layer; The surface of the exposed first P+ type doped region is heavily doped with N-type to form the first P+ type doped region; Remove the first hard mask layer.
12. The method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to claim 11, characterized in that, The formation of the GaN HEMT structure specifically includes: The channel layer, the barrier layer, and the p-GaN material layer are formed; the channel layer, the barrier layer, and the p-GaN material layer are stacked sequentially on the surface of the buffer layer in a vertical direction, and cover the first P+ type doped region and the first N+ type doped region. A first p-GaN layer, a source metal layer, and the drain metal layer are formed; The gate metal layer is formed.
13. The method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to claim 12, characterized in that, The formation of the first p-GaN layer, the source metal layer, and the drain metal layer specifically includes: The p-GaN material layer is etched at both ends along the horizontal direction to expose part of the barrier layer in order to form the first p-GaN layer; The source metal layer and the drain metal layer are formed on the exposed surface of the barrier layer, and the source metal layer and the drain metal layer are sequentially formed on both sides of the first p-GaN layer along the horizontal direction.
14. The method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to claim 12, characterized in that, The formation of the first p-GaN layer, the source metal layer, and the drain metal layer specifically includes: performing laser selective annealing only on the p-GaN material layer in the gate region to form the first p-GaN layer, and forming the second p-GaN layer on the remaining portion of the p-GaN material layer; The second p-GaN layer is etched in portions of the source and drain regions to form a first aperture and a second aperture; The first opening is filled with metal material to form the source metal layer, and the second opening is filled with metal material to form the drain metal.
15. A method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to any one of claims 14, characterized in that, When performing laser selective annealing on the p-GaN material layer in the gate region, the laser wavelength used is 300~600nm, the laser energy is 300W~1200W, and the laser spot size is 1um~0.5mm.
16. A method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to any one of claims 13 or 15, characterized in that, After forming the channel layer, the barrier layer, and the p-GaN material layer, the process further includes: Several isolation layers are formed; the several isolation layers penetrate the p-GaN material layer, the barrier layer, the channel layer and part of the end of the buffer layer.
17. The method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to claim 16, characterized in that, After forming the gate metal layer, the process further includes: A gate metal interconnect layer, a source metal interconnect layer, a drain metal interconnect layer, and a passivation layer are formed; Forming a gate field plate.
18. A semiconductor device, characterized in that, The GaN HEMT device with a substrate leakage suppression structure as described in any one of claims 1-9.
19. An electronic device comprising the semiconductor device of claim 18.
20. A method for fabricating a semiconductor device, characterized in that, A method for fabricating a GaN HEMT device with a substrate leakage suppression structure according to any one of claims 10-17.
21. A method for manufacturing an electronic device, comprising the method for manufacturing a semiconductor device as described in claim 20.