Preparation method of battery grid line and heterojunction battery
By using low-temperature silver paste and laser transfer technology to prepare grid lines on heterojunction batteries, the problem of film fragility is solved, and low-temperature preparation and high-efficiency battery performance are achieved.
Patent Information
- Application Number
- CN202210768476.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-01
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2042-07-01
AI Technical Summary
The membrane structure of heterojunction batteries is fragile and cannot withstand high temperatures, making high-temperature processes difficult to apply. The existing grid line preparation process damages the membrane layer and affects battery efficiency.
Using low-temperature silver paste and laser transfer technology, through pre-printing, grid line preparation and transfer steps, the conductive paste is cured at low temperature to form a stable grid line structure to avoid high temperature damage.
The low-temperature preparation of cell grid lines is achieved, which reduces damage to the cell, improves cell efficiency and light utilization, and reduces preparation costs.
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Figure CN116247121B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a method for preparing a grid line of a cell sheet and a heterojunction cell. Background Art
[0002] In the related technology, heterojunction batteries are relatively fragile due to their unique membrane structure and are not resistant to high temperatures, so they are not compatible with high-temperature processes. As a result, high-temperature technologies such as high-temperature sintering are difficult to implement on heterojunction batteries. The preparation process of the grid lines in the related technology can easily damage the heterojunction battery film layer, and the poor performance of the prepared grid lines affects the battery efficiency. Summary of the Invention
[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.
[0004] To this end, an embodiment of the present invention provides a method for preparing a grid line of a battery cell. The method for preparing a grid line of a battery cell has the advantages of low preparation temperature and little damage to the battery cell.
[0005] According to an embodiment of the present invention, the method for preparing the grid lines of a cell comprises the following steps: pre-printing, grid line preparation and grid line transfer, printing a conductive paste on the cell according to a preset grid line pattern to form a first grid line, preparing a second grid line matching the preset grid line pattern through a mold and curing the second grid line, aligning the second grid line with the first grid line, and curing the conductive paste at a low temperature to fix the second grid line on the cell.
[0006] The method for preparing the grid lines of a cell according to the embodiment of the present invention has the advantages of low preparation temperature and little damage to the cell.
[0007] In some embodiments, the first gate line is printed on the transparent conductive layer of the cell.
[0008] In some embodiments, the thickness of the first gate line is positively correlated with the depth of the silicon wafer texture of the solar cell.
[0009] In some embodiments, the conductive paste is a low-temperature silver paste, and the first gate line is a low-temperature silver paste layer.
[0010] In some embodiments, the thickness of the low-temperature silver paste layer is 1-5 um.
[0011] In some embodiments, the grid line transfer is performed using a laser, and the processing temperature of the laser is lower than 200°C.
[0012] According to an embodiment of the present invention, the heterojunction battery includes a battery cell and a plurality of grid lines arranged on a surface of the battery cell, wherein the grid lines include a first grid line formed on the battery cell and a second grid line formed on the first grid line.
[0013] In some embodiments, the width of the second gate line is negatively correlated with the thickness of the second gate line. In some embodiments, the cross-sectional profile of the second gate line is triangular and has a bottom surface, a first side surface, and a second side surface connected end to end, and the bottom surface is connected to the top surface of the first gate line.
[0014] In some embodiments, a width of a bottom surface of the second gate line is less than or equal to a width of a top surface of the first gate line, and a cross-sectional profile of the first gate line is a trapezoid or a rectangle. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 Schematic diagram of the grid line preparation steps of the method for preparing grid lines of a battery cell according to an embodiment of the present invention.
[0016] Figure 2 Schematic diagram of the grid line transfer step of the method for preparing the grid line of a battery cell according to an embodiment of the present invention.
[0017] Reference numerals: 100, battery cell; 2, first grid line; 3, second grid line; 200, mold. DETAILED DESCRIPTION
[0018] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present invention, but should not be understood as limiting the present invention.
[0019] According to the method for preparing the grid line of a battery cell according to an embodiment of the present invention, Figure 1 and Figure 2As shown, the method for preparing the grid lines of a cell includes the following steps: pre-printing, grid line preparation and grid line transfer, wherein a conductive paste is printed on the cell 100 according to a preset grid line pattern to form a first grid line 2, a second grid line 3 matching the preset grid line pattern is prepared by a mold 200 and the second grid line 3 is cured, the second grid line 3 is aligned with the first grid line 2, and the conductive paste is cured at low temperature to fix the second grid line 3 on the cell 100. In the pre-printing step, the conductive paste is printed on the surface of the cell 100 to form the first grid line 2. In the pre-printing step, the conductive paste does not need to be treated at high temperature to protect the cell 100. In the grid line preparation step, the second grid line 3 is prepared separately by the mold 200, which can avoid the second grid line 3 from damaging the cell 100. In the grid line transfer step, the low-temperature curing of the conductive paste can fix the second grid line 3 to the cell 100. The low-temperature curing avoids the damage to the cell 100 caused by the high-temperature process in the related art, reduces the difficulty of preparing the grid lines of the cell, and improves the battery efficiency.
[0020] The method for preparing the grid lines of a cell according to the embodiment of the present invention has the advantages of low preparation temperature and little damage to the cell 100 .
[0021] In some embodiments, the first gate lines 2 are printed on the transparent conductive layer of the cell 100 .
[0022] Specifically, the conductive paste forming the first gate line 2 is printed on the transparent conductive layer of the cell 100 so that the gate line and the transparent conductive layer are tightly combined. The low-temperature curing conductive paste can avoid the damage to the transparent conductive layer caused by the high-temperature process in the related art.
[0023] In some embodiments, the thickness of the first gate line 2 is positively correlated with the depth of the silicon wafer texture of the cell 100 .
[0024] Therefore, the thickness of the conductive paste of the first gate line is positively correlated with the depth of the silicon wafer texture, which facilitates the conductive paste to combine with the silicon wafer texture of the cell and facilitates the first gate line to better fix the second gate line. Controlling the thickness of the conductive paste can reduce material costs.
[0025] In some embodiments, the conductive paste is low-temperature silver paste, and the first gate line 2 is a low-temperature silver paste layer.
[0026] Therefore, the first grid line is made of low-temperature silver paste, which has a low curing temperature and can protect the transparent conductive layer of the cell to avoid damaging the cell.
[0027] In some embodiments, the thickness of the low-temperature silver paste layer is 1-5 um.
[0028] Therefore, controlling the thickness of the low-temperature silver paste layer to 1-5 μm can reduce the amount of low-temperature silver paste used and reduce the preparation cost of the battery cell grid line.
[0029] In some embodiments, as Figure 2 As shown, the grid line transfer is performed using laser, and the processing temperature of the laser is lower than 200°C.
[0030] Specifically, laser transfer is used for the gate line transfer, which can quickly form the second gate line 3 on the cell 100 and avoid the impact of other transfer methods on the shape and size of the gate line. The laser processing temperature is lower than 200°C, which can reduce damage to the transparent conductive film of the cell 100 caused by the gate line transfer. Laser transfer of gate lines has high production efficiency. Figure 2 The arrow in the middle is the direction of the laser.
[0031] According to the heterojunction battery of the embodiment of the present invention, Figure 1 and Figure 2 As shown, the heterojunction battery includes a battery cell 100 and a plurality of grid lines arranged on the surface of the battery cell 100 , wherein the grid lines include a first grid line 2 formed on the battery cell 100 and a second grid line 3 formed on the first grid line 2 .
[0032] Specifically, the grid lines on the surface of the battery cell 100 are formed twice, so as to form grid lines with stable shapes, ensure that the grid lines have a large aspect ratio, reduce contact resistance, and improve battery conversion efficiency.
[0033] In some embodiments, the width of the second gate line 3 is negatively correlated with the thickness of the second gate line 3 .
[0034] Specifically, the thickness direction of the second grid line 3 is consistent with the axial direction of the battery cell 100, which can form a slope on the side of the second grid line 3. When the optical fiber is irradiated on the second grid line 3, the side of the second grid line 3 can reflect the light to the surface of the battery cell 100, thereby improving the light utilization rate of the battery cell 100 and thus improving the battery efficiency.
[0035] In some embodiments, as Figure 1 and Figure 2 As shown, the cross-sectional profile of the second gate line 3 is triangular and has a bottom surface, a first side surface and a second side surface connected end to end, and the bottom surface is connected to the top surface of the first gate line 2 .
[0036] Specifically, the cross-sectional profile of the second grid line 3 can be a triangle or an approximate triangle. The triangular cross-sectional profile of the second grid line 3 makes the second grid line 3 have a larger aspect ratio and reduces the shadow obstruction caused by the second grid line 3, thereby improving the light utilization rate of the battery cell 100 and thus improving the battery efficiency.
[0037] In some embodiments, as Figure 2 As shown, the width of the bottom surface of the second gate line 3 is less than or equal to the width of the top surface of the first gate line 2 , and the cross-sectional profile of the first gate line 2 is a trapezoid or a rectangle.
[0038] Thus, the width of the bottom surface of the second gate line is less than or equal to the width of the top surface of the first gate line, so that the connection resistance between the second gate line and the first gate line is small, thereby reducing the contact resistance between the grid line and the cell. When the cross-sectional profile of the first gate line is trapezoidal or rectangular, it is convenient for the second gate line to align with the first gate line.
[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.
[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.
[0041] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.
[0042] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0043] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.
[0044] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments by those skilled in the art are within the scope of protection of the present invention.
Claims
1. A method for preparing a grid line of a battery cell, characterized in that: The following steps are involved: Pre-printing: printing a conductive paste on the cell according to a preset grid line pattern to form a first grid line; preparing a grid line, preparing a second grid line matching the preset grid line pattern through a mold and curing the second grid line; Gate line transfer, aligning the second gate line with the first gate line, and low-temperature curing the conductive paste to fix the second gate line on the battery cell, the conductive paste is a low-temperature silver paste, the first gate line is a low-temperature silver paste layer, the width of the second gate line is negatively correlated with the thickness of the second gate line; the cross-sectional profile of the second gate line is triangular and has a bottom surface, a first side surface, and a second side surface connected end to end, the bottom surface is connected to the top surface of the first gate line; the width of the bottom surface of the second gate line is less than or equal to the width of the top surface of the first gate line, and the cross-sectional profile of the first gate line is a trapezoid or a rectangle.
2. The method for preparing a battery grid line according to claim 1, wherein: The first gate lines are printed on the transparent conductive layer of the cell.
3. The method for preparing a battery grid line according to claim 1, wherein: The thickness of the first gate line is positively correlated with the depth of the silicon wafer texture of the cell.
4. The method for preparing a battery cell grid line according to claim 1, wherein: The thickness of the low-temperature silver paste layer is 1-5 μm.
5. The method for preparing a battery grid line according to claim 1, wherein: The grid line transfer is performed by using a laser, and the processing temperature of the laser is lower than 200°C.
Citation Information
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