A preparation method of an integrated flip-chip LED chip

Abstract

The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for manufacturing an integrated flip-chip LED chip, which includes the following steps: 1) Provide an epitaxial wafer; 2) Form an n-contact electrode platform (201); 3) Form a dividing groove (202); 4) Prepare an n-contact electrode (301); 5) Prepare a p-contact electrode (401); 6) Evaporate a DBR film (501); 7) Deposit a first insulating and passivating layer (502); 8) Expose the n-contact electrode (301); 9) Prepare an n-connection electrode (601); 10) Deposit a second insulating and passivating layer (701); 11) Expose the p-contact electrode (401); 12) Prepare a p-connection electrode (702); 13) Deposit a third insulating and passivating layer (801); 14) Expose the P-connection electrode (702) and the n-connection electrode (601); 15) Prepare a p-pad electrode (802) and an n-pad electrode (901). It can effectively stabilize the product performance and production yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for manufacturing a chip, and particularly to a method for manufacturing an integrated flip-chip LED chip. Background Art

[0002] Semiconductor lighting is known as the fourth-generation lighting source or green light source, and has the characteristics of energy saving, environmental protection, long life, small size, etc., and can be widely used in various fields such as indication, display, decoration, backlight, general lighting, and urban night scene. Its application fields are also expanding rapidly, such as ultraviolet disinfection and sterilization, ultraviolet curing, communication and other fields.

[0003] LED (light-emitting diode) is a commonly used light-emitting device, which emits light by the recombination of electrons and holes, and it is widely used in the lighting field. The light-emitting diode can efficiently convert electrical energy into light energy, and has a wide range of uses in modern society, such as lighting, flat panel display, medical devices, etc.

[0004] At present, there are mainly three schools of LED chip structures, namely the front-mounted structure, the flip-chip structure, and the vertical structure. Chips with different structures are applied in different fields, each having its own advantages. With the improvement of market demand for product performance and the development of technology, the technology for manufacturing chips is also constantly innovating and optimizing. Among them, the flip-chip structure chip has good advantages in downstream packaging and product performance, and is also the current mainstream technical route in the market. And through the long-term research and development of professional personnel, it is currently in a very mature stage. However, with the improvement of market requirements for device performance, such as high power and long life, there are still many technical points in chip manufacturing technology that require innovation and breakthroughs by professionals, so as to reach a new height in device performance and cost performance.

[0005] In chip manufacturing technology, technical indicators such as small size, high power, low cost, and long life are the goals that professional R & D personnel continuously break through, and the market demand for the cost performance of devices is also getting higher and higher. In terms of chip manufacturing, compared with some fields, such as the currently emerging deep ultraviolet chip field, limited by the characteristics of the upstream epitaxial structure and some chip manufacturing technologies, the flip-chip structure is still the mainstream direction in this field, and the effective light extraction efficiency of chips in the industry is still at a relatively low stage, while the market demand for high power is getting higher and higher.

[0006] At present, the common method adopted at the application end is to integrate multiple low-power devices into a large device module to achieve the application effect of high power, but this will also cause a substantial increase in manufacturing costs and transaction prices.

[0007] As problems emerge, R & D personnel on the chip side are also constantly innovating, such as preparing large-size and high-power chips. However, there are also some key technical points that need to be optimized in the preparation of high-power chips, such as current distribution, current density, heat dissipation, etc. At the same time, high electro-optical conversion efficiency can be achieved in the preparation of small-size chips, but after increasing the size, the electro-optical conversion efficiency usually cannot reach the same theoretical value. Regarding the optimization of this technical point, some professionals have also made many attempts, such as improving current distribution and density through simple electrode layout design; introducing roughening technology, reflection technology, antireflection technology to improve light extraction, etc. However, considering the stability and operability of the process implementation, some technologies are still difficult to be introduced into the mass production stage, with limited improvement and a long optimization process cycle.

[0008] In view of the above technical defects of the existing technology, there is an urgent need to develop a new method for preparing flip-chip LED chips. Summary of the Invention

[0009] In order to overcome the defects of the existing technology, the present invention provides a method for preparing an integrated flip-chip LED chip, which can achieve good effects in terms of device stability, reliability, high electro-optical conversion efficiency, high heat dissipation, etc.

[0010] In order to achieve the above object, the present invention provides the following technical solutions:

[0011] A method for preparing an integrated flip-chip LED chip, characterized by comprising the following steps:

[0012] 1), providing an epitaxial wafer, which sequentially includes a substrate, an n-type layer, a quantum light-emitting layer, and a p-type layer from bottom to top;

[0013] 2), etching part of the p-type layer and the quantum light-emitting layer by lithography and etching to etch to the n-type layer to form an n-contact electrode platform;

[0014] 3), etching part of the p-type layer, the quantum light-emitting layer, and the n-type layer adjacent to the n-contact electrode platform by lithography and etching to etch to the substrate to form a dividing groove;

[0015] 4), preparing an n-contact electrode on the n-contact electrode platform by lithography and evaporation;

[0016] 5), preparing a p-contact electrode on the unetched part of the p-type layer by lithography and evaporation;

[0017] 6), evaporating a layer of DBR film as a whole;

[0018] 7), depositing a layer of first insulating and passivating layer as a whole;

[0019] 8), Etch part of the first insulating passivation layer and the DBR thin film by photolithography and etching to expose the n-contact electrode;

[0020] 9), Prepare an n-connection electrode connected to the n-contact electrode by photolithography and evaporation;

[0021] 10), Deposit a second insulating passivation layer integrally;

[0022] 11), Etch part of the second insulating passivation layer, the first insulating passivation layer and the DBR thin film by photolithography and etching to expose the p-contact electrode;

[0023] 12), Prepare a p-connection electrode connected to the p-contact electrode by photolithography and evaporation;

[0024] 13), Deposit a third insulating passivation layer integrally;

[0025] 14), Etch part of the third insulating passivation layer by photolithography and etching to expose the p-connection electrode, and etch part of the third insulating passivation layer and the second insulating passivation layer to expose the n-connection electrode;

[0026] 15), Prepare a p-pad electrode connected to the p-connection electrode and an n-pad electrode connected to the n-connection electrode by photolithography and evaporation respectively.

[0027] Preferably, the dividing groove includes an in-cell dividing groove and an inter-cell dividing groove, and the width of the in-cell dividing groove is smaller than the width of the inter-cell dividing groove.

[0028] Preferably, the width of the in-cell dividing groove is 5 - 10 μm, and the width of the inter-cell dividing groove is 15 - 30 μm.

[0029] Preferably, the n-contact electrode is made of a metal system Cr / Al / Ti / Au and its thickness is 10 / 150 / 10 / 200 nm.

[0030] Preferably, in step 4), after preparing the n-contact electrode, high-temperature annealing is carried out by high-temperature rapid annealing technology, where the annealing temperature is 500 - 1000 °C, the annealing atmosphere is N2, and the annealing time is 1 - 5 min.

[0031] Preferably, the p-contact electrode is made of a metal system Ni / Au and its thickness is 10 / 20 nm.

[0032] Preferably, in step 5), after preparing the p-contact electrode, high-temperature annealing is carried out by a rapid thermal annealing technique, where the annealing temperature is 500 - 900 °C, the annealing time is 1 - 5 min, and the annealing atmosphere is N2.

[0033] Preferably, the DBR is SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2, and its thickness is 3 - 5 μm.

[0034] Preferably, the first insulating passivation layer, the second insulating passivation layer, and the third insulating passivation layer are all made of SiO2, and their thicknesses are all 1 - 3 μm.

[0035] Preferably, in step 9), a negative photoresist process is used during photolithography, and a mask is used to block a partial area directly above the p-contact electrode so that the n-connection electrode is not prepared thereon.

[0036] Preferably, in step 11), the part etched is the part opposite to the part blocked by the mask.

[0037] Preferably, the p-connection electrode is made of a metal system Cr / Al / Ti / Au and its thickness is 20 / 3000 / 20 / 200 nm.

[0038] Preferably, the p-pad electrode and the n-pad electrode are made of a metal system Ti / Au / Cr / AuSn, and their thicknesses are 200 / 300 / 20 / 3000 nm.

[0039] Preferably, the method for preparing the integrated flip-chip LED chip further includes:

[0040] 16), cutting the wafer prepared in step 15) into unit die by grinding, polishing, and dicing techniques.

[0041] Preferably, the method for preparing the integrated flip-chip LED chip further includes:

[0042] 17), performing optoelectronic tests on the cut unit die to complete chip preparation.

[0043] In addition, the present invention also provides an integrated flip-chip LED chip, characterized in that it is prepared by the above preparation method.

[0044] Compared with the prior art, the method for preparing the integrated flip-chip LED chip of the present invention has one or more of the following beneficial technical effects:

[0045] 1. It divides a single die into multiple small units through deep etching, and then connects the p and n electrodes of multiple small units through an integration method. After injecting the same proportion of current, a high current density can be achieved in each small unit area, so as to improve the photoelectric conversion efficiency of the entire die.

[0046] 2. It introduces a large-area high-reflection thin film, which can reflect part of the light source to the light-emitting surface, reduce the light absorption of electrodes and other materials, and thus can also improve the light extraction efficiency.

[0047] 3. It adopts a segmented design form. Compared with the traditional structure, it can not only effectively improve the heat dissipation of the chip, extend the working life of the chip, but also has certain benefits for the release of internal stress of the chip, and can avoid the phenomenon that large-size high-power chips often crack due to temperature rise during long-term operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flowchart of the preparation method of the integrated flip-chip LED chip of the present invention.

[0049] Figure 2 is a schematic structural diagram of the epitaxial wafer used in the present invention.

[0050] Figure 3 is a schematic structural diagram after etching the n-contact electrode platform and the segmentation groove on the epitaxial wafer.

[0051] Figure 4 is on Figure 3 the basis of which the n-contact electrode is prepared.

[0052] Figure 5 is on Figure 4 the basis of which the p-contact electrode is prepared.

[0053] Figure 6 is on Figure 5 the basis of which the DBR layer, the first insulating and passivating layer are prepared and etched to expose the n-contact electrode.

[0054] Figure 7 is on Figure 6 the basis of which the n-connection electrode is prepared.

[0055] Figure 8 is a cross-sectional view at another place, showing a schematic structural diagram after the p-connection electrode is prepared.

[0056] Figure 9 is on Figure 8 the basis of which the third insulating and passivating layer and the p-pad electrode are prepared.

[0057] Figure 10 is the structural schematic diagram after preparing a second passivation layer, a third insulating and passivating layer, and an n-pad electrode on the basis of Figure 7 .

[0058] Among them, due to the complex structure of the present invention, the above-mentioned drawings adopt schematic diagrams of different cross-sectional positions. Specifically, in the above-mentioned drawings, Figure 8 and Figure 9 are cross-sectional views taken at the same part, that is, on the p-electrode region; Figure 6-7 and Figure 10 are cross-sectional views taken at the same part, that is, on the n-electrode region. Specific embodiments

[0059] The present invention will be further described below in conjunction with the drawings and embodiments. The content of the embodiments shall not be used to limit the protection scope of the present invention.

[0060] The present invention relates to a preparation method of an integrated flip-chip LED chip, in particular to a preparation method of an integrated high-power flip-chip LED chip, which improves the current distribution uniformity through the form of segmentation and integration of the light-emitting region, thereby improving the photoelectric conversion efficiency and realizing the improvement of the optical power; and, by segmenting the light-emitting region, the heat dissipation effect of the device can be improved, the internal stress can be relieved, and the service life can be extended; in addition, by introducing a high-reflection insulating material thin film layer to cover all regions except the p- and n-electrode connection regions, including the filling of the deep etching segmentation grooves, the reflectivity can be improved and the light extraction efficiency can be enhanced.

[0061] Figure 1 shows a flowchart of the preparation method of the integrated flip-chip LED chip of the present invention. As Figure 1 shown, the preparation method of the integrated flip-chip LED chip of the present invention includes the following steps:

[0062] 1. Provide an epitaxial wafer.

[0063] In the present invention, as Figure 1 shown, the provided epitaxial wafer sequentially includes a substrate 101, an n-type layer 102, a quantum light-emitting layer 103, and a p-type layer 104 from bottom to top.

[0064] Preferably, the substrate 101 is a sapphire substrate.

[0065] In addition, preferably, the provided epitaxial wafer is cleaned. More preferably, hydrochloric acid and hydrogen peroxide are used to clean the epitaxial wafer to remove the stains on its surface.

[0066] 2. Etch part of the p-type layer 104 and the quantum light-emitting layer 103 by lithography and etching methods to etch to the n-type layer 102 to form an n-contact electrode platform 201.

[0067] Specifically, it includes the following steps:

[0068] 1. Lithography 1: Fabricate the MESA pattern through lithography technology. Using a positive photoresist process, expose the area to be etched, that is, part of the p-type layer 104.

[0069] 2. Adopt a dry etching method under the condition of Cl2. Etch the exposed area to the n-type layer 102, that is, etch away the p-type layer 104 and the quantum light-emitting layer 103 in the exposed area, and then remove the mask to form the n-contact electrode platform 201.

[0070] Among them, according to the size of the epitaxial wafer, the etching depth is usually 0.5 - 1 μm.

[0071] It should be noted that in the present invention, multiple parts of the P-type layer 104 need to be exposed to facilitate the formation of multiple n-contact electrode platforms 201, thereby realizing the segmentation of the light-emitting area, that is, a single die can be segmented into multiple small units through deep etching.

[0072] III. Through lithography and etching methods, etch part of the p-type layer 104, the quantum light-emitting layer 103, and the n-type layer 102 adjacent to the n-contact electrode platform 201 to etch to the substrate 101 to form a segmentation groove 202.

[0073] Specifically, it includes the following steps:

[0074] 1. Lithography 2: Fabricate the ISO pattern through lithography technology. Using a positive photoresist process, expose the area to be etched, that is, part of the p-type layer 104 adjacent to the n-contact electrode platform 201.

[0075] Among them, in this step, when designing the pattern, the pattern should include the segmentation area within the unit die and the segmentation area between the unit dies.

[0076] 2. Adopt a dry etching method under the condition of Cl2. Etch the exposed area to the substrate 101, that is, etch away the p-type layer 104, the quantum light-emitting layer 103, and the n-type layer 102 in the exposed area, and then remove the mask to form the segmentation groove 202.

[0077] Among them, according to the size of the epitaxial wafer, the etching depth is usually 3 - 7 μm.

[0078] In the present invention, the etching width within the unit die is smaller than the cutting channel width between the unit dies.

[0079] Preferably, in this embodiment, the deep etching width within the unit chip is 5 - 10 μm, and the etching width between the unit dies is 15 - 30 μm.

[0080] Through this step, a shape as shown in Figure 3 is formed.

[0081] IV. Prepare the n-contact electrode 301 on the n-contact electrode platform 201 by means of photolithography and evaporation.

[0082] Specifically, it includes the following steps:

[0083] 1. Photolithography III: Through photolithography technology, fabricate the pattern of the n-contact electrode on the n-contact electrode platform 201. Using the negative photoresist process, expose the area for preparing the n-contact electrode on the n-contact electrode platform 201.

[0084] 2. Evaporate the n-contact electrode metal through metal evaporation technology.

[0085] Among them, the metal system of the n-contact electrode metal is Cr / Al / Ti / Au, with a thickness of 10 / 150 / 10 / 200 nm. That is, it includes a Cr layer, an Al layer, a Ti layer, and an Au layer stacked in sequence, and the thickness of the Cr layer is 10 nm, the thickness of the Al layer is 150 nm, the thickness of the Ti layer is 10 nm, and the thickness of the Au layer is 200 nm.

[0086] 3. After evaporating the n-contact electrode metal, strip and remove the mask to form the n-contact electrode 301.

[0087] Preferably, after forming the n-contact electrode 301, perform high-temperature annealing through high-temperature rapid annealing technology. Among them, the annealing temperature is 500 - 1000 °C, the annealing atmosphere is N2, and the annealing time is 1 - 5 min. Through the high-temperature annealing process, a good ohmic contact is formed between the n-contact electrode 301 and the n-type layer 102.

[0088] Through this step, a structure as shown in Figure 4 is formed.

[0089] V. Prepare the p-contact electrode 401 on the unetched part of the p-type layer 104 by means of photolithography and evaporation.

[0090] Specifically, it includes the following steps:

[0091] 1. Photolithography IV: Through photolithography technology, fabricate the pattern of the p-contact electrode on the unetched part of the p-type layer 104. Using the negative photoresist process, expose the area for preparing the p-contact electrode.

[0092] 2. Evaporate the p-contact electrode metal through metal evaporation technology.

[0093] Among them, the metal system of the p-contact electrode metal is Ni / Au, and the thickness is 10 / 20 nm. That is, it includes a Ni layer and an Au layer stacked in sequence, and the thickness of the Ni layer is 10 nm, and the thickness of the Au layer is 20 nm.

[0094] 3. After evaporating the p-contact electrode metal, strip and remove the mask to form the p-contact electrode 401.

[0095] Preferably, after forming the p-contact electrode 401, high-temperature annealing is performed by a rapid thermal annealing technique. Among them, the annealing temperature is 500-900 °C, the annealing time is 1-5 min, and the annealing atmosphere is N2. Through high-temperature annealing, a good ohmic contact is formed between the p-contact electrode 401 and the p-type layer 104.

[0096] Through this step, the structure as Figure 5 shown is formed.

[0097] Six, evaporate a DBR thin film 501 integrally.

[0098] After preparing the p-contact electrode 401, a DBR thin film 501 is evaporated integrally.

[0099] In the present invention, a DBR (distributed Bragg reflector) thin film 501 can be evaporated by a vacuum evaporation technique.

[0100] And, in the present invention, the DBR thin film 501 adopts a structure of alternating SiO2 and TiO2.

[0101] The DBR thin film 501 is SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2, and its thickness is 3-5 μm. Thus, the reflectivity of the DBR thin film 501 to deep ultraviolet light sources can reach more than 95%.

[0102] Thus, in the present invention, by introducing a high-reflection insulating material thin film layer (that is, the DBR thin film 501), covering all regions except the p- and n-electrode connection regions, including the filling of the deep etching isolation region (that is, the dividing groove 202), the reflectivity can be improved, and the light extraction efficiency can be enhanced.

[0103] Seven, deposit a first insulating passivation layer 502 integrally.

[0104] After evaporating the DBR thin film 501, a first insulating passivation layer 502 is deposited integrally on the DBR thin film 501.

[0105] In the present invention, the first insulating and passivating layer 502 can be deposited by using PECVD (Plasma Enhanced Chemical Vapor Deposition) technology. Among them, the passivation material can be SiO2, and the thickness is 1-3 um.

[0106] VIII. By means of photolithography and etching, part of the first insulating and passivating layer 502 and the DBR thin film 501 are etched to expose the n-contact electrode 301.

[0107] Specifically, it includes the following steps:

[0108] 1. Photolithography V: Through photolithography technology and using a negative resist process, the n-connection electrode area is exposed, that is, the first insulating and passivating layer 502 directly above the n-contact electrode 301 is exposed.

[0109] Preferably, the photolithography pattern in this step is the same as the photolithography pattern in Photolithography III.

[0110] 2. Adopt a dry etching method and use the condition of CF4+Cl2 to etch the exposed area, that is, etch the exposed first insulating and passivating layer 502 and the DBR thin film 501 below it until the metal surface of the n-contact electrode 301 to expose the n-contact electrode 301.

[0111] Through this step, its structure is as Figure 6 shown.

[0112] IX. Prepare the n-connection electrode 601 connected to the n-contact electrode 301 by means of photolithography and evaporation.

[0113] Specifically, it includes the following steps:

[0114] 1. Photolithography VI: Through photolithography technology and using a negative resist process, part of the first insulating and passivating layer 502 directly above the p-contact electrode 401 is covered by a mask.

[0115] Among them, the area covered by the mask is used as the reserved area for preparing the p-connection electrode in the subsequent process.

[0116] 2. Through metal evaporation technology, evaporate the n-connection electrode metal.

[0117] Among them, the metal system of the n-connection electrode metal is Ti / Al / Ti / Au, and its thickness is 20 / 200 / 20 / 20 nm. That is, it includes a Ti layer with a thickness of 20 nm, an Al layer with a thickness of 200 nm, a Ti layer with a thickness of 20 nm, and an Au layer with a thickness of 20 nm stacked in sequence.

[0118] 3. After evaporating the n-connection electrode metal, strip and remove the mask to complete the preparation of the n-connection electrode 601.

[0119] The n-connection electrode 601 can connect all the n-contact electrodes 301 together.

[0120] After this step, a structure as shown in Figure 7 is formed.

[0121] Step Ten: Deposit a second insulating passivation layer 701 as a whole.

[0122] After preparing the n-connection electrode 601, deposit a second insulating passivation layer 701 as a whole.

[0123] In the present invention, the second insulating passivation layer 701 can be deposited by PECVD technology. Among them, the passivation material can be SiO2, and the thickness is 1-3 um.

[0124] Step Eleven: Etch part of the second insulating passivation layer 701, the first insulating passivation layer 502, and the DBR thin film 501 by photolithography and etching methods to expose the p-contact electrode 401.

[0125] Specifically, it includes the following steps:

[0126] 1. Photolithography Seven: By photolithography technology, using a positive photoresist process, according to the designed pattern, expose part of the second insulating passivation layer 701, that is, the part of the second insulating passivation layer 701 directly above the part covered by the mask in the Photolithography Six process.

[0127] 2. Adopt a wet + dry etching method to etch the exposed area.

[0128] Among them, the etching thickness in this step is relatively thick, including the DBR thin film 501, the first insulating passivation layer 502, and the second insulating passivation layer 701, until the metal surface of the p-contact electrode 401 is exposed.

[0129] Step Twelve: Prepare a p-connection electrode 702 connected to the p-contact electrode 401 by photolithography and evaporation.

[0130] Specifically, it includes the following steps:

[0131] 1. Photolithography Eight: By photolithography technology, make a pattern of the p-connection electrode on the second insulating passivation layer 701, using a negative photoresist process, and expose the area for preparing the p-connection electrode.

[0132] 2. By metal evaporation technology, evaporate the metal of the p-connection electrode.

[0133] Among them, the p-connection electrode metal uses Cr / Al / Ti / Au, and its thickness is 20 / 3000 / 20 / 200 nm. That is, it includes a Cr layer with a thickness of 20 nm, an Al layer with a thickness of 3000 nm, a Ti layer with a thickness of 20 nm, and an Au layer with a thickness of 200 nm stacked in sequence.

[0134] 3. After depositing the p-connection electrode metal, strip and remove the mask to complete the preparation of the p-connection electrode 702.

[0135] In the present invention, through this step, all the p-contact electrodes 401 isolated within the unit chip can be connected by the p-connection electrode 702.

[0136] After this step, the structure shown in Figure 8 is formed.

[0137] Thirteen. Deposit a third insulating passivation layer 801 integrally.

[0138] After preparing the p-connection electrode 702, deposit a third insulating passivation layer 801 integrally.

[0139] In the present invention, the third insulating passivation layer 801 can be deposited by PECVD technology. Among them, the passivation material can be SiO2, and the thickness is 1 - 3 um.

[0140] Fourteen. Etch part of the third insulating passivation layer 801 by photolithography and etching methods to expose the P-connection electrode 702, and etch part of the third insulating passivation layer 801 and the second insulating passivation layer 701 to expose the n-connection electrode 601.

[0141] Specifically, it includes the following steps:

[0142] 1. Photolithography IX. Through photolithography technology, make the area patterns of the p-pad electrode and the n-pad electrode, and expose the p-pad electrode and n-pad electrode areas. That is, expose the third insulating passivation layer 801 in the areas where the p-pad electrode and n-pad electrode are made.

[0143] 2. Through the dry etching process, under the condition of CF4, remove the insulating passivation layer in the exposed area, etch to the metal surface of the p-connection electrode 702 and the metal surface of the n-connection electrode 601 respectively, and then remove the mask.

[0144] Fifteen. Prepare a p-pad electrode 802 connected to the p-connection electrode 702 and an n-pad electrode 901 connected to the n-connection electrode 601 by photolithography and evaporation methods.

[0145] Specifically, it includes the following steps:

[0146] 1. Lithography Step Ten: Using photolithography technology and a negative photoresist process, fabricate the p-pad electrode pattern and the n-pad electrode pattern.

[0147] 2. Deposit pad metal through metal evaporation technology.

[0148] Among them, the pad metal adopts the metal system Ti / Au / Cr / AuSn, and its thickness is 200 / 300 / 20 / 3000 nm. That is, it includes a Ti layer with a thickness of 200 nm, an Au layer with a thickness of 300 nm, a Cr layer with a thickness of 20 nm, and an AuSn layer with a thickness of 3000 nm stacked in sequence.

[0149] 3. After depositing the pad metal, strip and remove the mask to complete the preparation of the p-pad electrode 802 and the n-pad electrode 901.

[0150] Among them, the structure after fabricating the p-pad electrode 802 is as Figure 9 shown. The structure after fabricating the n-pad electrode 901 is as Figure 10 shown.

[0151] Sixteen. Cut the wafer prepared in the fifteenth step into unit die through grinding, polishing, and dicing technologies.

[0152] Among them, the technologies used in this step are all existing technologies, so no detailed description will be given here.

[0153] Seventeen. Conduct optoelectronic tests on the cut unit die to complete the chip preparation.

[0154] The existing preparation technology for traditional large-size and high-power flip-chip structure LED chips is the same as the preparation process flow for small-size and low-power flip-chip structure LED chips. Usually, it is an enlargement based on the original small-size electrode design. However, as the proportion of the injection current increases, the chip performance often fails to reach the theoretical expected effect. For example, a small-size single die can achieve a high electro-optical conversion efficiency, while injecting the same proportion of current after the size is enlarged cannot reach a high electro-optical conversion efficiency. In the present invention, the traditional preparation idea is abandoned. The single die is divided into multiple small units through deep etching, and then the p and n electrodes of the multiple small units are connected through an integration method. Thus, after injecting the same proportion of current, a high current density can be achieved in each small unit area to improve the photoelectric conversion efficiency of the entire die. Secondly, compared with the traditional technology, the present invention introduces a large-area high-reflection thin film, which can reflect part of the light source to the light-emitting surface, reduce the light absorption of the electrodes and other materials, and thus can also improve the light extraction efficiency. Moreover, the segmentation design form of the present invention can not only effectively improve the chip heat dissipation and extend the chip working life compared with the traditional structure, but also has certain benefits for the release of the internal stress of the chip, avoiding the phenomenon that large-size and high-power chips often crack due to temperature rise during long-term operation in the past.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the protection scope of the present invention. Those skilled in the art can modify or equivalently replace the technical solutions of the present invention according to the idea of the present invention, without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A preparation method of an integrated flip-chip LED chip, characterized in that, It includes the following steps: 1). Provide an epitaxial wafer, which sequentially includes a substrate (101), an n-type layer (102), a quantum light-emitting layer (103), and a p-type layer (104) from bottom to top; 2). Etch part of the p-type layer (104) and the quantum light-emitting layer (103) by photolithography and etching methods to etch down to the n-type layer (102) to form an n-contact electrode platform (201); 3). Etch part of the p-type layer (104), the quantum light-emitting layer (103), and the n-type layer (102) adjacent to the n-contact electrode platform (201) by photolithography and etching methods to etch down to the substrate (101) to form a dividing groove (202); the dividing groove (202) includes an in-unit die dividing groove and an inter-unit die dividing groove, and the width of the in-unit die dividing groove is smaller than the width of the inter-unit die dividing groove; 4). Prepare an n-contact electrode (301) on the n-contact electrode platform (201) by photolithography and evaporation methods; 5). Prepare a p-contact electrode (401) on the unetched part of the p-type layer (104) by photolithography and evaporation methods; 6). Evaporate a DBR thin film (501) as a whole; 7). Deposit a first insulating passivation layer (502) as a whole; 8). Etch part of the first insulating passivation layer (502) and the DBR thin film (501) by photolithography and etching methods to expose the n-contact electrode (301); 9). Prepare an n-connection electrode (601) connected to the n-contact electrode (301) by photolithography and evaporation methods; 10). Deposit a second insulating passivation layer (701) as a whole; 11). Etch part of the second insulating passivation layer (701), the first insulating passivation layer (502), and the DBR thin film (501) by photolithography and etching methods to expose the p-contact electrode (401); 12). Prepare a p-connection electrode (702) connected to the p-contact electrode (401) by photolithography and evaporation methods; 13). Deposit a third insulating passivation layer (801) as a whole; 14). Etch part of the third insulating passivation layer (801) by photolithography and etching methods to expose the p-connection electrode (702), and etch part of the third insulating passivation layer (801) and the second insulating passivation layer (701) to expose the n-connection electrode (601); 15). Prepare a p-pad electrode (802) connected to the p-connection electrode (702) and an n-pad electrode (901) connected to the n-connection electrode (601) by photolithography and evaporation methods respectively.

2. The preparation method of the integrated flip-chip LED chip according to claim 1, wherein The width of the in-unit die dividing groove is 5 - 10 μm, and the width of the inter-unit die dividing groove is 15 - 30 μm.

3. The manufacturing method of the integrated flip-chip LED chip according to claim 1, wherein The n-contact electrode (301) is made of a metal system Cr / Al / Ti / Au and its thickness is 10 / 150 / 10 / 200 nm.

4. The preparation method of the integrated flip-chip LED chip according to claim 3, characterized in that, In step 4), after preparing the n-contact electrode (301), high-temperature annealing is carried out by a rapid thermal annealing technique, where the annealing temperature is 500 - 1000 °C, the annealing atmosphere is N2, and the annealing time is 1 - 5 min.

5. The manufacturing method of the integrated flip-chip LED chip according to claim 1, characterized in that, The p-contact electrode (401) is made of a metal system Ni / Au and has a thickness of 10 / 20 nm.

6. The manufacturing method of the integrated flip-chip LED chip according to claim 5, characterized in that, In step 5), after preparing the p-contact electrode (401), high-temperature annealing is carried out by a rapid thermal annealing technique, where the annealing temperature is 500 - 900 °C, the annealing time is 1 - 5 min, and the annealing atmosphere is N2.

7. The preparation method of the integrated flip-chip LED chip according to claim 1, characterized in that The DBR thin film (501) is SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2 / TiO2 / SiO2, and has a thickness of 3 - 5 μm.

8. The preparation method of the integrated flip-chip LED chip according to claim 1, characterized in that The first insulating passivation layer (502), the second insulating passivation layer (701), and the third insulating passivation layer (801) are all made of SiO2 and have a thickness of 1 - 3 μm.

9. The preparation method of the integrated flip-chip LED chip according to claim 1, characterized in that, In step 9), a negative photoresist process is used in lithography, and a mask is used to block a partial area directly above the p-contact electrode (401) so that the n-connection electrode (601) is not prepared thereon.

10. The manufacturing method of the integrated flip-chip LED chip according to claim 9, characterized in that, In step 11), the part etched is the part opposite to the part blocked by the mask.

11. The preparation method of the integrated flip-chip LED chip according to claim 1, characterized in that, The p-connection electrode (702) is made of a metal system Cr / Al / Ti / Au and has a thickness of 20 / 3000 / 20 / 200 nm.

12. The preparation method of the integrated flip-chip LED chip according to claim 1, characterized in that, The p-pad electrode (802) and the n-pad electrode (901) are made of a metal system Ti / Au / Cr / AuSn and have a thickness of 200 / 300 / 20 / 3000 nm.

13. The preparation method of the integrated flip-chip LED chip according to any one of claims 1-12, characterized in that, Further comprising: 16), cutting the wafer prepared in step 15) into unit die by grinding, polishing, and dicing techniques.

14. The preparation method of the integrated flip-chip LED chip according to claim 13, wherein Further comprising: 17), performing optoelectronic tests on the cut unit die to complete chip preparation.

15. An integrated flip-chip LED chip, characterized in that, It is prepared by using the preparation method described in any one of claims 1 - 14 herein.

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