LED epitaxial structure and preparation method thereof

Abstract

The application provides an LED epitaxial structure and a preparation method thereof. The LED epitaxial structure comprises a strain buffer layer, a cutoff layer, a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on a substrate. The strain buffer layer comprises a low-temperature buffer layer, a high-temperature isolation layer, a first superlattice buffer layer and a second superlattice buffer layer which are sequentially stacked. The low-temperature buffer layer is located between the substrate and the high-temperature isolation layer. The second superlattice buffer layer is located between the first superlattice buffer layer and the cutoff layer. The setting of the strain buffer layer can improve the crystal quality of the LED epitaxial structure, and thus the brightness of the light-emitting diode can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an LED epitaxial structure and its fabrication method. Background Technology

[0002] As a new light source, LED (Light Emitting Diode) semiconductor lamps consume only 1 / 10 the power of ordinary incandescent lamps at the same brightness, while their lifespan can be extended by 100 times. Moreover, LED semiconductor lamps are cold light sources, possessing advantages such as: high luminous efficacy, low operating voltage, low power consumption, small size, planar packaging, ease of developing thin and light products, robust structure and long lifespan, the light source itself does not contain harmful substances such as mercury and lead, has no infrared or ultraviolet pollution, and does not generate pollution to the environment during production and use. Therefore, whether from the perspective of saving energy, reducing greenhouse gas emissions, or reducing environmental pollution, LEDs have great potential to replace traditional lighting sources.

[0003] As people's requirements for lighting sources become increasingly demanding, it is essential to invent a brighter light-emitting diode (LED). Summary of the Invention

[0004] The purpose of this invention is to provide an LED epitaxial structure and its fabrication method to improve the brightness of light-emitting diodes.

[0005] To achieve the above and other related objectives, the present invention provides an LED epitaxial structure comprising a strain buffer layer, a cutoff layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially on a substrate. The strain buffer layer comprises a low-temperature buffer layer, a high-temperature isolation layer, a first superlattice buffer layer, and a second superlattice buffer layer stacked sequentially. The low-temperature buffer layer is located between the substrate and the high-temperature isolation layer, and the second superlattice buffer layer is located between the first superlattice buffer layer and the cutoff layer.

[0006] Optionally, in the LED epitaxial structure, the material of the low-temperature buffer layer includes GaAs; the material of the high-temperature isolation layer includes GaAs; the first superlattice buffer layer includes a superlattice structure composed of a first GaAsP layer and a GaAs layer; and the second superlattice buffer layer includes a superlattice structure composed of a second GaAsP layer and a GaInP layer.

[0007] Optionally, in the LED epitaxial structure, the material of the first GaAsP layer includes Ga... 0.5 (As x P 1-x ) 0.50.75 < x < 0.95; the material of the second GaAsP layer includes Ga 0.5 (As y P 1-y ) 0.5 0.75 < y < 0.95; the material of the GaInP layer includes Ga 0.25 In 0.25 P 0.5 .

[0008] Optionally, in the LED epitaxial structure, the As content in the first GaAsP layer is not greater than the As content in the second GaAsP layer.

[0009] Optionally, in the LED epitaxial structure, the growth cycle number of the first superlattice buffer layer is 10 to 20, wherein the thickness of the first GaAsP layer in each cycle is 5 nm to 20 nm; and the thickness of the GaAs layer in each cycle is 5 nm to 20 nm.

[0010] Optionally, in the LED epitaxial structure, the growth cycle number of the second superlattice buffer layer is 10 to 20, wherein the thickness of the second GaAsP layer in each cycle is 5 nm to 20 nm; and the thickness of the GaInP layer in each cycle is 5 nm to 20 nm.

[0011] Optionally, in the LED epitaxial structure, the thickness of the low-temperature buffer layer is 100nm to 300nm, and the low-temperature buffer layer is an unintentionally doped layer.

[0012] Optionally, in the LED epitaxial structure, the thickness of the high-temperature isolation layer is 100nm to 300nm, and the high-temperature isolation layer is an unintentionally doped layer.

[0013] Optionally, in the LED epitaxial structure, the first type of semiconductor layer includes a first type of ohmic contact layer, a first type of window layer, a first type of confinement layer, and a first barrier layer stacked sequentially, wherein the first type of ohmic contact layer is located between the cut-off layer and the first type of window layer, and the first barrier layer is located between the first type of confinement layer and the active layer.

[0014] Optionally, in the LED epitaxial structure, the material of the first type of ohmic contact layer includes (Al) c Ga 1-c ) 0.25 In 0.25 P 0.5 , 0.3 < c < 0.9; the thickness of the first type of ohmic contact layer is 100 nm to 200 nm.

[0015] Optionally, in the LED epitaxial structure, the second type semiconductor layer includes a second barrier layer, a second type confinement layer, a second type current spreading layer, and a second type ohmic contact layer stacked sequentially, and the second barrier layer is located between the active layer and the second type confinement layer.

[0016] Optionally, in the LED epitaxial structure, the first type semiconductor layer is an N-type semiconductor layer, and the second type semiconductor layer is a P-type semiconductor layer.

[0017] Optionally, in the LED epitaxial structure, the substrate includes a GaAs substrate.

[0018] To achieve the above and other related objectives, the present invention also provides a method for fabricating an LED epitaxial structure, comprising the following steps:

[0019] Provide a substrate;

[0020] A strain buffer layer is grown on the substrate. The strain buffer layer includes a low-temperature buffer layer, a high-temperature isolation layer, a first superlattice buffer layer, and a second superlattice buffer layer stacked sequentially. The low-temperature buffer layer is located between the substrate and the high-temperature isolation layer, and the second superlattice buffer layer is located between the first superlattice buffer layer and the cutoff layer.

[0021] A stop layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer are sequentially grown on the strain buffer layer.

[0022] Optionally, in the method for fabricating the LED epitaxial structure, the step of growing a strain buffer layer on the substrate includes:

[0023] The low-temperature buffer layer and the high-temperature isolation layer are sequentially grown on the substrate;

[0024] A high-temperature annealing process is performed on the structure with the aforementioned low-temperature buffer layer and high-temperature isolation layer.

[0025] A first superlattice buffer layer and a second superlattice buffer layer are sequentially grown on the high-temperature isolation layer.

[0026] Optionally, in the method for preparing the LED epitaxial structure, the high-temperature annealing process includes: cyclic annealing between a first temperature and a second temperature in an H2 atmosphere, and maintaining the second temperature for a set time after each cycle.

[0027] Optionally, in the method for preparing the LED epitaxial structure, the first temperature range is 400℃~500℃; the second temperature range is 700℃~800℃; and the set time is 5min~20min.

[0028] Optionally, in the method for fabricating the LED epitaxial structure, the growth temperature of the low-temperature buffer layer is 550℃~650℃; the growth temperature of the high-temperature isolation layer is 650℃~750℃; the growth temperature of the first superlattice buffer layer is 650℃~750℃; and the growth temperature of the second superlattice buffer layer is 650℃~750℃.

[0029] Optionally, in the method for fabricating the LED epitaxial structure, the material of the low-temperature buffer layer includes GaAs; the material of the high-temperature isolation layer includes GaAs; the first superlattice buffer layer includes a superlattice structure composed of a first GaAsP layer and a GaAs layer; and the second superlattice buffer layer includes a superlattice structure composed of a second GaAsP layer and a GaInP layer.

[0030] Optionally, in the method for fabricating the LED epitaxial structure, the material of the first GaAsP layer includes Ga... 0.5 (As x P 1-x ) 0.5 0.75 < x < 0.95; the material of the second GaAsP layer includes Ga 0.5 (As y P 1-y ) 0.5 0.75 < y < 0.95; the material of the GaInP layer includes Ga 0.25 In 0.25 P 0.5 .

[0031] Optionally, in the method for preparing the LED epitaxial structure, the As content in the first GaAsP layer is not greater than the As content in the second GaAsP layer.

[0032] Optionally, in the method for fabricating the LED epitaxial structure, the number of growth cycles of the first superlattice buffer layer is 10 to 20, wherein the thickness of the first GaAsP layer in each cycle is 5 nm to 20 nm; and the thickness of the GaAs layer in each cycle is 5 nm to 20 nm.

[0033] Optionally, in the method for fabricating the LED epitaxial structure, the number of growth cycles of the second superlattice buffer layer is 10 to 20, wherein the thickness of the second GaAsP layer in each cycle is 5 nm to 20 nm; and the thickness of the GaInP layer in each cycle is 5 nm to 20 nm.

[0034] Optionally, in the method for preparing the LED epitaxial structure, the thickness of the low-temperature buffer layer is 100nm to 300nm, and the low-temperature buffer layer is an unintentionally doped layer.

[0035] Optionally, in the method for preparing the LED epitaxial structure, the thickness of the high-temperature isolation layer is 100nm to 300nm, and the high-temperature isolation layer is an unintentionally doped layer.

[0036] Optionally, in the method for fabricating the LED epitaxial structure, the first type semiconductor layer includes a first type ohmic contact layer, a first type window layer, a first type confinement layer, and a first barrier layer stacked sequentially, wherein the first type ohmic contact layer is located between the cutoff layer and the first type window layer, and the first barrier layer is located between the first type confinement layer and the active layer.

[0037] Optionally, in the method for fabricating the LED epitaxial structure, the material of the first type of ohmic contact layer includes (Al) c Ga 1-c ) 0.25 In 0.25 P 0.5 , 0.3 < c < 0.9; the thickness of the first type of ohmic contact layer is 100 nm to 200 nm.

[0038] Optionally, in the method for fabricating the LED epitaxial structure, the second type semiconductor layer comprises, from bottom to top, a second barrier layer, a second type confinement layer, a second type current spreading layer, and a second type ohmic contact layer, and the second barrier layer is located between the active layer and the second type confinement layer.

[0039] Optionally, in the method for fabricating the LED epitaxial structure, the first type semiconductor layer is an N-type semiconductor layer, and the second type semiconductor layer is a P-type semiconductor layer.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] This invention adopts an epitaxial structure scheme of AlGaInP type-1 ohmic contact layer, replacing the existing technology scheme of using GaAs type-1 ohmic contact layer. This can avoid the problem of reduced light output from the front due to light absorption by GaAs material, thereby improving brightness and reliability.

[0042] Secondly, the entire LED epitaxial structure of this invention uses AlInP, AlGaInP, and AlGaAs lattice-matched materials, which makes the crystal quality of the LED epitaxial structure higher, thereby improving the brightness, luminous efficiency, and reliability of the light-emitting diode.

[0043] Furthermore, the present invention inserts a strain buffer layer between the substrate and the first type of ohmic contact layer, which can reduce the lattice mismatch and thermal mismatch between the substrate and the first type of ohmic contact layer, improve crystal quality, and thus improve brightness and reliability.

[0044] Furthermore, in the process of preparing the strain buffer layer, this invention first grows a low-temperature buffer layer on the substrate to annihilate defects on the substrate surface and obtain a smooth surface; then, a high-temperature isolation layer is grown to prevent impurities in the substrate from entering the epitaxial structure during the growth process; next, high-temperature annealing is performed in an H2 atmosphere to improve the crystal quality of the underlying GaAs layer (e.g., the high-temperature isolation layer), laying the foundation for growing a high-quality epitaxial structure; subsequently, elemental transition and mismatch stress are released by growing a first superlattice buffer layer and a second superlattice buffer layer. Therefore, high-quality LED epitaxial structures can be obtained using the strain buffer layer described above. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the LED epitaxial structure according to Embodiment 1 of the present invention;

[0046] Figure 2 This is a schematic diagram of the strain buffer layer according to Embodiment 1 of the present invention;

[0047] Figure 3 This is a flowchart of the method for preparing the LED epitaxial structure according to Embodiment 1 of the present invention;

[0048] Figures 1-3 middle:

[0049] 10-Substrate, 11-Epitaxial structure, 12-Strain buffer layer, 11A-Low temperature buffer layer, 11B-High temperature isolation layer, 11C-First superlattice buffer layer, 11D-Second superlattice buffer layer, 12-Stop layer, 13-Type I ohmic contact layer, 14-Type I window layer, 15-Type I confinement layer, 16-First barrier layer, 17-Active layer, 18-Second barrier layer, 19-Type II confinement layer, 20-Type II current spreading layer, 21-Type II ohmic contact layer. Detailed Implementation

[0050] The LED epitaxial structure and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0051] Before describing the embodiments according to the present invention, the following will be explained in advance. First, in this specification, binary materials are assumed to be compounds with a fixed chemical composition ratio of 1:1. When only "AlInP" is used, it indicates any compound in which the chemical composition ratio of the sum of Al and In to P is 1:1, and the ratio of Al to In is not fixed. When only "GaInP" is used, it indicates any compound in which the chemical composition ratio of the sum of Ga and In to P is 1:1, and the ratio of Ga to In is not fixed.

[0052] To improve brightness, this invention provides an LED epitaxial structure; please refer to [link / reference]. Figure 1 The LED epitaxial structure includes a strain buffer layer 11, a cutoff layer 12, a first type semiconductor layer, an active layer 17, and a second type semiconductor layer stacked sequentially on a substrate 10. The strain buffer layer 11 includes a low-temperature buffer layer 11A, a high-temperature isolation layer 11B, a first superlattice buffer layer 11C, and a second superlattice buffer layer 11D stacked sequentially. The low-temperature buffer layer 11A is located between the substrate 10 and the high-temperature isolation layer 11B, and the second superlattice buffer layer 11D is located between the first superlattice buffer layer 11C and the cutoff layer 12.

[0053] The LED epitaxial structure in this embodiment is preferably a deep red LED epitaxial structure, such as a deep red LED epitaxial structure with an emission wavelength of 630nm, but it is not limited to this.

[0054] In this embodiment, the first type of semiconductor layer includes a first type of ohmic contact layer 13, a first type of window layer 14, a first type of confinement layer 15, and a first barrier layer 16 stacked sequentially, wherein the first type of ohmic contact layer 13 is an AlGaInP layer. This embodiment replaces the existing GaAs-based first type of ohmic contact layer with an epitaxial structure using an AlGaInP material first type of ohmic contact layer grown on the substrate 10. This avoids the problem of reduced front-side light emission due to light absorption by GaAs, thereby improving brightness and reliability.

[0055] See Figure 2In this embodiment, the strain buffer layer 11 includes a low-temperature buffer layer 11A, a high-temperature isolation layer 11B, a first superlattice buffer layer 11C, and a second superlattice buffer layer 11D stacked sequentially. The low-temperature buffer layer 11A is located between the substrate 10 and the low-temperature buffer layer 11A, and the second superlattice buffer layer 11D is located between the first superlattice buffer layer 11C and the cutoff layer 12. Further, the material of the low-temperature buffer layer 11A is preferably GaAs, but not limited to it. The material of the high-temperature isolation layer 11B is preferably GaAs, but not limited to it. The first superlattice buffer layer 11C can be a superlattice structure composed of a first GaAsP layer and a GaAs layer. The second superlattice buffer layer 11D can be a superlattice structure composed of a second GaAsP layer and a GaInP layer. In this embodiment, the insertion of the strain buffer layer 11 can reduce the lattice mismatch and thermal mismatch between the substrate 10 and the first-type ohmic contact layer 13, thereby improving the crystal quality.

[0056] In this embodiment, the second type semiconductor layer includes, from bottom to top, a second barrier layer 18, a second type confinement layer 19, a second type current spreading layer 20, and a second type ohmic contact layer 21, and the second barrier layer 18 is located between the active layer 17 and the second type confinement layer 19.

[0057] In this embodiment, the first type of semiconductor layer is preferably an N-type semiconductor layer, and the second type of semiconductor layer is preferably a P-type semiconductor layer. For example, the first type of semiconductor layer includes an N-type ohmic contact layer, an N-type window layer, an N-type confinement layer, and a first barrier layer stacked sequentially, and the second type of semiconductor layer includes a second barrier layer, a P-type confinement layer, a P-type current spreading layer, and a P-type ohmic contact layer stacked sequentially.

[0058] See Figure 3 The above-described method for fabricating the LED epitaxial structure is illustrated, specifically including the following steps:

[0059] Step S1: Provide a substrate 10;

[0060] Step S2: A strain buffer layer 11 is grown on the substrate 10. The strain buffer layer includes a low-temperature buffer layer 11A, a high-temperature isolation layer 11B, a first superlattice buffer layer 11C, and a second superlattice buffer layer 11D stacked sequentially. The low-temperature buffer layer 11A is located between the substrate 10 and the high-temperature isolation layer 11B, and the second superlattice buffer layer 11D is located between the first superlattice buffer layer 11C and the cutoff layer 12.

[0061] Step S3: Sequentially grow a stop layer 12, a first type semiconductor layer, an active layer 17, and a second type semiconductor layer on the strain buffer layer 11.

[0062] The fabrication process of the LED epitaxial structure can be any one of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or ultra-high vacuum chemical vapor deposition (UHVCVD), preferably MOCVD. The following specific embodiments use MOCVD as an example for illustration.

[0063] Step S1 is performed to provide a substrate 10. In this embodiment, the substrate 10 is a GaAs substrate.

[0064] Step S2 is performed to grow a strain buffer layer 11 on the substrate 10. Because GaAs and AlGaInP materials have significant lattice and thermal mismatches, directly epitaxially growing AlGaInP (type-1 ohmic contact layer 13) on the substrate 10 (e.g., a GaAs substrate) will cause a sharp deterioration in crystal quality due to the large mismatch stress. This invention alleviates this problem by inserting a strain buffer layer 11 between the substrate 10 and the type-1 ohmic contact layer 13. That is, the strain buffer layer 11 can alleviate the lattice and thermal mismatches between the substrate 10 and the type-1 semiconductor layer, especially between the GaAs substrate and the type-1 ohmic contact layer 13, thereby improving crystal quality and optical efficiency. In this embodiment, the strain buffer layer 11 may include a low-temperature buffer layer 11A, a high-temperature isolation layer 11B, a first superlattice buffer layer 11C, and a second superlattice buffer layer 11D stacked sequentially. Therefore, the step of growing the strain buffer layer 11 on the substrate 10 includes:

[0065] The low-temperature buffer layer 11A and the high-temperature isolation layer 11B are sequentially grown on the substrate;

[0066] A high-temperature annealing process is performed on the structure with the low-temperature buffer layer 11A and the high-temperature isolation layer 11B grown thereon.

[0067] A first superlattice buffer layer 11C and a second superlattice buffer layer 11D are sequentially grown on the high-temperature isolation layer 11B.

[0068] In step S2, the first step is to grow a low-temperature buffer layer 11A on the substrate 10. The material of the low-temperature buffer layer 11A is preferably GaAs, and the low-temperature buffer layer 11A is an unintentionally doped layer. In this embodiment, a low-temperature buffer layer 11A with a thickness of 100 nm to 300 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a low-temperature buffer layer 11A with a thickness of 200 nm is grown. In this embodiment, growing a low-temperature buffer layer 11A of GaAs material with relatively poor crystal quality at a low temperature can annihilate defects on the surface of the substrate 10, and release stress by utilizing dislocations and defects in the low-temperature buffer layer 11A. Therefore, the growth temperature of the low-temperature buffer layer 11A is 550°C to 650°C, for example, 580°C. If the temperature of this layer is too low, the crystal quality of the low-temperature buffer layer 11A will be too poor, and its effect will be counterproductive; while if the temperature of this layer is too high, the purpose of stress release cannot be achieved.

[0069] After the step of growing the low-temperature buffer layer 11A, a high-temperature isolation layer 11B is grown on the low-temperature buffer layer 11A. The high-temperature isolation layer 11B is preferably made of GaAs and is an unintentionally doped layer. In this embodiment, a high-temperature isolation layer 11B with a thickness of 100 nm to 300 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a high-temperature isolation layer 11B with a thickness of 200 nm is grown.

[0070] In this embodiment, the growth temperature of the high-temperature isolation layer 11B is preferably higher than that of the low-temperature buffer layer 11A. Higher growth temperatures result in better GaAs crystal quality. Since a growth temperature above 750°C exceeds the suitable growth temperature for GaAs, the growth temperature of the high-temperature isolation layer 11B is preferably 650–750°C, for example, 700°C. In this embodiment, a high-temperature isolation layer 11B of high-quality GaAs material is grown at high temperature, i.e., a denser GaAs layer, to prevent impurities and defects from the lower layer (substrate 10 and low-temperature buffer layer 11A) from entering the upper epitaxial structure, resulting in a smooth and clean epitaxial growth surface.

[0071] After the step of growing the high-temperature isolation layer 11B, a high-temperature annealing process is performed on the structure with the low-temperature buffer layer 11A and the high-temperature isolation layer 11B grown. The high-temperature annealing process includes: cyclic annealing between a first temperature and a second temperature in an H2 atmosphere, and maintaining the second temperature for a set time after each cycle. In this embodiment, the first temperature is preferably in the range of 400℃ to 500℃, the second temperature is preferably in the range of 700℃ to 800℃, and the number of cycles is preferably 1 to 3. Performing thermal cyclic annealing within the above temperature range can effectively reduce the through-dislocation density in the high-temperature isolation layer 11B, improve crystal quality, and lay the foundation for growing a high-quality epitaxial structure. In this embodiment, the set time is preferably 5 min to 20 min. For example, cyclic annealing is performed between 450℃ and 720℃ in an H2 atmosphere, and maintaining the temperature at 720℃ for 10 min after each cycle.

[0072] After performing the high-temperature annealing process, a first superlattice buffer layer 11C is grown on the high-temperature isolation layer 11B. The first superlattice buffer layer 11C can be a superlattice structure composed of a first GaAsP layer and a GaAs layer, and its growth cycle number is preferably 10 to 20, for example, 15. The first superlattice buffer layer 11C is an unintentionally doped layer.

[0073] The GaAs layer is made of GaAs, and the first GaAsP layer is preferably made of Ga. 0.5 (As x P 1-x ) 0.5 And 0.75 < x < 0.95, for example, Ga 0.5 (As 0.8 P 0.2 ) 0.5 The higher the As content in the first GaAsP layer, the closer the lattice constant is to GaAs and GaInP. If the As content is too low, although elemental transition is achieved, the large difference in lattice constants will also cause lattice mismatch. The thickness of the first GaAsP layer in each period is preferably 5nm to 20nm, for example, 10nm. The thickness of the GaAs layer in each period is preferably 5nm to 20nm, for example, 10nm. The function of the superlattice structure of the first superlattice buffer layer 11C is to generate a quantum confinement effect by alternating growth of two thin layers of first GaAsP and GaAs, concentrating stress within the superlattice layer to release the stress of the epitaxial layer. If the thickness of the first GaAsP layer and GaAs layer is too thick or too thin, the quantum confinement effect will be weakened, and the above effect will not be achieved.

[0074] In this embodiment, the first superlattice buffer layer 11C is preferably grown in the reaction chamber of an MOCVD growth furnace. Furthermore, the growth temperature of the first superlattice buffer layer 11C is preferably 650°C to 750°C, for example, 700°C. Temperatures exceeding this range are unsuitable for the growth of GaAs and GaAsP. In this embodiment, the growth temperature of the first GaAsP layer is preferably the same as the growth temperature of the GaAs layer to reduce time loss due to temperature increases and decreases during the growth process.

[0075] After growing the first superlattice buffer layer 11C, a second superlattice buffer layer 11D is grown on the first superlattice buffer layer 11C. The second superlattice buffer layer 11D can be a superlattice structure composed of a second GaAsP layer and a GaInP layer, and its growth period number is preferably 10 to 20, for example, 15. The second superlattice buffer layer 11D is an unintentionally doped layer.

[0076] The material of the GaInP layer is preferably Ga. 0.25 In 0.25 P 0.5 The lattice constant of this material is closest to that of GaAs. The preferred material for the second GaAsP layer is Ga... 0.5 (As y P 1-y ) 0.5 And 0.75 < y < 0.95, for example, Ga 0.5 (As 0.8 P 0.2 ) 0.5 The higher the As content in the second GaAsP layer, the closer the lattice constant is to GaAs and GaInP. If the As content is too low, although elemental transition is achieved, the large difference in lattice constants will also cause lattice mismatch. In this embodiment, the As content in the first GaAsP layer is not greater than the As content in the second GaAsP layer. The superlattice structure of the first superlattice buffer layer 11C and the second superlattice buffer layer 11D can play a role in the transition of elements and lattice constants, and the subsequently grown Ga... 0.5 In 0.5 The lattice constant of P is 5.66, that of GaAs is 5.65, and that of GaP is 5.45. This means that in GaAsP, the higher the As content, the closer the lattice constant is to GaInP. A transition effect can be achieved when the As content in the second superlattice buffer layer 11D is greater than or equal to the As content in the first superlattice buffer layer 11C. Preferably, the As content in the second superlattice buffer layer 11D is equal to the As content in the first superlattice buffer layer 11C.

[0077] In this embodiment, the thickness of the second GaAsP layer in each cycle is preferably 5 nm to 20 nm, for example, 10 nm. The thickness of the GaInP layer in each cycle is preferably 5 nm to 20 nm, for example, 10 nm. The function of the superlattice structure of the second superlattice buffer layer 11D is to generate a quantum confinement effect by alternating growth of two thin layers of second GaAsP and GaInP, concentrating stress within the superlattice layer to release the stress of the epitaxial layer. If the thickness of the second GaAsP layer and GaInP layer is too thick or too thin, the quantum confinement effect will be weakened, and the desired effect will not be achieved.

[0078] In this embodiment, the second superlattice buffer layer 11D is preferably grown in the reaction chamber of an MOCVD growth furnace. Furthermore, the growth temperature of the second superlattice buffer layer 11D is preferably 650°C to 750°C, for example, 700°C. Temperatures exceeding this range are unsuitable for the growth of GaAsP and GaInP. In this embodiment, the growth temperature of the second GaAsP layer is preferably the same as that of the GaInP layer. Furthermore, the growth temperature of the second superlattice buffer layer 11D is preferably the same as that of the first superlattice buffer layer 11C, to reduce the time loss caused by heating and cooling during the growth process.

[0079] In this embodiment, the superlattice structure of the first superlattice buffer layer 11C and the second superlattice buffer layer 11D serves to generate a quantum confinement effect through the alternating growth of two thin layers in the superlattice structure, concentrating stress within the superlattice layer to release the stress of the epitaxial layer. Simultaneously, the two superlattice structures act as transition layers for elements and lattice constants; that is, the first superlattice buffer layer 11C transitions from GaAs to GaAsP, and the second superlattice buffer layer 11D transitions from GaAsP to GaInP. The lattice constant of GaAs is 5.65, and the lattice constant of GaP is 5.45. This means that in GaAsP, the higher the As content, the closer the lattice constant is to that of GaInP (GaAsP). 0.5 In 0.5 P: 5.66).

[0080] Step S3 is performed after the growth of the strain buffer layer 11, followed by the growth of a stop layer 12 on the strain buffer layer 11. The stop layer 12 is primarily used to protect the epitaxial structure layer grown on the substrate 10, i.e., to protect the first-type ohmic contact layer 13, during the stripping of the substrate 10. The material of the stop layer 12 is preferably GaInP, but not limited to it. The stop layer 12 is doped with a first-type dopant, such as an N-type dopant, which can be at least one of silicon (Si) and tellurium (Te), but is not limited to it. Further, the first-type dopant is preferably Te. Further, the doping concentration of the first-type dopant is preferably 5E17cm⁻¹. -3 ~5E18cm-3 For example, 2E18cm -3 .

[0081] In this embodiment, a stop layer 12 with a thickness of 100 nm to 400 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a stop layer 12 with a thickness of 200 nm is grown.

[0082] After the step of growing the stop layer 12, a first type semiconductor layer is grown on the stop layer 12. The first type semiconductor layer includes a first type ohmic contact layer 13, a first type window layer 14, and a first type confinement layer 15 stacked sequentially.

[0083] Therefore, after the step of growing the stop layer 12, the first type of ohmic contact layer 13 is grown on the stop layer 12. The material of the first type of ohmic contact layer 13 is preferably (Al). c Ga 1-c ) 0.25 In 0.25 P 0.5 And 0.3 < c < 0.9, for example (Al) 0.7 Ga 0.3 ) 0.25 In 0.25 P 0.5 This embodiment replaces the existing GaAs ohmic contact layer with an AlGaInP ohmic contact layer. After chip manufacturing, the GaAs in the front light-emitting direction is completely removed, thus avoiding the problem of reduced front light emission caused by GaAs light absorption when using GaAs as the ohmic contact layer.

[0084] The first type ohmic contact layer 13 is doped with a type I dopant, such as an N-type dopant, which can be silicon (Si) or tellurium (Te), but is not limited to these. Since the material of the first type ohmic contact layer 13 in this embodiment is AlGaInP, it would be difficult to achieve high doping (>1E19cm) if Si were used as the type I dopant. -3 Furthermore, the crystal quality of the epitaxial layer doped with Te is superior to that of the epitaxial layer doped with Si, resulting in fewer defects and better light emission. Since the purpose of this invention is to fabricate high-brightness light-emitting diodes, Te doping is preferred. More specifically, the first type of dopant is preferably Te. ， Furthermore, the preferred doping concentration is >1E19cm. -3 For example, 1.5E19cm -3 .

[0085] In this embodiment, a first type ohmic contact layer 13 with a thickness of 100 nm to 200 nm is preferably grown in the reaction chamber of the MOCVD growth furnace, for example, a first type ohmic contact layer 13 with a thickness of 120 nm is grown.

[0086] After the step of growing the first type ohmic contact layer 13, the first type window layer 14 is grown on the first type ohmic contact layer 13. The main functions of the first type window layer 14 are first type current expansion, light emission, and surface roughening.

[0087] The material of the first type window layer 14 is preferably AlInP, but not limited to it. The first type window layer 14 is doped with a type-1 dopant, such as an N-type dopant, which can be at least one of silicon (Si) and tellurium (Te), but is not limited to it. Further, the first type dopant is preferably Te. The doping concentration of the first type dopant is preferably 5E17cm⁻¹. -3 ~5E18cm -3 For example, 2E18cm -3 .

[0088] In this embodiment, a first type window layer 14 with a thickness of 1 μm to 5 μm is preferably grown in the reaction chamber of an MOCVD growth furnace, for example, a first type window layer 14 with a thickness of 2.5 μm is grown.

[0089] After the step of growing the first type window layer 14, the first type confinement layer 15 is grown on the first type window layer 14. The material of the first type confinement layer 15 is preferably AlInP, but not limited thereto. The first type confinement layer 15 is doped with a first type dopant, such as an N-type dopant, which can be at least one of silicon (Si) and tellurium (Te), but is not limited thereto. Further, the first type dopant is preferably Te. Further, the doping concentration is 1E18cm⁻¹. -3 ~8E18cm -3 For example, 5E18cm -3 .

[0090] In this embodiment, a first type confinement layer 15 with a thickness of 400 nm to 800 nm is preferably grown in the reaction chamber of an MOCVD growth furnace, for example, a first type confinement layer 15 with a thickness of 450 nm is grown.

[0091] After the step of growing the first type confinement layer 15, the first barrier layer 16 is grown on the first type confinement layer 105. The material of the first barrier layer 16 is preferably AlGaInP, but not limited thereto. Furthermore, the composition of the first barrier layer 16 is preferably consistent with that of the quantum barrier layer. The first barrier layer 16 is preferably an unintentionally doped layer.

[0092] In this embodiment, a first barrier layer 16 with a thickness of 200 nm to 500 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a first barrier layer 16 with a thickness of 250 nm is grown.

[0093] After the step of growing the first type of semiconductor layer, the active layer 17 is grown on the first type of semiconductor layer. The active layer 17 is preferably made of GaInP / AlGaInP. Specifically, the active layer 17 includes a quantum well layer and a quantum barrier layer, and the quantum well layer is preferably made of GaInP. 0.5 In 0.5 P, but not limited to this. The preferred material of the quantum barrier layer is (Al). z Ga 1-z ) 0.25 In 0.25 P 0.5 , 0.5≤z≤0.9, for example z=0.8.

[0094] In this embodiment, the active layer 17 is preferably grown for 10 to 40 cycles in the reaction chamber of an MOCVD growth furnace, for example, for 20 cycles. The overall thickness of the active layer 17 is preferably 150 nm to 600 nm, for example, 500 nm.

[0095] After the step of growing the active layer 17, a second type semiconductor layer is grown on the active layer 17. The second type semiconductor layer includes, from bottom to top: a second barrier layer 18, a second type confinement layer 19, a second type window layer 212, and a second type ohmic contact layer 21.

[0096] Therefore, after growing the active layer 17, a second barrier layer 18 is grown on the active layer 17. The second barrier layer 18 is preferably made of AlGaInP, but is not limited to this. Furthermore, the composition of the second barrier layer 18 is preferably consistent with that of the quantum barrier layer. The second barrier layer 18 is an unintentionally doped layer.

[0097] In this embodiment, a second barrier layer 18 with a thickness of 300 nm to 600 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a second barrier layer 18 with a thickness of 400 nm is grown.

[0098] After growing the second barrier layer 18, a second type confinement layer 19 is grown on the second barrier layer 18. The second type confinement layer 19 is used to provide holes. Moreover, the first type confinement layer 15 and the second type confinement layer 19 serve two main functions as confinement layers: firstly, they restrict minority carriers from overflowing the active layer 17, thereby improving recombination luminescence efficiency; secondly, they act as an important window, allowing photons emitted from the active layer 17 to easily pass through the confinement layer, thereby improving the luminescence efficiency of the light-emitting diode.

[0099] The material of the second type confinement layer 19 is preferably AlInP, but not limited to it. The second type confinement layer 19 is doped with a type II dopant, such as a p-type dopant, which can be at least one of magnesium (Mg) and zinc (Zn), but is not limited to it. Further, the second type dopant is preferably Mg, and the doping concentration is preferably 1E18cm⁻¹. -3 ~8E18cm -3 For example, 5E18cm -3 .

[0100] In this embodiment, a second type confinement layer 19 with a thickness of 300 nm to 800 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a second type confinement layer 19 with a thickness of 500 nm is grown.

[0101] After growing the second type confinement layer 19, a second type current spreading layer 20 is grown on the second type confinement layer 19. The second type current spreading layer 20 is used for current spreading to prevent uneven current distribution on the light-emitting diode. The material of the second type current spreading layer 20 is preferably AlInP, but not limited to it. The doping source of the second type current spreading layer 20 is preferably Mg, but not limited to it. Further, the doping concentration is preferably 5E17cm⁻¹. -3 ~5E18cm -3 For example, 3E18cm -3 .

[0102] In this embodiment, a type II current spreading layer 20 with a thickness of 500 nm to 3000 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a type II current spreading layer 20 with a thickness of 1500 nm is grown.

[0103] After the step of growing the second type current spreading layer 20, a second type ohmic contact layer 21 is grown on the second type current spreading layer 20. The second type ohmic contact layer 21 is used to form an ohmic contact with the metal electrode. The material of the second type ohmic contact layer 21 is preferably AlGaAs, specifically (Al... n Ga 1-n As 0.5 The n value is greater than or equal to 0.7, but is not limited thereto. The second type of ohmic contact layer 21 may be doped with carbon (C), and the doping concentration is preferably greater than 1E19 cm⁻¹. -3 For example, 2E19cm -3 .

[0104] In this embodiment, a second-type ohmic contact layer 21 with a thickness of 100 nm to 300 nm is preferably grown in the reaction chamber of an MOCVD growth furnace. For example, a second-type ohmic contact layer 21 with a thickness of 150 nm is grown.

[0105] In summary, the present invention uses a first-type ohmic contact layer made of AlGaInP material, replacing the first-type ohmic contact layer made of GaAs in the prior art. This can avoid the problem of reduced light emission from the front due to light absorption by GaAs material, thereby improving light efficiency and brightness.

[0106] Secondly, the entire LED epitaxial structure of this invention uses AlInP, AlGaInP, and AlGaAs lattice-matched materials, resulting in high crystal quality and improved chip brightness, luminous efficiency, and reliability.

[0107] Moreover, the present invention can reduce the lattice mismatch and thermal mismatch between the substrate and the first type of ohmic contact layer by inserting a strain buffer layer, thereby improving the crystal quality.

[0108] Furthermore, in the process of preparing the strain buffer layer, this invention first grows a low-temperature buffer layer on the substrate to annihilate defects on the substrate surface and obtain a smooth surface; then, a high-temperature isolation layer is grown to prevent impurities in the substrate from entering the epitaxial structure during growth; next, high-temperature annealing is performed in an H2 atmosphere to improve the crystal quality of the underlying GaAs layer, laying the foundation for growing a high-quality epitaxial structure; subsequently, a first superlattice buffer layer and a second superlattice buffer layer are grown to facilitate elemental transition and release mismatch stress. Therefore, the preparation of the strain buffer layer enables the acquisition of a high-quality and high-brightness deep red LED epitaxial structure with an emission wavelength of 630nm.

[0109] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0110] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.

Claims

1. An LED epitaxial structure, characterized in that, The device comprises a strain buffer layer, a cutoff layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially on a substrate. The strain buffer layer includes a low-temperature buffer layer, a high-temperature isolation layer, a first superlattice buffer layer, and a second superlattice buffer layer stacked sequentially. The low-temperature buffer layer is located between the substrate and the high-temperature isolation layer, and the second superlattice buffer layer is located between the first superlattice buffer layer and the cutoff layer. The low-temperature buffer layer is made of GaAs, the high-temperature isolation layer is made of GaAs, the first superlattice buffer layer includes a superlattice structure composed of a first GaAsP layer and a GaAs layer, and the second superlattice buffer layer includes a superlattice structure composed of a second GaAsP layer and a GaInP layer.

2. The LED epitaxial structure as described in claim 1, characterized in that, The material of the first GaAsP layer includes Ga 0.5 (As) x P 1-x ) 0.5 0.75 < x < 0.95; the material of the second GaAsP layer includes Ga 0.5 (As) y P 1-y ) 0.5 0.75 < y < 0.95; the material of the GaInP layer includes Ga 0.25 In 0.25 P 0.5 .

3. The LED epitaxial structure as described in claim 1, characterized in that, The As content in the first GaAsP layer is not greater than the As content in the second GaAsP layer.

4. The LED epitaxial structure as described in claim 1, characterized in that, The growth cycle number of the first superlattice buffer layer is 10~20, wherein the thickness of the first GaAsP layer in each cycle is 5nm~20nm; and the thickness of the GaAs layer in each cycle is 5nm~20nm.

5. The LED epitaxial structure as described in claim 1, characterized in that, The growth cycle number of the second superlattice buffer layer is 10~20, wherein the thickness of the second GaAsP layer in each cycle is 5nm~20nm; and the thickness of the GaInP layer in each cycle is 5nm~20nm.

6. The LED epitaxial structure as described in claim 1, characterized in that, The thickness of the low-temperature buffer layer is 100nm~300nm, and the low-temperature buffer layer is an unintentionally doped layer.

7. The LED epitaxial structure as described in claim 1, characterized in that, The high-temperature isolation layer has a thickness of 100nm~300nm, and the high-temperature isolation layer is an unintentionally doped layer.

8. The LED epitaxial structure as described in claim 1, characterized in that, The first type of semiconductor layer includes a first type of ohmic contact layer, a first type of window layer, a first type of confinement layer and a first barrier layer stacked sequentially, wherein the first type of ohmic contact layer is located between the cut-off layer and the first type of window layer, and the first barrier layer is located between the first type of confinement layer and the active layer.

9. The LED epitaxial structure as described in claim 8, characterized in that, The material of the first type of ohmic contact layer includes (Al) c Ga 1-c ) 0.25 In 0.25 P 0.5 , 0.3 < c < 0.9; the thickness of the first type of ohmic contact layer is 100nm~200nm.

10. The LED epitaxial structure as described in claim 1, characterized in that, The second type semiconductor layer includes a second barrier layer, a second type confinement layer, a second type current spreading layer and a second type ohmic contact layer stacked sequentially, and the second barrier layer is located between the active layer and the second type confinement layer.

11. The LED epitaxial structure as described in claim 1, characterized in that, The first type of semiconductor layer is an N-type semiconductor layer, and the second type of semiconductor layer is a P-type semiconductor layer.

12. The LED epitaxial structure as described in claim 1, characterized in that, The substrate includes a GaAs substrate.

13. A method for fabricating an LED epitaxial structure, characterized in that, Includes the following steps: Provide a substrate; A strain buffer layer is grown on the substrate. A cutoff layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer are sequentially grown on the strain buffer layer. The strain buffer layer includes a low-temperature buffer layer, a high-temperature isolation layer, a first superlattice buffer layer, and a second superlattice buffer layer stacked sequentially. The low-temperature buffer layer is located between the substrate and the high-temperature isolation layer, and the second superlattice buffer layer is located between the first superlattice buffer layer and the cutoff layer. The low-temperature buffer layer is made of GaAs, the high-temperature isolation layer is made of GaAs, the first superlattice buffer layer includes a superlattice structure composed of a first GaAsP layer and a GaAs layer, and the second superlattice buffer layer includes a superlattice structure composed of a second GaAsP layer and a GaInP layer.

14. The method for preparing the LED epitaxial structure as described in claim 13, characterized in that, The step of growing a strain buffer layer on the substrate includes: The low-temperature buffer layer and the high-temperature isolation layer are sequentially grown on the substrate; A high-temperature annealing process is performed on the structure with the aforementioned low-temperature buffer layer and high-temperature isolation layer. A first superlattice buffer layer and a second superlattice buffer layer are sequentially grown on the high-temperature isolation layer.

15. The method for preparing the LED epitaxial structure as described in claim 14, characterized in that, The high-temperature annealing process includes: cyclic annealing in an H2 atmosphere, ranging from a first temperature to a second temperature, and maintaining the temperature at the second temperature for a set time after each cycle.

16. The method for preparing the LED epitaxial structure as described in claim 15, characterized in that, The first temperature range is 400℃~500℃; the second temperature range is 700℃~800℃; and the set time is 5min~20min.

17. The method for preparing the LED epitaxial structure as described in claim 14, characterized in that, The growth temperature of the low-temperature buffer layer is 550℃~650℃; the growth temperature of the high-temperature isolation layer is 650℃~750℃; the growth temperature of the first superlattice buffer layer is 650℃~750℃; and the growth temperature of the second superlattice buffer layer is 650℃~750℃.

18. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The material of the first GaAsP layer includes Ga 0.5 (As) x P 1-x ) 0.5 0.75 < x < 0.95; the material of the second GaAsP layer includes Ga 0.5 (As) y P 1-y ) 0.5 0.75 < y < 0.95; the material of the GaInP layer includes Ga 0.25 In 0.25 P 0.5 .

19. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The As content in the first GaAsP layer is not greater than the As content in the second GaAsP layer.

20. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The growth cycle number of the first superlattice buffer layer is 10~20, wherein the thickness of the first GaAsP layer in each cycle is 5nm~20nm; and the thickness of the GaAs layer in each cycle is 5nm~20nm.

21. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The second superlattice buffer layer has 10 to 20 growth cycles, wherein the thickness of the second GaAsP layer in each cycle is 5 nm to 20 nm; and the thickness of the GaInP layer in each cycle is 5 nm to 20 nm.

22. The method for preparing the LED epitaxial structure as described in claim 14, characterized in that, The thickness of the low-temperature buffer layer is 100nm~300nm, and the low-temperature buffer layer is an unintentionally doped layer.

23. The method for preparing the LED epitaxial structure as described in claim 14, characterized in that, The high-temperature isolation layer has a thickness of 100nm~300nm, and the high-temperature isolation layer is an unintentionally doped layer.

24. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The first type of semiconductor layer includes a first type of ohmic contact layer, a first type of window layer, a first type of confinement layer and a first barrier layer stacked sequentially, wherein the first type of ohmic contact layer is located between the cut-off layer and the first type of window layer, and the first barrier layer is located between the first type of confinement layer and the active layer.

25. The method for preparing an LED epitaxial structure as described in claim 24, characterized in that, The material of the first type of ohmic contact layer includes (Al) c Ga 1-c ) 0.25 In 0.25 P 0.5 , 0.3 < c < 0.9; the thickness of the first type of ohmic contact layer is 100nm~200nm.

26. The method for preparing the LED epitaxial structure as described in claim 13, characterized in that, The second type semiconductor layer comprises, from bottom to top, a second barrier layer, a second type confinement layer, a second type current spreading layer, and a second type ohmic contact layer, wherein the second barrier layer is located between the active layer and the second type confinement layer.

27. The method for preparing an LED epitaxial structure as described in claim 13, characterized in that, The first type of semiconductor layer is an N-type semiconductor layer, and the second type of semiconductor layer is a P-type semiconductor layer.

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