High-precision three-phase alternating current signal variable-period average value sampling system and method

Abstract

The application relates to a high-precision three-phase alternating-current signal variable-period average value sampling system and method, which comprises the following steps: 3 / 2 transformation is carried out on three-phase sampling signals to obtain alpha-beta axis current and voltage; a clock CLK is set, and a variable-period time length T is calculated; three-phase sampling signals in the variable period are accumulated; then, low-speed current and voltage average values are calculated; finally, the current and voltage signals are compensated according to the low-speed current and voltage average values. According to the application, the current and voltage feedback values are calculated in an average mode according to the time between two pulses, and phase compensation is carried out on the current and voltage feedback according to the three-phase alternating-current sine wave mode, so as to adapt to the controller calculation requirement.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of current voltage sampling, and particularly relates to a high-precision three-phase alternating current signal variable period average value sampling system and method. BACKGROUND

[0002] In three-phase alternating current frequency conversion control, a digital control system needs to sample current and voltage values as system feedback, and the current and voltage values are not stable at the moment of opening of a power element triggered, or the current and voltage sampling is disturbed, so that the current and voltage sampling instantaneous values jump or have burrs. In order to achieve stable sampling, the instantaneous sampling values are usually processed by means of hardware filtering, software filtering, software average value calculation and the like to obtain relatively stable average values. The average value sampling basically adopts a fixed period average method, that is, a plurality of data in a certain period is averaged. However, for a power element trigger period which is not determined or changes, the fixed period sampling is not suitable, and the average value sampling time may cross the periods of a plurality of pulses, causing feedback waveform distortion. If the average value calculation sets a high fixed period sampling frequency, such as an average sampling time of 20 us to 30 us, the current and voltage waveforms can be truly reflected, but this causes poor filtering effect and increased load of the controller. SUMMARY

[0003] The application aims at overcoming the defects of the prior art, and provides a high-precision three-phase alternating current signal variable period average value sampling system and method, which can average calculate current and voltage feedback according to the time between two pulses, and perform phase compensation on the current and voltage feedback in a three-phase alternating current sinusoidal wave mode to adapt to the calculation requirement of the controller.

[0004] The application solves the technical problem by adopting the following technical scheme:

[0005] The high-precision three-phase alternating current signal variable period average value sampling system comprises a transformation module, a variable period length timing module, a variable period sampling signal accumulation module, a low-speed current and voltage average value calculation module and a low-speed current and voltage signal compensation module, the output end of the transformation module is connected with the input end of the variable period sampling signal accumulation module, the output end of the variable period sampling signal accumulation module and the output end of the variable period length timing module are connected with the input end of the low-speed current and voltage average value calculation module, and the output end of the low-speed current and voltage average value calculation module is connected with the input end of the low-speed current and voltage signal compensation module.

[0006] Further, the structure of the conversion module is that the current signal IR and -33.333% are input to a multiplication module Al, the current signal IS and -33.333% are input to a multiplication module A2, the current signal IT and -33.333% are input to a multiplication module A4, the output of the module Al and the output of the module A2 are input to an addition module A3, the output of the addition module A3 and the output of the module A4 are input to an addition module A5, the input of the addition module A5 and the current signal IR are input to an addition module A6, the addition module A6 outputs the α-axis current amount IAL, the current signal IS and 57.735% are input to a multiplication module A7, the current signal IT and 57.735% are input to a multiplication module A8, the output of the module A7 and the output of the module A8 are input to a subtraction module A9, the output of the subtraction module A9 outputs the β-axis current amount IBE, the voltage signal UR and -33.333% are input to a multiplication module A19, the voltage signal US and -33.333% are input to a multiplication module A20, the voltage signal UT and -33.333% are input to a multiplication module A22, the output of the module A19 and the output of the module A20 are input to an addition module A21, the output of the addition module A21 and the output of the module A22 are input to an addition module A23, the input of the addition module A23 and the voltage signal UR are input to an addition module A24, the addition module A24 outputs the α-axis voltage amount UAL, the voltage signal US and 57.735% are input to a multiplication module A25, the voltage signal UT and 57.735% are input to a multiplication module A26, the output of the module A25 and the output of the module A26 are input to a subtraction module A27, the output of the subtraction module A27 outputs the β-axis voltage amount UBE.

[0007] Moreover, the structure of the variable period length timing module is that the output of module A1 and the integral coefficient 1 of O2 format input to the addition module A2, the output of the addition module A2 and the integral setting value 100% input to the remainder function module A3, the output of the remainder function module A3 input to the module A1 and output the clock CLK, the trigger pulse signal PF input to the state register module A5, the input of the module A5 input to the non-module A6, the output of the non-module A6 and PF input to the AND module A4, the output of the AND module A4 output the single sampling period monostable synchronization pulse signal SYP, the output of the state register module A7, the output of the remainder function module A3 and the output of the AND module A4 input to the state selection module A8, the output of the module A8 input to the input of the module A7, the output of the module A8 and the output of the module A10 input to the subtraction module A11, the subtraction module A11 and the integral setting value 100% input to the remainder function module A12, the output of the remainder function module A12 and the integral coefficient 1 of O2 format and the output of the module A16 input to the state selection module A17, the output of the module A17 output the variable period length T, the output of the state register module A9, the output of the remainder function module A3 and the output of the AND module A4 input to the state selection module A10, the output of the module A10 input to the input of the module A9, the output of the remainder function module A12 input to the right shift 1 bit module A13, the output of the right shift 1 bit module A13 and the output of the module A10 input to the addition module A14, the addition module A14 and the integral setting value 100% input to the remainder function module A15, the output of the remainder function module A15, the output of the remainder function module A3 and the output of the module A16 input to the module A18, the output of the module A18 is the sampling time offset T1, PF and EN input to the logic judgment module A16.

[0008] Moreover, the structure of the variable period length timing module is that the structure of the variable period length timing module is that the output of module A1 and the integral coefficient 1 of O2 format input to the addition module A2, the output of the addition module A2 and the integral setting value 100% input to the remainder function module A3, the output of the remainder function module A3 input to the module A1 and output the clock CLK, the trigger pulse signal PF input to the state register module A5, the input of the module A5 input to the non-module A6, the output of the non-module A6 and PF input to the AND module A4, the output of the AND module A4 output the single sampling period monostable synchronization pulse signal SYP, the output of the state register module A7, the output of the remainder function module A3 and the output of the AND module A4 input to the state selection module A8, the output of the module A8 input to the input of the module A7, the output of the module A8 and the output of the module A10 input to the subtraction module A11, the subtraction module A11 and the integral setting value 100% input to the remainder function module A12, the output of the remainder function module A12 and the integral coefficient 1 of O2 format and the output of the module A16 input to the state selection module A17, the output of the module A17 output the variable period length T, the output of the state register module A9, the output of the remainder function module A3 and the output of the AND module A4 input to the state selection module A10, the output of the module A10 input to the input of the module A9, the output of the remainder function module A12 input to the right shift 1 bit module A13, the output of the right shift 1 bit module A13 and the output of the module A10 input to the addition module A14, the addition module A14 and the integral setting value 100% input to the remainder function module A15, the output of the remainder function module A15, the output of the remainder function module A3 and the output of the module A16 input to the module A18, the output of the module A18 is the sampling time offset T1, PF and EN input to the logic judgment module A16.

[0009] Moreover, the structure of the low-speed current voltage average value calculation module is that the variable period length T is input into module A1 in the low-speed current voltage average value calculation module, the output ends of UAF and module A1 are input into module A2, the output end of module A2 is input into module A3, module A3 outputs the α-axis voltage value UA, UBT and the output end of module A1 are input into module A4, the output end of module A4 is input into module A5, module A5 outputs the β-axis voltage value UB, IAF and the output end of module A1 are input into module A6, the output end of module A6 is input into module A7, module A7 outputs the α-axis current value IA, IBT and the output end of module A1 are input into module A8, the output end of module A8 is input into module A9, and module A9 outputs the β-axis current value IB.

[0010] Moreover, the structure of the low-speed current voltage signal compensation module is that the clock CLK and T1 are input into subtraction module A1 in the low-speed current voltage signal compensation module, the current voltage fundamental frequency FSS and the parameter K3 of the current output are input into module A3, subtraction module A1 and 100% are input into module A2, the output end of module A2 and the output end of module A3 are input into module A5, the output end of module A5 is input into left shift 2 module A6, the output end of left shift 2 module A6 is input into COS module A7 and SIN module A8, the output end of COS module A7 and the α-axis voltage value UA are input into module A9, the output end of SIN module A8 and the β-axis voltage value UB are input into module A10, the output end of module A9 and the output end of module A10 are connected to subtraction module A11, and subtraction module A11 outputs the compensated UAF; the output end of COS module A7 and the β-axis voltage value UB are input into module A12, the output end of SIN module A8 and the α-axis voltage value UA are input into module A13, the output end of module A13 and the output end of module A12 are connected to subtraction module A14, and subtraction module A14 outputs the compensated UBT; COS module A7 and the α-axis current value IA are input into module A15, the output end of SIN module A8 and the β-axis current value IB are input into module A16, the output end of module A15 and the output end of module A16 are connected to subtraction module A17, and subtraction module A17 outputs the compensated IAF; COS module A7 and the β-axis current value IB are input into module A18, the output end of SIN module A8 and the α-axis current value IA are input into module A19, the output end of module A18 and the output end of module A19 are connected to subtraction module A20, and subtraction module A20 outputs the compensated IBF.

[0011] A sampling method of a high-precision three-phase alternating current signal variable period average value sampling system, comprising the following steps:

[0012] Step 1, 3 / 2 transformation is performed on the three-phase sampling signal to obtain αβ-axis current and voltage quantities;

[0013] Step 2, set clock CLK, calculate variable period length T;

[0014] Step 3, according to the sampling period and αβ axis current and voltage, accumulate variable period three-phase sampling signal;

[0015] Step 4, according to the accumulated variable period three-phase sampling signal and variable period length T, calculate low-speed current and voltage average value;

[0016] Step 5, according to the low-speed current and voltage average value, compensate current and voltage signal.

[0017] Moreover, the specific implementation method of step 1 is that module A1 to module A5 in the transformation module are used to calculate three-phase current signal zero sequence component, module A6 calculates R-phase current signal minus zero sequence component, module A7 to module A9 calculate β axis component current signal, module A19 to module A23 calculate three-phase voltage signal zero sequence component, module A24 calculates R-phase voltage signal minus zero sequence component, module A25 to module A27 calculate β axis component voltage signal, and the common mode interference of current and voltage signal is eliminated at the same time of 3 / 2 transformation;

[0018] The specific implementation method of step 2 is that module A1 to module A3 in the variable period length timing module are synchronous clock, PF comes from trigger pulse module, is formed by 6-way trigger pulse first pulse phase, module A4 to module A6 are single sampling period rising edge monostable signal generation link, generate single sampling period monostable synchronization pulse signal SYP according to PF rising edge, which is used as start / stop signal of variable period accumulation actual value, module A7 to module A8 are used to remember clock value of current time of variable period, module A9 to module A10 are used to remember clock value of initial time of last variable period, module A11 to module A12 calculate clock value T corresponding to variable period length, module A13 to module A15 calculate clock value corresponding to intermediate time of previous variable period, clock value is equivalent sampling time T1 of last period, which is used for lag compensation when variable period average value is used later, module A16 makes timing length 1 when system has no trigger pulse or trigger pulse is less than 2, and finally calculated value is instantaneous value.

[0019] The specific implementation method of step 4 is that: the modules A2 to A4 in the low-speed current voltage average value calculation module are used for accumulated calculation of the variable period input signal, and the modules A5 to A6 are used for memorizing the accumulated value of the variable period; the modules A1 and A7 are used for bypassing the method before the trigger pulse release, and the functions of the modules A1 and A7 are as follows: since the PF signal is "0" before the trigger pulse release, the SYF signal is also "0"; if the method is not bypassed, the line ripple signal will be accumulated and calculated by the modules A2 to A4, the feedback signal is not normal at the initial time of system release, and the system is impacted and oscillated, and the modules A2 to A7 need to adopt double-word data type.

[0020] The specific implementation method of step 5 is that: the average value sampling time T1 in the low-speed current voltage signal compensation module is subtracted from the sampling clock CLK to obtain a deviation time, multiplied by the current voltage fundamental frequency FSS of the current output, to obtain a compensation phase angle, according to the characteristics of the sine and orthogonal correlation of the alpha axis and beta axis voltage current signals, the current voltage is compensated, and finally the current voltage value with the same period as the controller is obtained.

[0021] The advantages and positive effects of the present application are as follows:

[0022] 1. The present application obtains the alpha-beta axis current and voltage by 3 / 2 transformation of the three-phase sampling signal; the clock CLK is set, the variable period length T is calculated; the variable period three-phase sampling signal is accumulated; and then the low-speed current voltage average value is calculated.

[0023] Finally, the current voltage signal is compensated according to the low-speed current voltage average value. According to the time between two pulses, the current voltage feedback value is calculated and phase compensated according to the three-phase alternating current sine wave mode, so as to adapt to the calculation requirement of the controller.

[0024] 2. In the variable frequency control system, the current voltage signal sampling instantaneous value is limited by the sampling circuit, the basic sampling time is 2us, and the data precision of the sampling is 12 bits, if the hardware cost is greatly increased, the instantaneous signal also contains interference signals and non-periodic signals, and the harmonic signals generated by the conduction and commutation of the variable current device, which are not needed in the control, the present application adopts the variable period average and compensation method to obtain a relatively perfect current voltage sine signal. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a 3 / 2 transformation logic diagram of the three-phase sampling signal of the present application;

[0026] Figure 2 It is a variable period length timing logic diagram of the present application;

[0027] Figure 3Logic diagram for variable period sampling signal accumulation of the present application

[0028] Figure 4 Logic diagram for high speed variable period sampling accumulation of the present application

[0029] Figure 5 Logic diagram for low speed current voltage average value calculation of the present application

[0030] Figure 6 Logic diagram for low speed current voltage signal compensation of the present application

[0031] Figure 7 Three-phase instantaneous sampling current waveform diagram of the present application

[0032] Figure 8 Variable period average value waveform diagram of the present application

[0033] Figure 9 500us fixed period average waveform diagram of the present application

[0034] Figure 10 Variable period average value waveform diagram of the present application after phase compensation

[0035] Figure 11 Variable period average value waveform diagram of the present application after phase compensation

[0036] Figure 12 Sampling and accumulation calculation FPGA module diagram of the present application

[0037] Figure 13 Sampling and accumulation calculation FPGA system diagram of the present application

[0038] Figure 14 Average value calculation DSP module diagram of the present application DETAILED DESCRIPTION

[0039] The present application is further described in detail below with reference to the accompanying drawings.

[0040] The actual value signals of voltage and current of three-phase vector control need to be fed back in vector form, that is, on the basis of consistent three-phase signal calibration, the consistency (synchronization) of sampling time is ensured, otherwise the three-phase vector cannot be accurately obtained, and the vector directional control cannot be accurately realized. When variable period average value sampling is used, such as three-phase sampling average value according to respective variable period, the sampling time of three-phase feedback signals is not synchronized, and the three-phase vector signal cannot be obtained. Three phases are calculated according to the variable period of a certain phase, and the equivalent sampling time is memorized at the same time. According to the current equivalent fundamental frequency, the phase difference corresponding to the current time is converted, and then the phase difference is compensated according to the respective phase. The approximate three-phase synchronous feedback signal obtained by vector control is suitable, and the advantage is that the sampling time of three phases is synchronized. When three-phase calibration is ideal, the algebraic sum of three-phase average values is zero.

[0041] The high-precision three-phase alternating current signal variable period average value sampling system comprises a transformation module, a variable period length timing module, a variable period sampling signal accumulation module, a low-speed current voltage average value calculation module and a low-speed current voltage signal compensation module. The output end of the transformation module is connected to the input end of the variable period sampling signal accumulation module. The output end of the variable period sampling signal accumulation module and the output end of the variable period length timing module are connected to the input end of the low-speed current voltage average value calculation module. The output end of the low-speed current voltage average value calculation module is connected to the input end of the low-speed current voltage signal compensation module.

[0042] The sampling method of the high-precision three-phase alternating current signal variable period average value sampling system comprises the following steps:

[0043] Step 1, 3 / 2 transformation is performed on three-phase sampling signals to obtain αβ-axis current and voltage.

[0044] As Figure 1As shown, the structure of the conversion module is that the current signal IR and -33.333% are input to the multiplication module A1, the current signal IS and -33.333% are input to the multiplication module A2, the current signal IT and -33.333% are input to the multiplication module A4, the output end of the module A1 and the output end of the module A2 are input to the addition module A3, the output end of the addition module A3 and the output end of the module A4 are input to the addition module A5, the input end of the addition module A5 and the current signal IR are input to the addition module A6, the addition module A6 outputs the α-axis current quantity IAL, the current signal IS and 57.735% are input to the multiplication module A7, the current signal IT and 57.735% are input to the multiplication module A8, the output end of the module A7 and the output end of the module A8 are input to the subtraction module A9, the output end of the subtraction module A9 outputs the β-axis current quantity IBE, the voltage signal UR and -33.333% are input to the multiplication module A19, the voltage signal US and -33.333% are input to the module A20, the voltage signal UT and -33.333% are input to the multiplication module A22, the output end of the module A19 and the output end of the module A20 are input to the addition module A21, the output end of the addition module A21 and the output end of the module A22 are input to the addition module A23, the input end of the addition module A23 and the voltage signal UR are input to the addition module A24, the addition module A24 outputs the α-axis voltage quantity UAL, the voltage signal US and 57.735% are input to the multiplication module A25, the voltage signal UT and 57.735% are input to the multiplication module A26, the output end of the module A25 and the output end of the module A26 are input to the subtraction module A27, the output end of the subtraction module A27 outputs the β-axis voltage quantity UBE.

[0045] Among them, the modules A1 to A5 in the conversion module are used to calculate the zero sequence component of the three-phase current signal, the module A6 calculates the R-phase (i.e. the α-axis component) current signal subtracted by the zero sequence component, the modules A7 to A9 calculate the β-axis component current signal, the modules A19 to A23 calculate the zero sequence component of the three-phase voltage signal, the module A24 calculates the R-phase (i.e. the α-axis component) voltage signal subtracted by the zero sequence component, and the modules A25 and A27 calculate the β-axis component voltage signal. The common mode interference of the current and voltage signals is eliminated at the same time of 3 / 2 conversion.

[0046] Step 2, set the clock CLK, calculate the variable period T, and the time deviation T1 between the sampling time and the calculated time is used for subsequent phase compensation.

[0047] As Figure 2As shown, the output of module A1 in the variable period length timing module and the integral coefficient 1 in O2 format are input to the addition module A2, the output of the addition module A2 and the integral setting value 100% are input to the remainder function module A3, the output of the remainder function module A3 is input to the module A1 and outputs the clock CLK, the trigger pulse signal PF is input to the state register module A5, the input of the module A5 is input to the non-module A6, the output of the non-module A6 and PF are input to the AND module A4, the output of the AND module A4 outputs the single sampling period monostable synchronization pulse signal SYP, the output of the state register module A7, the output of the remainder function module A3 and the output of the AND module A4 are input to the state selection module A8, the output of the module A8 is input to the input of the module A7, the output of the module A8 and the output of the module A10 are input to the subtraction module A11, the subtraction module A11 and the integral setting value 100% are input to the remainder function module A12, the output of the remainder function module A12, the integral coefficient 1 in O2 format and the output of the module A16 are input to the state selection module A17, the output of the module A17 outputs the variable period length T, the output of the state register module A9, the output of the remainder function module A3 and the output of the AND module A4 are input to the state selection module A10, the output of the module A10 is input to the input of the module A9, the output of the remainder function module A12 is input to the right shift 1 bit module A13, the output of the right shift 1 bit module A13 and the output of the module A10 are input to the addition module A14, the addition module A14 and the integral setting value 100% are input to the remainder function module A15, the output of the remainder function module A15, the output of the remainder function module A3 and the output of the module A16 are input to the module A18, the output of the module A18 is the sampling time offset T1, PF and EN are input to the logic judgment module A16.

[0048] The modules A1 to A3 in the variable period length timing module are synchronous clocks, the integral coefficient of which is 1 (O2 format), and the sampling period of the module is T s , the time of integral to 100% is 16384T s , for example, T s = 2us, and the output CLK is calibrated to 100% corresponding to 32.768ms. PF comes from the trigger pulse module, which is composed of 6 trigger pulse phase or, the modules A4 to A6 are single sampling period rising edge monostable signal generation links, which generate the single sampling period monostable synchronization pulse signal SYP according to the rising edge of PF, which is used as the start / stop signal of the variable period accumulation actual value.

[0049] Module A7 to module A8 for memory variable period current time clock value (ie the end of the last variable period and the initial time of the variable period), module A9 to module A10 for memory initial time of the last variable period clock value, module A11 to module A12 calculate the length of the variable period corresponding to the clock value T, module A13 to module A15 calculate the clock value corresponding to the intermediate time of the previous variable period, the clock value is the equivalent sampling time T1 of the last period, for the lag compensation after the use of the variable period average, module A16 in the system does not trigger pulse or trigger pulse is less than 2 (can't calculate two pulse interval time), make the timing length is 1, the final calculated value is instantaneous value.

[0050] Step 3, according to the sampling period and αβ axis current and voltage, accumulate variable period three phase sampling signal.

[0051] As Figure 3 The signal digital quantity zero 0%, the actual sampling signal X and the allowable signal EN are input to the state selection module A1 in the variable period sampling signal accumulation module, the output end of the module A1 and the output end of the state selection module A3 are input to the addition module A4, the output end of the addition module A4 is input to the state register module A2, the output end of the module A2, 0% and the single sampling period monostable synchronization pulse signal SYP are input to the module A3, the output end of the module A2, the output end of the state register module A5 and the single sampling period monostable synchronization pulse signal SYP are input to the state selection module A6, the output end of the module A6, the signal X and the signal EN are input to the state selection module A7, the module A7 output signal Y, the output end of the module A6 is input to the module A5.

[0052] The module A2 to module A4 in the variable period sampling signal accumulation module are used for the accumulation calculation of the variable period input signal, the module A5 to module A6 are used for the memory of the accumulation value of the variable period; the module A1 and the module A7 are used for bypassing the method before the trigger pulse release, the function of the module A1 and the module A7 is that: before the trigger pulse release, the PF signal is "0", the SYF signal is also "0"; if the method is not bypassed, the line ripple signal will be accumulated and calculated by the module A2 to module A4, the initial time feedback signal of the system is not normal, which causes impact oscillation to the system, the module A2 to module A7 need to use double word data type.

[0053] As Figure 4 The sampling accumulation part is shown in the total diagram, which contains Figure 1 Corresponding to B1 block 1, Figure 2 Corresponding to B2 block 1, Figure 3 Corresponding to B3 block 4. The execution period is 2us high speed signal sampling period, and the output signal enters the frequency converter.

[0054] Step 4, according to the accumulated variable period three-phase sampling signal and variable period length T, the low-speed current voltage average value is calculated, wherein the control period is 250us-1000us.

[0055] As shown in Figure 5 , the variable period length T is input into the module A1 in the low-speed current voltage average value calculation module, the output end of UAF and module A1 is input into module A2, the output end of module A2 is input into module A3, module A3 outputs the α-axis voltage value UA, UBT and the output end of module A1 is input into module A4, the output end of module A4 is input into module A5, module A5 outputs the β-axis voltage value UB, IAF and the output end of module A1 is input into module A6, the output end of module A6 is input into module A7, module A7 outputs the α-axis current value IA, IBT and the output end of module A1 is input into module A8, the output end of module A8 is input into module A9, module A9 outputs the β-axis current value IB.

[0056] Step 5, according to the low-speed current voltage average value, the current voltage signal is compensated.

[0057] As shown in Figure 6 , the clock CLK and T1 are input into the subtraction module A1 in the low-speed current voltage signal compensation module, the current output current voltage fundamental frequency FSS and the parameter K3 are input into module A3, the subtraction module A1 and 100% are input into module A2, the output end of module A2 and the output end of module A3 are input into module A5, the output end of module A5 is input into the left shift 2 for module A6, the output end of the left shift 2 for module A6 is input into the COS module A7 and the SIN module A8, the output end of the COS module A7 and the α-axis voltage value UA are input into module A9, the output end of the SIN module A8 and the β-axis voltage value UB are input into module A10, the output end of module A9 and the output end of module A10 are connected to the subtraction module A11, the subtraction module A11 outputs the compensated UAF; the output end of the COS module A7 and the β-axis voltage value UB are input into module A12, the output end of the SIN module A8 and the α-axis voltage value UA are input into module A13, the output end of module A13 and the output end of module A12 are connected to the subtraction module A14, the subtraction module A14 outputs the compensated UBT; the output end of the COS module A7 and the α-axis current value IA are input into module A15, the output end of the SIN module A8 and the β-axis current value IB are input into module A16, the output end of module A15 and the output end of module A16 are connected to the subtraction module A17, the subtraction module A17 outputs the compensated IAF; the output end of the COS module A7 and the β-axis current value IB are input into module A18, the output end of the SIN module A8 and the α-axis current value IA are input into module A19, the output end of module A18 and the output end of module A19 are connected to the subtraction module A20, the subtraction module A20 outputs the compensated IBF.

[0058] The average sampling time T1 is subtracted from the sampling clock CLK to obtain a deviation time, multiplied by the current voltage fundamental frequency FSS of the current output, to obtain a compensation phase angle, and the current voltage is compensated by rotation according to the characteristics of the sine and orthogonal correlation of the alpha and beta axis voltage and current signals, and finally the current voltage value with the same period as the controller is obtained.

[0059] In a variable frequency control system, the sampling instantaneous value of the current and voltage signals is limited by the sampling circuit, the basic sampling time is 2us, and the sampling data precision is 12 bits, and if it needs to be improved, the hardware cost will be greatly increased. Moreover, the instantaneous signal also contains interference signals and non-periodic signals, and harmonic signals generated by the conduction and commutation of the converter, which are not needed in the control. The present application adopts a variable period average and compensation method to obtain a relatively perfect current and voltage sine signal.

[0060] Figure 7 The three-phase current waveform obtained by real-time sampling of the three-phase alternating variable frequency output has a frequency of 10Hz, and the current sampling waveform can be seen to be curved and distorted, and contains many harmonic components.

[0061] Figure 8 The current waveform after variable period sampling and averaging, in which the three-phase current waveform is converted to alpha and beta axis currents, can be seen to be approximately sinusoidal without distortion.

[0062] Figure 9 The current waveform obtained by the fixed period sampling method as a comparison, with a sampling period of 500us, in which the three-phase current waveform is converted to alpha and beta axis currents, can be seen to have distortion components compared with the sinusoidal waveform. The effect is not good.

[0063] Figure 10 Further phase shift compensation of the calculated values obtained by variable period sampling and averaging according to the three-phase sinusoidal law, the two curves with platform steps are the alpha and beta axis currents before compensation, and the smooth sinusoidal waveform is the alpha and beta axis currents after compensation.

[0064] Figure 11 The alpha and beta axis currents obtained after the method.

[0065] As shown in Figure 12 and Figure 13 , the present application adopts FPGA to realize high-speed sampling accumulation calculation part, the FPGA receives three-phase current and voltage signals (which have been converted to 16-bit digital quantities), selects the R-phase pulse in the three-phase phase control unit as the variable period time reference PF signal, performs common mode elimination operation, 3 / 2 transformation operation, timing operation and accumulation operation. Figure 13 is Figure 4 The system diagram of the high-speed variable period sampling accumulation logic realized by FPGA programming.

[0066] As Figure 14 shown, the implementation process uses the application block VTM_I written by the inventor himself TGCS software platform to realize the subsequent average value calculation and compensation algorithm, adopts a DSP programming processor, and sets the processing period to 400us.

[0067] It should be emphasized that the embodiments described in the present application are illustrative rather than restrictive, and therefore the present application includes and is not limited to the embodiments described in the specific embodiments, and any other embodiments derived by those skilled in the art according to the technical solutions of the present application also belong to the scope of protection of the present application.

Claims

1. A high-precision three-phase AC signal variable-period average sampling system, characterized in that: It includes a conversion module, a variable period length timing module, a variable period sampling signal accumulation module, a low-speed current and voltage average value calculation module, and a low-speed current and voltage signal compensation module. The output terminal of the conversion module is connected to the input terminal of the variable period sampling signal accumulation module. The output terminals of the variable period sampling signal accumulation module and the variable period length timing module are connected to the input terminal of the low-speed current and voltage average value calculation module. The output terminal of the low-speed current and voltage average value calculation module is connected to the input terminal of the low-speed current and voltage signal compensation module. The structure of the conversion module is as follows: Current signal IR and -33.333% are input to multiplication module A1; current signal IS and -33.333% are input to multiplication module A2; current signal IT and -33.333% are input to multiplication module A4; the outputs of modules A1 and A2 are input to addition module A3; the outputs of addition module A3 and A4 are input to addition module A5; the input of addition module A5 and current signal IR are input to addition module A6; addition module A6 outputs the α-axis current IAL; current signal IS and 57.735% are input to multiplication module A7; current signal IT and 57.735% are input to multiplication module A8; the outputs of modules A7 and A8 are input to subtraction module A9; subtraction module A9 outputs the β-axis current IBE. Voltage signals UR and -33.333% are input to multiplication module A19, voltage signals US and -33.333% are input to multiplication module A20, voltage signals UT and -33.333% are input to multiplication module A22, the outputs of modules A19 and A20 are input to addition module A21, the outputs of addition module A21 and A22 are input to addition module A23, the input of addition module A23 and voltage signal UR are input to addition module A24, addition module A24 outputs α-axis voltage UAL, voltage signals US and 57.735% are input to multiplication module A25, voltage signals UT and 57.735% are input to multiplication module A26, the outputs of modules A25 and A26 are input to subtraction module A27, subtraction module A27 outputs β-axis voltage UBE; The structure of the variable period length timing module is as follows: the output of module A1 and the integral coefficient 1 in O2 format are input to the adder module A2. The output of adder module A2 and the integral setpoint 100% are input to the remainder function module A3. The output of remainder function module A3 is input to module A1 and outputs clock CLK. The trigger pulse signal PF is input to the status register module A5. The input of module A5 is input to the non-module A6. The output of non-module A6 and PF are input to the AND module A4. The AND module A4 outputs a single-sampling-period monostable synchronous pulse signal SYP. The output of status register module A7, the output of remainder function module A3, and the output of AND module A4 are input to the status selection module A8. The output of module A8 is input to the input of module A7. The outputs of module A8 and module A10 are input to the subtraction module A11. The subtraction module A11 and the integral setpoint 100% are input to the remainder function module A11. The output of function module A12, the output of the modulo function module A12, the integral coefficient 1 in O2 format, and the output of module A16 are input to the state selection module A17. The output of module A17 outputs the variable period duration T. The output of state register module A9, the output of modulo function module A3, and the output of module A4 are input to state register module A10. The output of module A10 is input to the input of module A9. The output of modulo function module A12 is input to right shift 1 bit module A13. The output of right shift 1 bit module A13 and the output of module A10 are input to addition module A14. The addition module A14 and the integral setting value 100% are input to modulo function module A15. The output of modulo function module A15, modulo function module A3, and module A16 are input to module A18. The output of module A18 is the sampling time offset T1. PF and EN are input to logic judgment module A16.

2. The high-precision three-phase AC signal variable-period average value sampling system according to claim 1, characterized in that: The structure of the variable period sampling signal accumulation module is as follows: the digital signal value 0%, the actual sampled signal X, and the enable signal EN are input to the state selection module A1 in the variable period sampling signal accumulation module. The output of module A1 and the output of state selection module A3 are input to the addition module A4. The output of addition module A4 is input to the state register module A2. The output of module A2, 0%, and the single-sampling-period monostable synchronous pulse signal SYP are input to module A3. The output of module A2, the output of state register module A5, and the single-sampling-period monostable synchronous pulse signal SYP are input to the state selection module A6. The output of module A6, signal X, and signal EN are input to the state selection module A7. Module A7 outputs signal Y, and the output of module A6 is input to module A5.

3. The high-precision three-phase AC signal variable-period average value sampling system according to claim 1, characterized in that: The structure of the low-speed current and voltage average value calculation module is as follows: the variable period duration T is input to module A1 in the low-speed current and voltage average value calculation module; UAF and the output terminal of module A1 are input to module A2; the output terminal of module A2 is input to module A3; module A3 outputs the α-axis voltage value UA; UBT and the output terminal of module A1 are input to module A4; the output terminal of module A4 is input to module A5; module A5 outputs the β-axis voltage value UB; IAF and the output terminal of module A1 are input to module A6; the output terminal of module A6 is input to module A7; module A7 outputs the α-axis current value IA; IBT and the output terminal of module A1 are input to module A8; the output terminal of module A8 is input to module A9; module A9 outputs the β-axis current value IB.

4. The high-precision three-phase AC signal variable-period average value sampling system according to claim 1, characterized in that: The structure of the low-speed current and voltage signal compensation module is as follows: clock CLK and T1 are input to subtraction module A1 in the low-speed current and voltage signal compensation module; the current output fundamental frequency FSS and parameter K3 are input to module A3; subtraction module A1 and 100% are input to module A2; the outputs of module A2 and module A3 are input to module A5; the output of module A5 is input to module A6 (left-shifted by 2); the output of module A6 (left-shifted by 2) is input to COS module A7 and SIN module A8; COS module A7 and α-axis voltage value UA are input to module A9; the output of SIN module A8 and β-axis voltage value UB are input to module A10; the outputs of module A9 and module A10 are connected to subtraction module A11; subtraction module A11 outputs the compensated UAF; the output of COS module A7 and β-axis... The voltage value UB is input to module A12. The output of SIN module A8 and the α-axis voltage value UA are input to module A13. The outputs of module A13 and module A12 are connected to subtraction module A14, which outputs the compensated UBT. The COS module A7 and the α-axis current value IA are input to module A15. The output of SIN module A8 and the β-axis current value IB are input to module A16. The outputs of module A15 and module A16 are connected to subtraction module A17, which outputs the compensated IAF. The COS module A7 and the β-axis current value IB are input to module A18. The output of SIN module A8 and the α-axis current value IA are input to module A19. The outputs of module A18 and module A19 are connected to subtraction module A20, which outputs the compensated IBF.

5. A sampling method for a high-precision three-phase AC signal variable-period average value sampling system as described in any one of claims 1 to 4, characterized in that: Includes the following steps: Step 1: Perform a 3 / 2 transformation on the three-phase sampled signals to obtain the αβ axis current and voltage quantities; Step 2: Set the clock CLK and calculate the variable period duration T; Step 3: Accumulate the variable-period three-phase sampled signals according to the sampling period and the αβ axis current and voltage. Step 4: Calculate the average value of low-speed current and voltage based on the accumulated variable-period three-phase sampling signal and the variable-period duration T; Step 5: Compensate the current and voltage signals based on the average low-speed current and voltage values.

6. The sampling method of the high-precision three-phase AC signal variable-period average value sampling system according to claim 5, characterized in that: The specific implementation method of step 1 is as follows: Modules A1 to A5 in the transformation module are used to calculate the zero-sequence component of the three-phase current signal, module A6 calculates the R-phase current signal after subtracting the zero-sequence component, modules A7 to A9 calculate the β-axis component current signal, modules A19 to A23 calculate the zero-sequence component of the three-phase voltage signal, module A24 calculates the R-phase voltage signal after subtracting the zero-sequence component, and module A25 and A27 calculate the β-axis component voltage signal. The common-mode interference of the current and voltage signals is eliminated during the 3 / 2 transformation. Step 2 is implemented as follows: Modules A1 to A3 in the variable period length timing module are synchronous clocks. PF comes from the trigger pulse module and is generated by the phase OR of the first pulses of 6 trigger pulses. Modules A4 to A6 are single-sampling period rising edge monostable signal generation links. Based on the rising edge of PF, a single-sampling period monostable synchronous pulse signal SYP is generated, which is used as the start / end signal for the variable period accumulation acquisition of the actual value. Modules A7 to A8 are used to memorize the clock value of the current moment of the variable period. Modules A9 to A10 are used to memorize the clock value of the initial moment of the previous variable period. Modules A11 to A12 calculate the clock value T corresponding to the length of the variable period. Modules A13 to A15 calculate the clock value corresponding to the middle moment of the previous variable period. The clock value is the equivalent sampling moment T1 of the previous period, which is used for lag compensation when the variable period average value is used later. Module A16 sets the timing length to 1 when there is no trigger pulse or less than 2 trigger pulses in the system. The final calculated value is the instantaneous value. The specific implementation method of step 4 is as follows: Modules A2 to A4 in the low-speed current and voltage average value calculation module are used for the accumulation calculation of the variable period input signal, and modules A5 to A6 are used to memorize the accumulated value of the variable period; modules A1 and A7 are used to bypass this method before the trigger pulse is released. The function of modules A1 and A7 is as follows: before the trigger pulse is released, the PF signal is "0" and the SYF signal is also "0"; if this method is not bypassed, the line ripple signal will be accumulated by modules A2 to A4, and the feedback signal at the initial moment of system release will be abnormal, causing impact oscillation to the system. In this step, modules A2 to A7 need to use double-word data type. The specific implementation method of step 5 is as follows: the average sampling time T1 in the low-speed current and voltage signal compensation module is subtracted from the sampling clock CLK to obtain the deviation time, which is multiplied by the fundamental frequency FSS of the current and voltage output to obtain the compensation phase angle. Based on the sinusoidal and orthogonal correlation characteristics of the voltage and current signals of the α-axis and β-axis, the current and voltage are subjected to rotational compensation to finally obtain the current and voltage values ​​with the same period as the controller.

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