A hybrid multi-level inverter fault-tolerant control method and system

Abstract

The application provides a hybrid multi-level inverter fault-tolerant control method and system, which utilizes amplitude-shifted carrier modulation to modulate N-1 carriers in the same phase and stacked, so that the T-type inverter part and the H-bridge unit share one carrier for modulation, and N is the number of voltage levels; when an open-circuit fault occurs in a switch tube of an H-bridge unit of a phase, the fault-tolerant control of the modified three-phase modulation wave reference voltage is carried out, and the redundant state of the switch is utilized to make the current bypass the faulty switch tube, so that the hybrid topology N-level inverter in normal operation is converted into an N-1-level inverter in fault operation. In the application, the method of limiting the modification degree is adopted in the fault, the change of the modulation wave is affected, the charging and discharging time of the flying capacitor voltage is changed, and then the flying capacitor voltage is balanced, so that the fluctuation is stable within the range without causing three-phase current distortion.

Description

Technical Field

[0001] This invention belongs to the field of inverter control technology, and relates to a fault-tolerant control method and system for a hybrid multilevel inverter. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In photovoltaic power generation, multilevel inverters are increasingly used due to their advantages such as low switching stress and good output waveform. However, the increased number of switching devices makes the system more complex and the control technology more difficult, leading to fault tolerance issues. Furthermore, when switching devices fail, the consequences can range from affecting the output waveform and voltage quality to causing power supply system failures, resulting in irreversible damage to life and property. Therefore, research on fault-tolerant control of multilevel inverters is crucial.

[0004] The hybrid topology seven-level inverter consists of a T-type three-level inverter and three H-bridge units connected in series. Therefore, this topology combines the advantages of both: the T-type inverter, as the main topology, offers low transmission loss and high transmission efficiency, while the H-bridge units offer advantages such as modularity and low cost. Furthermore, this topology has a peak-to-peak value of 6E, which is 1.5 times that of the T-type three-level inverter. This is equivalent to increasing the DC input voltage, thereby improving DC voltage utilization. In addition, compared to the T-type three-level inverter, this topology has more output voltage stages, resulting in a smoother output voltage waveform. Moreover, compared to a cascaded H-bridge seven-level inverter, this topology uses fewer switching devices, has a simpler modulation method, and a lower probability of switching device failure.

[0005] However, this hybrid topology seven-level inverter is still prone to switching device failures when performing output voltage modulation, and the failure probability of the switching devices in the H-bridge unit is also higher because the switching devices in this part are used more frequently.

[0006] This topology has seven output voltage levels, corresponding to twelve switching modes. Only the ±3E output voltage corresponds to one switching mode, while the other output voltage states correspond to two switching modes. Therefore, the redundancy of the output voltage switching modes in this topology can achieve fault-tolerant control for minor faults. However, when a switching device failure prevents the inverter from outputting the ±3E voltage, the redundant switching mode cannot be used for voltage output. Summary of the Invention

[0007] To address the aforementioned problems, this invention proposes a fault-tolerant control method and system for a hybrid multilevel inverter. This invention uses modulation to enable the T-type three-level inverter and the H-bridge unit to share the same carrier wave for modulation. Simultaneously, it employs a method of modifying the reference voltage in the modulation wave, allowing the topology to maintain the balance of the three-phase output current even under fault conditions. During a fault, a method of limiting the modulation index is used, affecting the change in the modulation wave and altering the charging and discharging time of the flying capacitor voltage, thereby balancing the flying capacitor voltage and ensuring stable fluctuations within a range that does not cause distortion of the three-phase current.

[0008] According to some embodiments, the present invention adopts the following technical solution:

[0009] A fault-tolerant control method for a hybrid multilevel inverter includes the following steps:

[0010] Using amplitude-shift carrier modulation, N-1 in-phase superimposed carriers are modulated so that the T-type inverter section and the H-bridge unit share the same carrier for modulation, where N is the number of output voltage levels;

[0011] When an open-circuit fault occurs in the switching transistor of a certain phase H-bridge unit, fault-tolerant control is implemented. The redundant state of the switch is used to allow the current to bypass the faulty switching transistor, so that the hybrid topology N-level inverter under normal operation is transformed into an N-1 level inverter under fault operation.

[0012] As an alternative implementation method, the specific process of fault-tolerant control includes modifying the reference voltage of the three-phase modulation wave so that when a switch of a certain phase H-bridge unit fails, the modulation wave of the faulty phase is modified during the output voltage distortion stage so that the output voltage of that phase returns to normal, that is, the output voltage is at the N-1 level.

[0013] Furthermore, the difference between the reference voltage of the modulated wave after the fault phase is modified and the reference voltage of the modulated wave before the modification is added to the other two normal phases during the output voltage distortion stage, so that the line voltage remains unchanged before and after the fault when calculating the line voltage, thus maintaining the balance of the three-phase current.

[0014] As an alternative implementation, when a switch of a phase H-bridge unit fails, the inverter can maintain normal operation by utilizing the remaining output voltage state and the redundant switching state of the hybrid topology multilevel inverter.

[0015] As an alternative implementation, when the current bypasses the faulty switch by utilizing the redundant state of the switch, the charging and discharging time of the flying capacitor is controlled by limiting the modulation. By controlling the on-time of the output voltage state that affects the voltage change of the flying capacitor, the voltage of the flying capacitor is made to reach equilibrium as soon as possible.

[0016] Furthermore, controlling the flying capacitor voltage has a higher priority than controlling the midpoint capacitor voltage.

[0017] Furthermore, if the detected flying capacitor voltage is greater than the set threshold, flying capacitor voltage control will be used preferentially; if the detected flying capacitor voltage is less than the set threshold, midpoint voltage control will be used preferentially.

[0018] As an alternative implementation, the direction of current flow in the flying capacitor is controlled by changing the switching state of the H-bridge, thereby controlling the charging and discharging state and time of the flying capacitor. When the inverter is working normally, the voltage value of the flying capacitor is compared with the rated value E to determine whether charging and discharging is required. By utilizing the redundancy of the inverter, the charging and discharging of the flying capacitor can be controlled when the same voltage level is output.

[0019] A hybrid multilevel inverter fault-tolerant control system includes:

[0020] The carrier modulation module is configured to use amplitude-shift carrier modulation to modulate N-1 in-phase stacked carriers, so that the T-type inverter section and the H-bridge unit share the same carrier for modulation, where N is the number of output voltage levels;

[0021] The fault-tolerant control module is configured to perform fault-tolerant control when an open-circuit fault occurs in the switching transistor of a certain phase H-bridge unit. It utilizes the redundant state of the switch to allow the current to bypass the faulty switching transistor, thereby transforming the hybrid topology N-level inverter in normal operation into an N-1 level inverter in fault operation.

[0022] A hybrid topology multilevel inverter includes three-phase bridge arms connected in parallel. Each bridge arm includes one bridge arm of a T-type three-level inverter and an H-bridge unit. One bridge arm of the T-type three-level inverter consists of two reverse-connected series switches connected to a half-bridge unit, and the two ends of the half-bridge unit are connected to the two ends of two series capacitors in a DC link.

[0023] The H-bridge unit consists of two two-level half-bridge units formed by four switching transistors connected in series end to end, and the upper and lower midpoints of the H-bridge unit circuit are connected to the two ends of the flying capacitor; the midpoints of the two half-bridge units are respectively connected to the T-type three-level inverter in the front stage and the power grid in the back stage.

[0024] Use the methods described above for fault-tolerant control or to include the control systems described above.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] Compared to a T-type three-level inverter, this invention is equivalent to increasing the DC input voltage, thereby improving the utilization rate of the DC voltage, and the output voltage waveform is a more accurate sine wave.

[0027] This invention utilizes the amplitude-shifting carrier modulation method in SPWM, and also adopts the method of sharing the same carrier modulation for both the front and rear parts, which simplifies the analysis process.

[0028] This invention reduces the output voltage of the faulty phase from a seven-level to a six-level after a faulty switch in the H-bridge unit, without voltage distortion, and still maintains the normal operation of the inverter.

[0029] This invention uses a method of changing the modulation wave to balance the line voltage, making the method applicable in the photovoltaic industry to prevent damage to the system caused by three-phase current imbalance.

[0030] This invention achieves control over the voltage across the capacitor after a fault in a certain IGBT of a certain phase by limiting and modifying the modulation scheme, thereby stabilizing the waveform of the output current. Attached Figure Description

[0031] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0032] Figure 1 This is a schematic diagram of a hybrid topology seven-level inverter according to an embodiment of the present invention.

[0033] Figure 2 This is a simulation diagram of the relationship between the modulation wave voltage and the carrier voltage and the modulation wave current when a hybrid topology seven-level inverter is operating normally using the amplitude shift carrier modulation method in SPWM according to an embodiment of the present invention.

[0034] Figure 3(a) is a simulation diagram of the output voltage of phase AB of the inverter when it is operating normally according to an embodiment of the present invention.

[0035] Figure 3(b) shows the A-phase switch S according to an embodiment of the present invention. a6 Simulation diagram of the output voltage of phase AB after an open circuit fault.

[0036] Figure 3(c) shows the A-phase switch S according to an embodiment of the present invention. a6 Simulation diagram of the output voltage of phase AB after an open-circuit fault and fault-tolerant control.

[0037] Figure 4(a) is a simulation diagram of the A-phase output voltage of the inverter under normal operation according to an embodiment of the present invention.

[0038] Figure 4(b) shows the A-phase switch S according to an embodiment of the present invention. a6 Simulation diagram of phase A output voltage after open circuit fault.

[0039] Figure 4(c) shows the A-phase switch S according to an embodiment of the present invention.a6 Simulation diagram of phase A output voltage after fault-tolerant control following an open-circuit fault.

[0040] Figure 5(a) is a simulation diagram of the three-phase output current of an inverter under normal operation according to an embodiment of the present invention.

[0041] Figure 5(b) shows the A-phase switch S according to an embodiment of the present invention. a6 Simulation diagram of three-phase output current after open circuit fault.

[0042] Figure 5(c) is a simulation diagram of the three-phase output current after fault-tolerant control according to an embodiment of the present invention.

[0043] Figure 5(d) is a fast Fourier analysis simulation diagram of the three-phase output current after fault-tolerant control according to an embodiment of the present invention.

[0044] Figure 6(a) is a simulation diagram of the three-phase reference voltage when the inverter is operating normally according to an embodiment of the present invention.

[0045] Figure 6(b) is a simulation diagram of the three-phase reference voltage after the modulation wave is modified by fault-tolerant control according to an embodiment of the present invention.

[0046] Figure 7(a) is a simulation diagram of the flying capacitor voltage in a three-phase H-bridge unit when the inverter is operating normally according to an embodiment of the present invention.

[0047] Figure 7(b) shows phase A of an embodiment of the present invention. a6 Simulation diagram of the flying capacitor voltage in a three-phase H-bridge unit after an open-circuit fault in the switching transistor.

[0048] Figure 7(c) is a simulation diagram of the flying capacitor voltage in a three-phase H-bridge unit after fault-tolerant control according to an embodiment of the present invention.

[0049] Figure 8 The diagram illustrates a specific fault-tolerant control method according to one embodiment of the present invention. Detailed Implementation

[0050] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0051] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0052] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0053] This invention provides a hybrid topology, including parallel three-phase bridge arms. Each bridge arm includes an H-bridge unit and a bridge arm of a T-type inverter. The T-type inverter's bridge arm consists of two units: the first unit comprises two IGBT switches connected in reverse series, and the second unit comprises two IGBT switches connected in forward series, forming a two-level half-bridge unit. A 2E capacitor is connected to each end of the second unit, and these two capacitors are connected in series. One end of the first unit is then connected to the connection point of the two capacitors, and the other end is connected to the midpoint of the second unit, thus forming one bridge arm of the T-type three-level inverter. The H-bridge unit comprises two parallel two-level half-bridge units formed by four IGBT switches connected in series, and a capacitor with a capacitance of E is connected in parallel with the two half-bridge units to form the H-bridge unit. This topology is formed by connecting the connection point of the first and second units in one bridge arm of the T-type three-level inverter to the midpoint of one of the two half-bridge units in the H-bridge unit. Each unit is grounded via a star connection through capacitors.

[0054] In some embodiments, different switching transistors can withstand different maximum voltages, so different voltage levels or types of power devices can be used for switching transistors in different locations to save hardware costs.

[0055] The control method for the aforementioned hybrid topology seven-level inverter utilizes amplitude-shift carrier modulation in SPWM. Since the inverter's output voltage is seven levels, six in-phase stacked carriers are required for modulation. Furthermore, the T-type inverter and the H-bridge unit share the same carrier for modulation, further simplifying the modulation process.

[0056] In some embodiments, an open-circuit fault is caused in a certain phase H-bridge unit. The faulty phase is analyzed, and the output voltage of the H-bridge unit is reduced from three levels to two levels. The redundant switching state of the faulty phase is used to reduce the output voltage of the faulty phase from seven levels to six levels to maintain the normal operation of the inverter.

[0057] In some embodiments, the fault-tolerance method involves modifying the reference voltage of the modulation wave to balance the line voltage and thus the three-phase current. The modified modulation wave of the faulty phase is then subtracted from the original modulation wave (if it is S...). a6In the event of a fault, the modified modulation wave remains constant at +2E during the phase when the H-bridge unit cannot output +E normally. At the same time, this difference is added to the modulation wave voltage of the other two phases during the phase when the H-bridge unit cannot output voltage normally, so that the line voltage can still maintain the original difference when performing differential calculations, thereby balancing the line voltage.

[0058] In some embodiments, after a fault, the lack of a switching mode due to the H-bridge unit failure leads to an imbalance in the charging and discharging of the flying capacitor in the H-bridge unit, causing a deviation in the flying capacitor voltage and thus affecting the three-phase output current waveform. A method of limiting and modifying the inverter modulation is adopted, which changes the charging and discharging time of the flying capacitor under the same carrier wave with different modulation waves, thereby balancing the flying capacitor voltage more quickly.

[0059] As a typical embodiment of the present invention, a hybrid seven-level inverter topology is provided. For example... Figure 1 As shown, this hybrid topology consists of one arm of a T-type three-level inverter and an H-bridge unit connected in series. x1 —S x8 For 8 fully controlled switching devices, V cd1 and V cd2 These are the upper and lower capacitor voltages of the DC link, U fx Let x be the voltage across the flying capacitor (x = a, b, c). The voltage across Cd1 and Cd2 is 2E, the DC link voltage is constant at 4E, and the voltage across the flying capacitor is E. x1 and S x2 Withstands the voltage of the entire DC power supply (4E), S x3 and S x4 The voltage it withstands is half of the DC power supply (2E), S x5 —S x8 It withstands the voltage (E) across the flying capacitor. Cx It is the current flowing into the leap capacitor Cx, i mx This is the current flowing out from the midpoint of the DC link. For a T-type three-level inverter, S x1 With S x2 S x3 With S x4 The drive signals are complementary. By controlling the on / off state of the four switching devices, the T-type topology can generate three voltage levels: -2E, 0, and 2E. Therefore, the T-type inverter is a three-level topology. For the H-bridge unit, the upper and lower switching devices on each side of the bridge arm are complementary in conduction, i.e., S... x5 With S x6 S x7 With S x8 The drive signals are complementary. By controlling the on / off state of the four switching devices, the H-bridge unit can generate three voltage levels: -E, 0, and E. Therefore, the H-bridge unit is also a three-level topology. (The last sentence appears to be incomplete and possibly refers to a different topic.) x1 and Sx2 The midpoint of S x5 and S x6 By connecting the midpoints, the resulting hybrid topology can output seven levels from -3E to +3E, thus constituting a seven-level inverter. The seven levels from -3E to 3E correspond to 12 different conduction paths. When the output voltage is ±3E, there is only one conduction path; when the output voltage is -2E to +2E, each output voltage corresponds to two conduction paths. Table I shows the switching states and output voltage states corresponding to different conduction paths.

[0060] Table I Output Voltage Status and Switching Status

[0061]

[0062]

[0063] According to the present invention, a control method using the above-described topology is also provided.

[0064] According to a specific embodiment of the present invention, Figure 2 This paper presents a simulation diagram showing the relationship between the modulation wave voltage and the carrier voltage, as well as the modulation wave current, when using amplitude-shift carrier modulation (SPWM) in a hybrid topology seven-level inverter during normal operation. The output voltage is generated by comparing the modulation wave and the carrier wave; for example, in region 3, when the modulation wave is greater than +2E, the inverter's output voltage is +3E. When the A-phase switch S... a6 After an open-circuit fault, the output voltage of phase A cannot reach +3E. Therefore, the waveform of the modulation wave was modified in this fault-tolerant method to maintain the normal operation of the inverter.

[0065] According to a specific embodiment of the present invention, in Figure 3(a), the output voltage of phase AB of the inverter is output during normal operation using the amplitude shift carrier modulation method in SPWM. Figure 3(b) shows the A-phase switch S. a6 Figure 3(c) shows the output voltage of phase AB after an open-circuit fault in phase A switch Sa6, which is controlled by fault tolerance. The output voltage is an eleven-level voltage obtained by subtracting the seven-level output voltages of the two phases with phase shift.

[0066] This inverter consists of two parts: a T-type inverter outputting voltages at three levels (+2E, 0, -2E), and a series-connected H-bridge unit outputting voltages at three levels (+E, 0, -E). Therefore, the total output voltage during normal operation is seven levels: +3E, +2E, +E, 0, -E, -2E, and -3E. A simulation of the normal operation of the hybrid topology seven-level inverter was performed. Figure 4(a) shows the voltage at a DC bus voltage of 580V, i.e., V... dc =580V, simulation diagram of phase A output voltage during normal operation.

[0067] When phase A H bridge S a6 During an open-circuit fault, the T-type inverter output voltage remains at three levels: +2E, 0, and -2E. The H-bridge unit connected in series outputs two levels: 0 and -E. If the switching state is not changed, the current will continue to flow through the faulty switch S. a6 The output voltage will be distorted. Figure 4(b) shows the output voltage when the DC bus voltage is 580V, i.e., V dc =580V, simulation diagram of phase A output voltage when phase A switch Sa6 is open-circuited. The fault-tolerant method in this invention utilizes the redundant switching states of the inverter to allow current to bypass the faulty device S. a6 To ensure the inverter continues to operate normally under fault conditions, the overall output voltage after fault-tolerant control is a six-level system, consisting of +2E, +E, 0, -E, -2E, and -3E. A simulation of the fault-tolerant method for the hybrid topology seven-level inverter was performed. Figure 4(c) shows the output voltage at a DC bus voltage of 580V, i.e., V... dc =580V, simulation diagram of phase A output voltage after fault-tolerant control.

[0068] When the inverter is operating normally, the three-phase output current remains balanced. Figure 5(a) shows a simulation diagram of the three-phase current when the inverter is operating normally. When phase A H-bridge S... a6 When an open-circuit fault occurs, some of the original switch states cannot output voltage normally in phase A, causing a change in the output voltage of phase A and distortion of the three-phase current. Figure 5(b) shows the simulation diagram of the three-phase current after the phase A fault. After fault-tolerant control, the original switch states are changed so that the current can only flow in reverse through the switching device S. a6 The output voltage distortion of phase A is eliminated, and the output voltage level is reduced from seven levels to six levels. A method of limiting the modulated wave is used to add the voltage difference between phase A and the original modulated wave to phases B and C. When calculating the line voltage, since all three phases (A, B, and C) have an equal difference added, the line voltage remains at the pre-fault level without distortion, thus generating a balanced three-phase current. Figure 5(c) shows the simulation diagram of the three-phase current after fault-tolerant control of phase A. Fast Fourier analysis of the three-phase current after fault-tolerant control shows that when the fundamental frequency is 50 Hz, the total harmonic distortion of the output current after fault-tolerant control is 4.10%, less than 5%, indicating a good current waveform that meets the conditions for normal inverter operation. Figure 5(d) shows the fundamental frequency, first harmonic, second harmonic, and total harmonic distortion of the output current after fault-tolerant control.

[0069] According to a specific embodiment of the present invention, when the inverter is operating normally, the sinusoidal modulation wave generated by the PI closed-loop control is shown in Figure 6(a). The fault-tolerance method in this invention involves modifying the reference voltages of each phase in the modulation wave when a fault occurs in a certain IGBT of a certain phase, thereby ensuring that the line voltage remains balanced after the fault. When the A-phase switch Sa6 experiences an open-circuit fault, the H-bridge output voltage level is 0, -E. The output voltage level range of the hybrid topology seven-level inverter is -3E to +2E, which cannot reach +3E. Therefore, when the original modulation wave is greater than +2E, the modulation wave is modified to be constant at +2E to maintain the normal operation of phase A.

[0070] Because there is a difference between the original modulation wave and the modified modulation wave during the stage where the original modulation wave is greater than +2E, the line voltages of phases AB and AC change when calculated before and after the fault. Furthermore, this change is not equal to the line voltage between phases BC, resulting in an imbalance of the three-phase line voltages. In this invention, the fault-tolerant method, after modifying the reference voltage of the faulty phase, simultaneously adds the difference between the original modulation wave and +2E to phases BC at every moment during the stage where the original modulation wave is greater than +2E, as shown in Figure 6(b). This ensures that the line voltages of phases AB, AC, and BC remain balanced with the line voltages before the fault when calculating line voltages at these moments, thereby balancing the three-phase currents and reducing current distortion.

[0071] Specifically, it is expressed as follows:

[0072]

[0073] V a * =2E,V x =V a * -V a '

[0074] V a V b V c For the modified three-phase reference voltage, V a ',V b ',V c The original three-phase reference voltage, V a * For S a6 The reference voltage of phase A after fault tolerance control, V x For V a * and V a The difference between ' and '.

[0075] That is, S a6The voltage changes from a sine wave before the fault to a straight line of +2E after the fault. We need to control it by using a reference voltage to adjust the voltage after the fault and maintain line voltage balance.

[0076] According to a specific embodiment of the present invention, when the inverter is operating normally, it is necessary to control the balance of the midpoint voltage connected to the T-type inverter and the voltage balance of the flying capacitor connected to the H-bridge unit by modulating the switch state. Since the control method for the flying capacitor voltage differs from that for the midpoint voltage and is only related to the switching state of the single-phase H-bridge unit, it cannot be jointly adjusted by the three-phase switch states. Therefore, the priority of controlling the flying capacitor voltage of the H-bridge unit is higher than that of the midpoint voltage. A constant is preset as a threshold. Since the system is a closed-loop control, when the system detects a flying capacitor voltage greater than this constant, flying capacitor voltage control is used preferentially; when the system detects a flying capacitor voltage less than this constant, midpoint voltage control is used preferentially. In the H-bridge unit, the direction of current flow is controlled by changing the switching state of the H-bridge, thereby controlling the charging and discharging state and time of the flying capacitor. When the inverter is operating normally, the voltage value of the flying capacitor is used to determine whether to charge or discharge. By utilizing the redundancy of the inverter, the charging and discharging of the flying capacitor can be controlled at the same output voltage level. Figure 7(a) is a simulation diagram of the flying capacitor voltage of the three-phase H-bridge unit when the inverter is working normally.

[0077] When phase A switch S a6 After an open-circuit fault, due to the loss of redundant state of the A-phase H-bridge unit switch, it is impossible to control the flying capacitor voltage balance through its redundant state. Figure 7(b) is a simulation diagram of the distortion of the flying capacitor voltage in the three-phase H-bridge unit after an open-circuit fault of the A-phase switch Sa6.

[0078] Analysis of the output voltage levels and switch states reveals that only the +3E, +E, -E, and -3E output levels affect the flying capacitor voltage, while the other three output levels, +2E, 0, and -2E, have no effect. This is because the A-phase switch S... a6 The fault causes phase A to fail to output a voltage level of +3E, resulting in an imbalance in the flying capacitor voltage within the phase A H-bridge unit over one cycle. The fault-tolerance method in this invention employs a modification of the modulation index to alter the modulation wave, thereby changing the timing of the output voltage level during the comparison between the modulation wave and the carrier wave. For example... Figure 2As shown in region 5, if the modulation waveform changes while the current direction remains unchanged, the output voltage +E and +2E times in this region will change, while the total time in region 5 remains unchanged. This is because the +2E output voltage does not affect the flying capacitor voltage, while the +E output voltage will cause the flying capacitor to charge (discharge). This fault-tolerant control method controls the charging and discharging time of the flying capacitor, ensuring that the flying capacitor voltage reaches charging and discharging balance within one cycle when the modulation index is within a certain range. For example, in this system, when the total harmonic distortion of the current is less than 5% and the flying capacitor voltage is balanced, the modulation index ranges from 0.66 to 0.74. Figure 7(c) is a simulation diagram showing the flying capacitor voltage in the three-phase H-bridge unit reaching charging and discharging balance again after fault-tolerant control.

[0079] According to a specific embodiment of the present invention, a method of modifying the modulation wave of the three-phase reference voltage is used for fault-tolerant control. Figure 8 This is a schematic diagram of a specific fault-tolerant method. For example, when the output voltage of phase A is greater than +2E, due to the switching transistor S of phase A... a6 The fault prevented the inverter from outputting a voltage level of +3E. Therefore, the portion of the original modulation wave in phase A that was greater than +2E was modified to be constant at +2E to maintain normal operation of the inverter. For phases B and C, during the period when the original modulation wave was greater than +2E, the difference between the modified modulation wave in phase A and the original modulation wave was added to phases B and C to keep the line voltage unchanged before and after the fault, thereby maintaining the balance of the three-phase current.

[0080] The present invention also provides the following product examples:

[0081] A hybrid multilevel inverter fault-tolerant control system includes:

[0082] The carrier modulation module is configured to use amplitude-shift carrier modulation to modulate N-1 in-phase stacked carriers, so that the T-type inverter section and the H-bridge unit share the same carrier for modulation, where N is the number of output voltage levels;

[0083] The fault-tolerant control module is configured to perform fault-tolerant control when an open-circuit fault occurs in the switching transistor of a certain phase H-bridge unit. It utilizes the redundant state of the switch to allow the current to bypass the faulty switching transistor, thereby transforming the hybrid topology N-level inverter in normal operation into an N-1 level inverter in fault operation.

[0084] A computer-readable storage medium storing a plurality of instructions adapted for loading by a processor of a terminal device and executing steps in the method.

[0085] A terminal device includes a processor and a computer-readable storage medium, the processor being configured to implement instructions; the computer-readable storage medium being configured to store a plurality of instructions adapted to be loaded by the processor and executed in accordance with the steps of the method described therein.

[0086] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0089] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0091] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A fault-tolerant control method for a hybrid multilevel inverter, characterized in that, Includes the following steps: Using amplitude-shift carrier modulation, N-1 in-phase superimposed carriers are modulated so that the T-type inverter section and the H-bridge unit share the same carrier for modulation, where N is the number of output voltage levels; When a certain phase H When the switching transistor of the bridge unit experiences an open-circuit fault, fault-tolerant control is implemented. The redundant state of the switch is used to allow the current to bypass the faulty switching transistor, so that the hybrid topology N-level inverter in normal operation is transformed into an N-1 level inverter in fault operation. The specific process of fault-tolerant control includes modifying the reference voltage of the three-phase modulation wave so that when a certain phase... H When a switch in the bridge unit fails, the modulation wave of the faulty phase is modified during the output voltage distortion stage to restore the output voltage of that phase to normal, i.e., the output voltage is at the N-1 level. At the same time, the difference between the reference voltage of the modulated wave after the fault phase is modified and the reference voltage of the modulated wave before the phase is modified is added to the other two normal phases during the output voltage distortion stage, so that the line voltage remains unchanged before and after the fault when calculating the line voltage, thus maintaining the balance of the three-phase current. When the current bypasses the faulty switch by utilizing the redundant state of the switch, the charging and discharging time of the flying capacitor is controlled by limiting the modulation. By controlling the conduction time of the output voltage state that affects the voltage change of the flying capacitor, the voltage of the flying capacitor is made to reach equilibrium as soon as possible.

2. The fault-tolerant control method for a hybrid multilevel inverter as described in claim 1, characterized in that, When a certain phase H When one of the switching transistors in the bridge unit fails, the inverter can maintain normal operation by utilizing the remaining output voltage state and the redundant switching state of the hybrid topology multilevel inverter.

3. The fault-tolerant control method for a hybrid multilevel inverter as described in claim 1, characterized in that, The difference between the reference voltage of the faulty phase after fault-tolerant control and the original reference voltage of the corresponding phase is obtained. The voltage of the non-faulty phase in the modified three-phase reference voltage is the sum of the three-phase reference voltage before modification and the difference value. The voltage of the faulty phase is the reference voltage after fault-tolerant control.

4. The fault-tolerant control method for a hybrid multilevel inverter as described in claim 1, characterized in that, Controlling the flying capacitor voltage has a higher priority than controlling the midpoint capacitor voltage.

5. The fault-tolerant control method for a hybrid multilevel inverter as described in claim 1, characterized in that, If the detected flying capacitor voltage is greater than the set threshold, flying capacitor voltage control will be used first; if the detected flying capacitor voltage is less than the set threshold, midpoint voltage control will be used first.

6. The fault-tolerant control method for a hybrid multilevel inverter as described in claim 1, characterized in that, By changing the switching state of the H-bridge, the direction of current flow in the flying capacitor is controlled, thereby controlling the charging and discharging state and time of the flying capacitor. When the inverter is working normally, the voltage value of the flying capacitor is compared with the rated value to determine whether charging and discharging is required. By utilizing the redundancy of the inverter, the charging and discharging of the flying capacitor can be controlled when the same voltage level is output.

7. A hybrid multilevel inverter fault-tolerant control system, characterized in that, include: The carrier modulation module is configured to use amplitude-shift carrier modulation to modulate N-1 in-phase stacked carriers, so that the T-type inverter section and the H-bridge unit share the same carrier for modulation, where N is the number of output voltage levels; The fault-tolerant control module is configured to... H When the switching transistor of the bridge unit experiences an open-circuit fault, fault-tolerant control is implemented. The redundant state of the switch is used to allow the current to bypass the faulty switching transistor, so that the hybrid topology N-level inverter in normal operation is transformed into an N-1 level inverter in fault operation. The specific process of fault-tolerant control includes modifying the reference voltage of the three-phase modulation wave so that when a certain phase... H When a switch in the bridge unit fails, the modulation wave of the faulty phase is modified during the output voltage distortion stage to restore the output voltage of that phase to normal, i.e., the output voltage is at the N-1 level. At the same time, the difference between the reference voltage of the modulated wave after the fault phase is modified and the reference voltage of the modulated wave before the phase is modified is added to the other two normal phases during the output voltage distortion stage, so that the line voltage remains unchanged before and after the fault when calculating the line voltage, thus maintaining the balance of the three-phase current. When the current bypasses the faulty switch by utilizing the redundant state of the switch, the charging and discharging time of the flying capacitor is controlled by limiting the modulation. By controlling the conduction time of the output voltage state that affects the voltage change of the flying capacitor, the voltage of the flying capacitor is made to reach equilibrium as soon as possible.

8. A hybrid topology multilevel inverter, characterized in that, Including three-phase bridge arms in parallel, each phase bridge arm includes T One arm and one of the three-level inverters H Bridge unit, T One arm of a three-level inverter consists of two reverse-connected series switches connected to a half-bridge unit, and the two ends of the half-bridge unit are connected to the two ends of two series-connected capacitors in the DC link. H The bridge unit consists of two two-level half-bridge units formed by four switching transistors connected in series end to end, and H The midpoints of the upper and lower bridge units are connected to the two ends of the flying capacitor; the midpoints of the two half-bridge units are respectively connected to the preceding stage. T Three-level inverter and the downstream power grid; Fault-tolerant control can be performed using any one of claims 1-6, or the control system described in claim 7 can be included.

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