A frequency dithering control circuit, a control chip, and a switching power supply

Abstract

This invention discloses a frequency dithering control circuit, a control chip, and a switching power supply. The frequency dithering control circuit includes: a narrow pulse generation module, used to convert an input high-level enable signal into a low-level narrow pulse after the control chip is started; a current source charging and discharging module, used to charge a capacitor connected to a pin of the control chip when a low-level narrow pulse is received, and simultaneously output a first voltage signal based on the voltage signal detected at its detection terminal; and to discharge the capacitor when no low-level narrow pulse is received at its input terminal; a level shifting module, used to convert the first voltage signal into a second voltage signal, either the supply voltage or ground level, and then output it; and a frequency dithering switch module, used to control the conduction and cutoff of the transmission gate based on the second voltage signal, the narrow pulse, and the enable signal, thereby enabling and disabling the frequency dithering function of the control chip. This invention reduces the design difficulty for application engineers.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic technology, and specifically to a frequency dithering control circuit, a control chip, and a switching power supply. Background Technology

[0002] Currently, an increasing number of switching power supply manufacturers are using frequency dithering technology to reduce electromagnetic interference (EMI). Frequency dithering technology reduces EMI by appropriately modulating the switching frequency to distribute radiated energy over a wider frequency range, reducing harmonic amplitude and smoothing it out.

[0003] However, frequency dithering technology is not without its drawbacks. In some applications, such as low-power, small-size applications, the output capacitor is very small, and frequency dithering technology often brings intolerable output ripple. In addition, some communication power supply standards explicitly prohibit the use of frequency dithering technology. Therefore, in such applications, chips that integrate frequency dithering technology are often abandoned, and ordinary chips are used for PWM control instead. This limits the application scope of chips that integrate frequency dithering function.

[0004] Based on existing technology, in order to meet the application requirements of both frequency dithering and non-frequency dithering, chip designers have to design two types of chips separately or add extra pins as frequency dithering enable pins. This undoubtedly increases the design and manufacturing costs for chip design manufacturers. For chip application manufacturers, in order to meet the two different application requirements, they have to use two types of chips to develop two different solutions, which increases the product design and product management costs for application manufacturers. Alternatively, they can design external enable circuits for the extra enable pins. These external enable circuits are often more complex, which increases the design difficulty and PCB layout area.

[0005] This invention is an innovative achievement resulting from further research and development by the applicant based on the inventive concept of a prior patent application, CN107294373A, which discloses a frequency dithering control circuit applied to a switching power supply control chip. Figure 1 This is a circuit block diagram of the frequency dithering control circuit 100 from the patent document with publication number CN107294373A. Figure 2 For integration Figure 1The schematic diagram of the application circuit of the frequency dithering control circuit 100 chip 10 is shown. The frequency dithering control circuit 100 includes a detection pin, a detection module 110, an enable module 120, and an enable signal output terminal EN connected in sequence. The detection pin is multiplexed with the pin RI of the switching power supply control chip. Its working principle is that at a specific moment after the chip 10 is started (such as after 2us), the detection module 110 starts to detect the voltage of the pin RI and generates a sampling voltage Vs, which is sent to the enable module 120. The enable module 120 compares the received sampling voltage Vs with the preset voltage V1. If the sampling voltage Vs is less than the preset voltage V1, it sends an enable signal EN to enable the frequency dithering module 200 and add the frequency dithering function to the switching power supply. Otherwise, the frequency dithering function is not added to the switching power supply.

[0006] The function of pin RI is to adjust the driving frequency of the control chip via an external resistor. When designing the frequency dithering control circuit, as long as the specific timing mentioned above is properly designed and the existing function of pin RI and the timing of frequency dithering are properly handled, pin reuse can be achieved, saving pins for the chip and reducing costs for the chip design company. It should be noted that... Figure 1 and Figure 2 The detection pin multiplexing of the frequency dithering control circuit 100 using pin RI of the control chip 10 is only one example; those skilled in the art can also reuse other pins, such as... Figure 2 For pins such as VCC or VFB, you only need to handle the existing functions of the multiplexed pins and the timing issues of frequency dithering determination.

[0007] The aforementioned prior patent allows selection of whether to incorporate frequency dithering by adding or removing capacitor C1 to pin RI. Adding capacitor C1 to RI reduces the voltage rise slope, resulting in a sampling voltage Vs that is less than the preset voltage V1 after a specified 2µs, thus incorporating frequency dithering into the power supply. Conversely, adding C1 prevents frequency dithering. Since 2µs is a short time, a low-voltage capacitor (nF level) is sufficient for selection, simplifying the power supply circuit. However, this patent focuses on implementing frequency dithering control through pin multiplexing of the power supply's control chip; specific circuit designs for the detection module 110 and enable module 120 require separate construction. Summary of the Invention

[0008] Therefore, the technical problem to be solved by the present invention is to provide a frequency dithering control circuit, a control chip, and a switching power supply. For the above-mentioned frequency dithering control achieved by multiplexing the pins of the control chip of the switching power supply, an effective specific circuit solution is provided.

[0009] As a first aspect of the present invention, an embodiment of the frequency dithering control circuit is provided as follows:

[0010] A frequency dithering control circuit is applied to a switching power supply. The switching power supply includes a control chip. During use, the switching power supply selects whether or not to add a frequency dithering function by connecting a capacitor to a certain pin of the control chip. The frequency dithering control circuit includes:

[0011] A narrow pulse generation module is provided, the input terminal of which is used to input the enable signal ENP of the control chip. After the control chip is started, the narrow pulse generation module is used to convert the high-level enable signal ENP input to its input terminal into a low-level narrow pulse Vpulse output.

[0012] A current source charging and discharging module has a power supply terminal for inputting the supply voltage VCC, a control terminal connected to the output terminal of the narrow pulse generation module, a detection terminal connected to a pin of the control chip, an output terminal for outputting a first voltage signal Viout, and a ground terminal for grounding. When the capacitor is connected to a pin of the control chip, the current source charging and discharging module, when receiving a low-level narrow pulse Vpulse at its input terminal, charges the capacitor with the supply voltage VCC, simultaneously detecting the voltage at its detection terminal. If this voltage is less than a first reference voltage Vref_2VRC, the first voltage signal Viout is set to a low level; if this voltage is greater than or equal to the first reference voltage Vref_2VRC, the first voltage signal Viout is set to a high level. When not receiving the low-level narrow pulse Vpulse at its input terminal, the module releases the energy stored in the capacitor.

[0013] The level shifting module has an input terminal connected to the output terminal of the current source charging and discharging module, a power supply terminal for inputting the power supply voltage VCC, and a ground terminal for grounding. The level shifting module is used to convert the first voltage signal Viout into a second voltage signal Vn and then output it. When the first voltage signal Viout is low, the second voltage signal Vn is the power supply voltage, and when the first voltage signal Viout is high, the second voltage signal Vn is the ground voltage.

[0014] The frequency dithering switch module includes a transmission gate, whose first input terminal is connected to the output terminal of the level shifting module, the second input terminal is connected to the output terminal of the narrow pulse generation module, and the third input terminal is connected to the input terminal of the narrow pulse generation module. The frequency dithering switch module is used to control the conduction and cutoff of the two ends of the transmission gate according to the second voltage signal Vn, the narrow pulse Vpulse, and the enable signal ENP, thereby realizing the addition and deactivation of the frequency dithering function of the control chip.

[0015] Preferably, the narrow pulse generation module includes: inverter INV1, inverter INV2, constant current source IB2, PMOS transistor PM4, NMOS transistor NM5, capacitor C2, Schmitt inverter Smt1, and NAND gate; the input terminal of inverter INV1 is the input terminal of the narrow pulse generation module, and the output terminal of inverter INV1 is simultaneously connected to the input terminal of inverter INV2, the gate of PMOS transistor PM4, and the gate of NMOS transistor NM4; the input terminal of constant current source IB2 is used to input power... The constant current source IB2 is connected to the source of the PMOS transistor PM4. The drain of the PMOS transistor PM4, the drain of the NMOS transistor NM4, the upper plate of the capacitor C2, and the input of the Schmitt inverter Smt1 are connected together. The output of the Schmitt inverter Smt1 is connected to one input of the NAND gate, and the output of the inverter INV2 is connected to the other input of the NAND gate. The output of the NAND gate is the output of the narrow pulse generation module.

[0016] Preferably, the current source charging and discharging module includes: a constant current source IB1, a PMOS transistor PM1, an NMOS transistor NM1, a PMOS transistor PM2, an NMOS transistor NM2, and a capacitor C3; the gate of the PMOS transistor PM2 serves as the input of the current source charging and discharging module and is connected to the output terminal of the narrow pulse generation module; the drain of the PMOS transistor PM2 and the input terminal of the constant current source IB1 are used to input the supply voltage, and the source of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM1 as the current. The detection terminal of the current source charging and discharging module has a first reference voltage Vref_2VRC input to the gate of the PMOS transistor PM1; the gates of the NMOS transistor NM1, NMOS transistor NM2, and the drain of the NMOS transistor NM1 are connected to the output terminal of the constant current source IB1; the sources of the NMOS transistor NM1 and NMOS transistor NM2 are connected to ground; and the drains of the PMOS transistor PM1 and NMOS transistor NM2 are connected together as the output terminal of the current source charging and discharging module 112.

[0017] Preferably, the level shifting module includes: a resistor R1 and an NMOS transistor NM3; one end of the resistor R1 is used to input the power supply voltage, the gate of the NMOS transistor NM3 is the input terminal of the level shifting module, the other end of the resistor R1 is connected to the drain of the NMOS transistor NM3 as the output terminal of the level shifting module, and the source of the NMOS transistor NM3 is used to connect to ground.

[0018] Preferably, the level shifting module includes: an inverter INV6, a PMOS transistor PM3, an NMOS transistor NM3, a PMOS transistor PM4, and an NMOS transistor NM4; the input terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM4 as the input terminal of the level shifting module, the output terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM3, the drain of the PMOS transistor PM3 and the drain of the PMOS transistor PM4 are connected together for inputting the power supply voltage, the source, gate, drain of the PMOS transistor PM3, source, gate, and drain of the NMOS transistor NM3 are connected together as the output terminal of the level shifting module, and the source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are connected to ground.

[0019] Preferably, the frequency dithering switch module includes a Schmitt inverter Smt2, a D flip-flop DFF, inverters INV3, INV4, and INV5, a PMOS transistor PM3, and an NMOS transistor NM4; the input terminal of the Schmitt inverter Smt2 is the first input terminal of the frequency dithering switch module, connected to the output terminal of the level shifting module; the input terminal of the inverter INV3 is the second input terminal of the frequency dithering switch module, connected to the output terminal of the narrow pulse generation module; the output terminal of the Schmitt inverter Smt2 is connected to the D terminal of the D flip-flop DFF; the Clr_L terminal of the D flip-flop DFF is the third input terminal of the frequency dithering switch module, connected to the input terminal of the narrow pulse generation module; and the CP_L terminal of the D flip-flop DFF... The output terminal of the inverter INV3 is connected to the output terminal of the inverter INV4. The Q terminal of the DFF of the D flip-flop is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the gate of the NMOS transistor NM4 and the input terminal of the inverter INV5. The gate of the PMOS transistor PM3 is connected to the output terminal of the inverter INV5. The source of the PMOS transistor PM3 and the drain of the NMOS transistor NM4 are connected together as the first output terminal of the frequency dithering switch module, i.e., the first terminal IRI_IN of the transmission gate. The drain of the PMOS transistor PM3 and the source of the NMOS transistor NM4 are connected together as the second output terminal of the frequency dithering switch module, i.e., the second terminal IRI_jitter of the transmission gate.

[0020] A frequency dithering control circuit is applied to a switching power supply. The switching power supply includes a control chip. During use, the switching power supply selects whether or not to add a frequency dithering function by connecting a capacitor to a certain pin of the control chip. The frequency dithering control circuit includes:

[0021] A narrow pulse generation module includes: inverter INV1, inverter INV2, constant current source IB2, PMOS transistor PM4, NMOS transistor NM5, capacitor C2, Schmitt inverter Smt1, and NAND gate; the input terminal of inverter INV1 is the input terminal of the narrow pulse generation module, used to input the enable signal ENP of the control chip; the output terminal of inverter INV1 is simultaneously connected to the input terminal of inverter INV2, the gate of PMOS transistor PM4, and the gate of NMOS transistor NM4; the output of constant current source IB2... The input terminal is used to input the power supply voltage. The output terminal of the constant current source IB2 is connected to the source of the PMOS transistor PM4. The drain of the PMOS transistor PM4, the drain of the NMOS transistor NM4, the upper plate of the capacitor C2, and the input terminal of the Schmitt inverter Smt1 are connected together. The output terminal of the Schmitt inverter Smt1 is connected to one input terminal of the NAND gate. The output terminal of the inverter INV2 is connected to the other input terminal of the NAND gate. The output terminal of the NAND gate is the output terminal of the narrow pulse generation module.

[0022] A current source charging / discharging module includes: a constant current source IB1, a PMOS transistor PM1, an NMOS transistor NM1, a PMOS transistor PM2, an NMOS transistor NM2, and a capacitor C3; the gate of the PMOS transistor PM2 serves as the input of the current source charging / discharging module and is connected to the output terminal of the narrow pulse generation module; the drain of the PMOS transistor PM2 and the input terminal of the constant current source IB1 are used to input the supply voltage; the source of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM1 together as the current source charging / discharging module. At the detection terminal of the discharge module, the gate of the PMOS transistor PM1 is input with a first reference voltage Vref_2VRC; the gates of the NMOS transistor NM1, NMOS transistor NM2, and the drain of the NMOS transistor NM1 are connected to the output terminal of the constant current source IB1; the sources of the NMOS transistor NM1 and NMOS transistor NM2 are connected to ground; and the drains of the PMOS transistor PM1 and NMOS transistor NM2 are connected together as the output terminal of the current source charging and discharging module 112.

[0023] A level shifting module includes: a resistor R1 and an NMOS transistor NM3; one end of the resistor R1 is used to input the power supply voltage, the gate of the NMOS transistor NM3 is the input terminal of the level shifting module, the other end of the resistor R1 is connected to the drain of the NMOS transistor NM3 as the output terminal of the level shifting module, and the source of the NMOS transistor NM3 is used to connect to ground;

[0024] The frequency dithering switch module includes: a Schmitt inverter Smt2, a D flip-flop DFF, inverters INV3, INV4, and INV5, a PMOS transistor PM3, and an NMOS transistor NM4. The input terminal of the Schmitt inverter Smt2 is the first input terminal of the frequency dithering switch module, connected to the output terminal of the level shifting module. The input terminal of the inverter INV3 is the second input terminal of the frequency dithering switch module, connected to the output terminal of the narrow pulse generation module. The output terminal of the Schmitt inverter Smt2 is connected to the D terminal of the D flip-flop DFF. The Clr_L terminal of the D flip-flop DFF is the third input terminal of the frequency dithering switch module, connected to the input terminal of the narrow pulse generation module. The CP_L terminal of the D flip-flop DFF is connected to... The output terminal of the inverter INV3 is connected to the output terminal of the inverter INV4. The Q terminal of the DFF of the D flip-flop is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the gate of the NMOS transistor NM4 and the input terminal of the inverter INV5. The gate of the PMOS transistor PM3 is connected to the output terminal of the inverter INV5. The source of the PMOS transistor PM3 and the drain of the NMOS transistor NM4 are connected together as the first output terminal of the frequency dithering switch module, i.e., the first terminal IRI_IN of the transmission gate. The drain of the PMOS transistor PM3 and the source of the NMOS transistor NM4 are connected together as the second output terminal of the frequency dithering switch module, i.e., the second terminal IRI_jitter of the transmission gate.

[0025] A frequency dithering control circuit is applied to a switching power supply. The switching power supply includes a control chip. During use, the switching power supply selects whether or not to add a frequency dithering function by connecting a capacitor to a certain pin of the control chip. The frequency dithering control circuit includes:

[0026] A narrow pulse generation module includes: inverter INV1, inverter INV2, constant current source IB2, PMOS transistor PM4, NMOS transistor NM5, capacitor C2, Schmitt inverter Smt1, and NAND gate; the input terminal of inverter INV1 is the input terminal of the narrow pulse generation module, used to input the enable signal ENP of the control chip; the output terminal of inverter INV1 is simultaneously connected to the input terminal of inverter INV2, the gate of PMOS transistor PM4, and the gate of NMOS transistor NM4; the output of constant current source IB2... The input terminal is used to input the power supply voltage. The output terminal of the constant current source IB2 is connected to the source of the PMOS transistor PM4. The drain of the PMOS transistor PM4, the drain of the NMOS transistor NM4, the upper plate of the capacitor C2, and the input terminal of the Schmitt inverter Smt1 are connected together. The output terminal of the Schmitt inverter Smt1 is connected to one input terminal of the NAND gate. The output terminal of the inverter INV2 is connected to the other input terminal of the NAND gate. The output terminal of the NAND gate is the output terminal of the narrow pulse generation module.

[0027] A current source charging / discharging module includes: a constant current source IB1, a PMOS transistor PM1, an NMOS transistor NM1, a PMOS transistor PM2, an NMOS transistor NM2, and a capacitor C3; the gate of the PMOS transistor PM2 serves as the input of the current source charging / discharging module and is connected to the output terminal of the narrow pulse generation module; the drain of the PMOS transistor PM2 and the input terminal of the constant current source IB1 are used to input the supply voltage; the source of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM1 together as the current source charging / discharging module. At the detection terminal of the discharge module, the gate of the PMOS transistor PM1 is input with a first reference voltage Vref_2VRC; the gates of the NMOS transistor NM1, NMOS transistor NM2, and the drain of the NMOS transistor NM1 are connected to the output terminal of the constant current source IB1; the sources of the NMOS transistor NM1 and NMOS transistor NM2 are connected to ground; and the drains of the PMOS transistor PM1 and NMOS transistor NM2 are connected together as the output terminal of the current source charging and discharging module 112.

[0028] A level shifting module includes: an inverter INV6, a PMOS transistor PM3, an NMOS transistor NM3, a PMOS transistor PM4, and an NMOS transistor NM4; the input terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM4 as the input terminal of the level shifting module; the output terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM3; the drains of the PMOS transistor PM3 and PM4 are connected together for inputting the power supply voltage; the sources, gates, drains of the PMOS transistor PM3, PM4, and NMOS transistor NM3 are connected together as the output terminal of the level shifting module; and the sources of the NMOS transistor NM3 and NM4 are connected to ground.

[0029] The frequency dithering switch module includes: a Schmitt inverter Smt2, a D flip-flop DFF, inverters INV3, INV4, and INV5, a PMOS transistor PM3, and an NMOS transistor NM4. The input terminal of the Schmitt inverter Smt2 is the first input terminal of the frequency dithering switch module, connected to the output terminal of the level shifting module. The input terminal of the inverter INV3 is the second input terminal of the frequency dithering switch module, connected to the output terminal of the narrow pulse generation module. The output terminal of the Schmitt inverter Smt2 is connected to the D terminal of the D flip-flop DFF. The Clr_L terminal of the D flip-flop DFF is the third input terminal of the frequency dithering switch module, connected to the input terminal of the narrow pulse generation module. The CP_L terminal of the D flip-flop DFF is connected to... The output terminal of the inverter INV3 is connected to the output terminal of the inverter INV4. The Q terminal of the DFF of the D flip-flop is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the gate of the NMOS transistor NM4 and the input terminal of the inverter INV5. The gate of the PMOS transistor PM3 is connected to the output terminal of the inverter INV5. The source of the PMOS transistor PM3 and the drain of the NMOS transistor NM4 are connected together as the first output terminal of the frequency dithering switch module, i.e., the first terminal IRI_IN of the transmission gate. The drain of the PMOS transistor PM3 and the source of the NMOS transistor NM4 are connected together as the second output terminal of the frequency dithering switch module, i.e., the second terminal IRI_jitter of the transmission gate.

[0030] As a second aspect of the present invention, the provided control chip embodiment is as follows:

[0031] A control chip is applied to a switching power supply. When the switching power supply is in use, the frequency dithering function can be selected by whether or not a capacitor is connected to a certain pin of the control chip. The control chip includes the frequency dithering control circuit described in any of the first aspects above.

[0032] As a third aspect of the present invention, the provided control chip embodiment is as follows:

[0033] A switching power supply includes a control chip. When in use, the switching power supply selects whether to add a frequency dithering function by selectively connecting a capacitor to a certain pin of the control chip. The switching power supply includes the frequency dithering control circuit described in any of the first aspects above.

[0034] The frequency dithering control circuit provided by this invention can enable the selection of whether to add frequency dithering function when the power supply is off, by choosing whether to connect a capacitor to a certain pin of the control chip. Moreover, the circuit is simple, which helps to reduce the design and manufacturing costs of control chip and switching power supply manufacturers. Attached Figure Description

[0035] Figure 1 The circuit block diagram of the frequency dithering control circuit 100 in the patent document with publication number CN107294373A;

[0036] Figure 2 For integration Figure 1 A schematic diagram of the application circuit of chip 10 in frequency dithering control circuit 100;

[0037] Figure 3 This is a circuit block diagram of the frequency dithering control circuit 100 according to the first embodiment of the present invention;

[0038] Figure 4 This is a specific circuit diagram of the frequency dithering control circuit according to the first embodiment of the present invention;

[0039] Figure 5 This is another specific circuit diagram of the frequency dithering control circuit according to the first embodiment of the present invention;

[0040] Figure 6 The switching power supply of the third embodiment of the present invention is applied Figure 4 Simulation waveform of the frequency dithering control circuit. Detailed Implementation

[0041] To make the objectives, circuit design, and advantages of this invention clearer, the invention will be further described in detail below with reference to examples. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0042] First Embodiment

[0043] This embodiment provides a frequency dithering control circuit. Figure 3 This is a frequency dithering control circuit diagram of the first embodiment of the present invention, applied to a switching power supply. The switching power supply includes a control chip 100. When in use, the switching power supply selects a certain pin of the control chip 100 ( Figure 3 Taking pin RI as an example, the selection of whether to add frequency dithering is achieved by connecting capacitor C1 or not. The frequency dithering control circuit includes:

[0044] The narrow pulse generation module 111 has an input terminal for inputting the enable signal ENP of the control chip 100. After the control chip 100 is started, the narrow pulse generation module 111 is used to convert the high-level enable signal ENP input to its input terminal into a low-level narrow pulse Vpulse output.

[0045] The current source charging and discharging module 112 has a power supply terminal for inputting the power supply voltage VCC, a control terminal connected to the output terminal of the narrow pulse generation module 111, a detection terminal connected to a pin of the control chip, an output terminal for outputting a first voltage signal Viout, and a ground terminal for grounding. When a capacitor C1 is connected to a pin of the control chip 100, the current source charging and discharging module 112 charges capacitor C1 with the power supply voltage VCC when it receives a low-level narrow pulse Vpulse at its input terminal, while simultaneously detecting the voltage at its detection terminal. If the voltage is less than the first reference voltage Vref_2VRC, the first voltage signal Viout is set to a low level; if the voltage is greater than or equal to the first reference voltage Vref_2VRC, the first voltage signal Viout is set to a high level. When it does not receive a low-level narrow pulse Vpulse at its input terminal, the energy stored in capacitor C1 is released.

[0046] The level shifting module 121 has an input terminal connected to the output terminal of the current source charging and discharging module 112, a power supply terminal for inputting the power supply voltage VCC, and a ground terminal for grounding. The level shifting module 121 is used to convert the first voltage signal Viout into a second voltage signal Vn and then output it. When the first voltage signal Viout is low, the second voltage signal Vn is the power supply voltage, and when the first voltage signal Viout is high, the second voltage signal Vn is the ground voltage.

[0047] The frequency dithering switch module 122 includes a transmission gate, whose first input terminal is connected to the output terminal of the level shift module 121, its second input terminal is connected to the output terminal of the narrow pulse generation module 111, and its third input terminal is connected to the input terminal of the narrow pulse generation module 111. The frequency dithering switch module 122 is used to control the conduction and cutoff of the two ends of the transmission gate according to the second voltage signal Vn, the narrow pulse Vpulse, and the enable signal ENP, thereby realizing the addition and deactivation of the frequency dithering function of the control chip 100.

[0048] Figure 3 The control chip 100 also involves other circuits within the chip, such as the first reference voltage Vref_2VRC generation circuit, the frequency dithering function generation circuit, and the reference current IB1 generation circuit and reference current IB2 generation circuit described below. These have many different circuit structures and are not relevant to this invention; therefore, they will not be described further, nor are they shown in the diagrams.

[0049] The high-level enable signal ENP of the control chip can start the operation of each module in the control chip.

[0050] Figure 4 For a specific circuit diagram of the frequency dithering control circuit of the first embodiment of the present invention, please refer to [link / reference]. Figure 4 The narrow pulse generation module 111 includes inverters INV1 and INV2, a constant current source IB2, a PMOS transistor PM4, an NMOS transistor NM5, a capacitor C2, a Schmitt inverter Smt1, and a NAND gate. The input terminal of inverter INV1 is the input terminal of the narrow pulse generation module 111, and the output terminal of inverter INV1 is simultaneously connected to the input terminal of inverter INV2, the gate of PMOS transistor PM4, and the gate of NMOS transistor NM4. The input terminal of the constant current source IB2... The constant current source IB2 is used to input the power supply voltage. Its output is connected to the source of PMOS transistor PM4. The drain of PMOS transistor PM4, the drain of NMOS transistor NM4, the upper plate of capacitor C2, and the input of Schmitt inverter Smt1 are connected together. The output of Schmitt inverter Smt1 is connected to one input of NAND gate NAND. The output of inverter INV2 is connected to the other input of NAND gate NAND. The output of NAND gate NAND is the output of narrow pulse generation module 111.

[0051] The working principle of the aforementioned narrow pulse generation module 111 is as follows: After the high-level enable signal ENP is input, it is changed to a low level by inverter INV1. This low level is input to inverter INV2, which is composed of PMOS transistor PM4 and NMOS transistor NM5. PMOS transistor PM4 is turned on, NMOS transistor NM4 is turned off, and constant current source IB2 charges capacitor C2 through PMOS transistor PM4, while simultaneously inputting to Schmitt inverter Smt1. Before the voltage at the input terminal of Smt1 reaches its flip threshold, the output of Schmitt inverter Smt1 is high; after the voltage at the input terminal of Smt1 reaches its flip threshold, the output of Schmitt inverter Smt1 is low. Inverter INV2 outputs a high level and is input to one input terminal of NAND gate, while the signal output of Schmitt inverter Smt1 is input to the other input terminal of NAND gate. Since the output of inverter INV2 is high, the output of NAND gate depends on the output of Schmitt inverter Smt1. When the output of Schmitt inverter Smt1 is high, the output of NAND gate is low; when the output of Schmitt inverter Smt1 is low, the output of NAND gate is high. This enables the high-level enable signal ENP input to the control chip to be converted into a low-level narrow pulse Vpulse output after the control chip is started.

[0052] Please continue reading Figure 4 The current source charging and discharging module 112 includes a constant current source IB1, a PMOS transistor PM1, an NMOS transistor NM1, a PMOS transistor PM2, an NMOS transistor NM2, and a capacitor C3. The gate of the PMOS transistor PM2 serves as the input of the current source charging and discharging module 112 and is connected to the output of the narrow pulse generation module 111. The drain of the PMOS transistor PM2 and the input of the constant current source IB1 are used to input the supply voltage. The source of the PMOS transistor PM2 and the drain of the PMOS transistor PM1 are connected together as the detection terminal of the current source charging and discharging module 112. The gate of the PMOS transistor PM1 receives the first reference voltage Vref_2VRC. The gates of the NMOS transistors NM1, NM2, and NM1 are connected to the output of the constant current source IB1. The sources of the NMOS transistors NM1 and NM2 are connected to ground. The drains of the PMOS transistors PM1 and NM2 are connected together as the output of the current source charging and discharging module 112.

[0053] The working principle of the current source charging and discharging module 112 is as follows: When the output of the narrow pulse generation module 111 is low, the PMOS transistor PM2 is turned on. If a capacitor is connected to the pin of the control chip multiplexed by the detection terminal of the current source charging and discharging module 112 (described below using pin RI as an example), the supply voltage charges the capacitor connected to pin RI through the drain of the PMOS transistor PM2 during the time when the narrow pulse Vpulse is low. When the voltage at pin RI is lower than the first reference voltage Vref_2VRC (e.g., 2V), the PMOS transistor PM1 is turned off. Since the NMOS transistor NM2 and NMOS transistor NM1 form a current mirror structure, the drain of the PMOS transistor PM1, i.e., the output terminal of 112, is pulled to ground by the NMOS transistor NM2 in the current mirror structure. The pull-up current is the current flowing through the NMOS transistor NM1 (i.e., the current flowing through the constant current source IB1) ​​replicated by the NMOS transistor NM2, and the output voltage signal Viout of the current source charging and discharging module 112 is low. Conversely, when the voltage at pin RI is higher than the 2V reference, the output voltage signal Viout of the current source charging / discharging module 112 is high. After the narrow pulse time, the charge stored on the capacitor is also released by the pull-down current (i.e., the current flowing through the constant current source IB1).

[0054] Please continue reading Figure 4 The level shifting module 121 includes a resistor R1 and an NMOS transistor NM3. One end of the resistor R1 is used to input the power supply voltage VCC, the gate of the NMOS transistor NM3 is the input terminal of the level shifting module 121, the other end of the resistor R1 is connected to the drain of the NMOS transistor NM3 as the output terminal of the level shifting module 121, and the source of the NMOS transistor NM3 is used to connect to ground.

[0055] The working principle of the above-mentioned level shift module 121 is as follows: when the output voltage signal Viout of the output terminal of 112 is low, that is, the gate of NMOS transistor NM3 is low, NMOS transistor NM3 is turned off, the drain of NMOS transistor NM3 is pulled to the supply voltage VCC through resistor R1, and the output of level shift module 121 is high; otherwise, the output of level shift module 121 is low.

[0056] Please continue reading Figure 4The frequency dithering switch module 122 includes a Schmitt inverter Smt2, a D flip-flop DFF, inverters INV3, INV4, and INV5, a PMOS transistor PM3, and an NMOS transistor NM4. The input of Schmitt inverter Smt2 is the first input of the frequency dithering switch module 122, connected to the output of the level shifting module 121. The input of inverter INV3 is the second input of the frequency dithering switch module 122, connected to the output of the narrow pulse generation module 111. The output of Schmitt inverter Smt2 is connected to the D terminal of the D flip-flop DFF. The Clr_L terminal of the D flip-flop DFF is the third input of the frequency dithering switch module 122, connected to the input of the narrow pulse generation module 111. The CP_L terminal of the D flip-flop DFF is connected to the output terminal of the inverter INV3. The Q terminal of the D flip-flop DFF is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the gate of the NMOS transistor NM4 and the input terminal of the inverter INV5. The gate of the PMOS transistor PM3 is connected to the output terminal of the inverter INV5. The source of the PMOS transistor PM3 and the drain of the NMOS transistor NM4 are connected together as the first output terminal of the frequency dithering switch module 122, i.e., the first terminal IRI_IN of the transmission gate. The drain of the PMOS transistor PM3 and the source of the NMOS transistor NM4 are connected together as the second output terminal of the frequency dithering switch module 122, i.e., the second terminal IRI_jitter of the transmission gate.

[0057] The working principle of the frequency dithering switch module 122 is as follows: When the input Vn of the frequency dithering switch module 122 is high, the D terminal of the D flip-flop DFF is low. The output of inverter INV3 is the inverted low-level narrow pulse, which is a high-level narrow pulse. The Clr_L terminal of the D flip-flop DFF is connected to the input terminal of the narrow pulse generation module 111, and the enable signal ENP is high. When the falling edge of the high-level narrow pulse output by inverter INV3 reaches the CP_L terminal of the D flip-flop DFF, the Q terminal of the DFF outputs the potential of its D terminal, so the Q terminal of the DFF outputs a low potential. The low potential output by the Q terminal becomes a high potential through inverter INV4, and then becomes a low potential through inverter INV5. These two potentials can respectively turn on NMOS transistor NM4 and PMOS transistor PM3. The transmission gate composed of PMOS transistor PM3 and NMOS transistor NM4 is turned on, and the chip has the frequency dithering function. Conversely, the transmission gate is closed, and the chip does not have the frequency dithering function.

[0058] Figure 5 This is another specific circuit diagram of the frequency dithering control circuit according to the first embodiment of the present invention, and... Figure 1 The difference lies in the circuit structure of the level shifting module 121.

[0059] Please see Figure 5The level shifting module 121 includes an inverter INV6, a PMOS transistor PM3, an NMOS transistor NM3, a PMOS transistor PM4, and an NMOS transistor NM4. The input terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM4 as the input terminal of the level shifting module 121. The output terminal of the inverter INV6 is connected to the gate of the NMOS transistor NM3. The drains of the PMOS transistor PM3 and PMOS transistor PM4 are connected together for input power supply voltage. The source, gate, drain, and PMOS transistor PM4 are connected together as the output terminal of the level shifting module 121. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are connected to ground.

[0060] The working principle of the aforementioned level shift module 121 is as follows: When the input terminal of the level shift module 121 is high, the NMOS transistor NM4 is turned on, the output terminal of the inverter INV6 is low, the NMOS transistor NM3 is not turned on, and its drain is high. The PMOS transistor PM4 is not turned on, and the drain of the PMOS transistor PM4 is pulled to ground by the drain of the NMOS transistor NM4, that is, the output of the level shift module 121 is low. Conversely, the output of the level shift module 121 is high, thus achieving the effect of level shifting.

[0061] Figure 5 The circuit is only relative to the level shifting module. Figure 4 With modifications, the working principle of level shifting is as described above. It can also realize whether to add frequency dithering function to the switching power supply by adding or not adding capacitor C1 to the RI pin of the control chip.

[0062] Second Embodiment

[0063] This embodiment provides a control chip for use in a switching power supply. When the switching power supply is in use, the frequency dithering function can be selected by whether or not to connect capacitor C1 to a certain pin of the control chip. The control chip includes a specific implementation circuit of any frequency dithering control circuit in the first embodiment.

[0064] Third Embodiment

[0065] This embodiment provides a switching power supply, including a control chip. When the switching power supply is in use, the frequency dithering function can be selected by whether or not to connect a capacitor C1 to a certain pin of the control chip. The switching power supply includes a specific implementation circuit of any frequency dithering control circuit in the first embodiment.

[0066] Figure 6 The switching power supply of the third embodiment of the present invention is applied Figure 4The simulation waveforms of the frequency dithering control circuit are shown below. From top to bottom, the first waveform represents the narrow pulse generated by the narrow pulse generation module 111; the second waveform is the voltage waveform at pin RI of the switching power supply control chip when capacitor C1 is not connected; the third waveform is the voltage waveform at pin RI of the switching power supply control chip when capacitor C1 is connected; the fourth waveform is the waveform of the NMOS transistor NM4 in the transmission gate driven by the signal output from pin RI when capacitor C1 is not connected, with PMOS transistor PM3 showing the opposite waveform; the fifth waveform is the waveform of the NMOS transistor NM4 in the transmission gate driven by the signal output from pin RI of the switching power supply control chip when capacitor C1 is connected, with PMOS transistor PM3 showing the opposite waveform. From... Figure 6 As can be seen, after connecting capacitor C1 to pin RI of the switching power supply control chip, the voltage rise slope at the pin slows down significantly. Simultaneously, the on / off signals at both ends of the transmission gate composed of the output driving NMOS transistor NM4 and PMOS transistor PM3 change sequentially depending on whether the capacitor is connected to the pin, thus achieving the switching control of the frequency dithering function.

[0067] The above description is a preferred embodiment of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention, such as setting a specific time to a preset time after the chip starts up or the power transistor turn-on time in each cycle, setting a specific time period to a preset time period after the chip starts up or the power transistor turn-on time period in each cycle, setting a specific pin to other functional pins, setting a specific state to current or other states, changing preset conditions, etc., should also be considered within the scope of protection of the present invention.

Claims

1. A frequency jitter control circuit applied to a switching power supply, the switching power supply comprising a control chip, the switching power supply, when in use, realizing selection of whether to add a frequency jitter function by selecting whether to connect a capacitor to a certain pin of the control chip. The jitter control circuit comprises: a narrow pulse generation module, an input end of which is used for inputting an enable signal ENP of the control chip, and the narrow pulse generation module is used for converting the high-level enable signal ENP input at the input end into a low-level narrow pulse Vpulse and outputting the low-level narrow pulse Vpulse after the control chip is started; a current source charging and discharging module, a power supply end of which is used for inputting a power supply voltage VCC, a control end of which is connected to an output end of the narrow pulse generation module, a detection end of which is used for connecting a pin of the control chip, an output end of which is used for outputting a first voltage signal Viout, and a ground end of which is used for grounding, and the current source charging and discharging module is used for charging the capacitor by the power supply voltage VCC when the low-level narrow pulse Vpulse is received at the input end in the case that the pin of the control chip is connected to the capacitor, simultaneously detecting a voltage at the detection end, and making the first voltage signal Viout low when the voltage is less than a first reference voltage Vref_2VRC, and making the first voltage signal Viout high when the voltage is greater than or equal to the first reference voltage Vref_2VRC; and the current source charging and discharging module is used for releasing the energy stored on the capacitor when the low-level narrow pulse Vpulse is not received at the input end; a level shift module, an input end of which is connected to an output end of the current source charging and discharging module, a power supply end of which is used for inputting a power supply voltage VCC, and a ground end of which is used for grounding, and the level shift module is used for converting the first voltage signal Viout into a second voltage signal Vn and outputting the second voltage signal Vn, wherein the second voltage signal Vn is the power supply voltage when the first voltage signal Viout is low, and the second voltage signal Vn is a ground voltage when the first voltage signal Viout is high; a jitter switch module, comprising a transmission gate, a first input end of which is connected to an output end of the level shift module, a second input end of which is connected to an output end of the narrow pulse generation module, and a third input end of which is connected to an input end of the narrow pulse generation module, and the jitter switch module is used for controlling conduction and shutdown of the transmission gate at two ends according to the second voltage signal Vn, the narrow pulse Vpulse and the enable signal ENP, so as to realize addition and shutdown of the jitter function of the control chip.

2. The frequency dithering control circuit of claim 1, wherein, The narrow pulse generation module comprises an inverter INV1, an inverter INV2, a constant current source IB2, a PMOS tube PM4, an NMOS tube NM5, a capacitor C2, a Schmitt inverter Smt1 and a NAND gate; the input end of the inverter INV1 is the input end of the narrow pulse generation module, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the gate of the PMOS tube PM4 and the gate of the NMOS tube NM4; the input end of the constant current source IB2 is used for inputting a supply voltage, the output end of the constant current source IB2 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4, the drain of the NMOS tube NM4, the upper plate of the capacitor C2 and the input end of the Schmitt inverter Smt1 are connected together; the output end of the Schmitt inverter Smt1 is connected to one input end of the NAND gate, the output end of the inverter INV2 is connected to the other input end of the NAND gate, and the output end of the NAND gate is the output end of the narrow pulse generation module.

3. The frequency dithering control circuit of claim 1, wherein, The current source charging and discharging module comprises a constant current source IB1, a PMOS tube PM1, an NMOS tube NM1, a PMOS tube PM2, an NMOS tube NM2 and a capacitor C3; the gate of the PMOS tube PM2 is used as the input of the current source charging and discharging module and is connected to the output end of the narrow pulse generation module; the drain of the PMOS tube PM2 and the input end of the constant current source IB1 are used for inputting the supply voltage, the source of the PMOS tube PM2 and the drain of the PMOS tube PM1 are connected together and are used as the detection end of the current source charging and discharging module, the gate of the PMOS tube PM1 inputs a first reference voltage Vref_2VRC; the gate of the NMOS tube NM1, the gate of the NMOS tube NM2 and the drain of the NMOS tube NM1 are connected to the output end of the constant current source IB1, the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are used for being connected to the ground, and the drain of the PMOS tube PM1 and the drain of the NMOS tube NM2 are connected together and are used as the output end of the current source charging and discharging module 112.

4. The frequency dithering control circuit of claim 1, wherein, The level shift module comprises a resistor R1 and an NMOS tube NM3; one end of the resistor R1 is used for inputting the supply voltage, the gate of the NMOS tube NM3 is the input end of the level shift module, the other end of the resistor R1 and the drain of the NMOS tube NM3 are connected together and are used as the output end of the level shift module, and the source of the NMOS tube NM3 is used for being connected to the ground.

5. The frequency dithering control circuit of claim 1, wherein, The level shift module comprises an inverter INV6, a PMOS tube PM3, an NMOS tube NM3, a PMOS tube PM4 and an NMOS tube NM4; an input end of the inverter INV6 is connected with a gate of the NMOS tube NM4 together as an input end of the level shift module, an output end of the inverter INV6 is connected with a gate of the NMOS tube NM3, a drain of the PMOS tube PM3 and a drain of the PMOS tube PM4 are connected together for inputting the supply voltage, a source of the PMOS tube PM3, a gate of the PMOS tube PM3, a drain of the NMOS tube NM3, a source of the PMOS tube PM4, a gate of the PMOS tube PM4 and a drain of the NMOS tube NM3 are connected together as an output end of the level shift module, and a source of the NMOS tube NM3 and a source of the NMOS tube NM4 are connected to the ground.

6. The frequency dithering control circuit of claim 1, wherein, The jitter switch module comprises a Schmitt inverter Smt2, a D flip-flop DFF, an inverter INV3, an inverter INV4, an inverter INV5, a PMOS tube PM3 and an NMOS tube NM4; an input end of the Schmitt inverter Smt2 is a first input end of the jitter switch module and is connected with an output end of the level shift module, an input end of the inverter INV3 is a second input end of the jitter switch module and is connected with an output end of the narrow pulse generation module, a D end of the D flip-flop DFF is connected with an output end of the Schmitt inverter Smt2, a Clr_L end of the D flip-flop DFF is a third input end of the jitter switch module and is connected with an input end of the narrow pulse generation module, a CP_L end of the D flip-flop DFF is connected with an output end of the inverter INV3, a Q end of the D flip-flop DFF is connected with an input end of the inverter INV4, an output end of the inverter INV4 is connected with a gate of the NMOS tube NM4 and an input end of the inverter INV5, a gate of the PMOS tube PM3 is connected with an output end of the inverter INV5, a source of the PMOS tube PM3 and a drain of the NMOS tube NM4 are connected together as a first output end of the jitter switch module, i.e. a first end IRI_IN of the transmission gate, and a drain of the PMOS tube PM3 and a source of the NMOS tube NM4 are connected together as a second output end of the jitter switch module, i.e. a second end IRI_jitter of the transmission gate.

7. A frequency jitter control circuit applied to a switching power supply, the switching power supply comprising a control chip, the switching power supply, when in use, realizing selection of whether to add a frequency jitter function by selecting whether to connect a capacitor to a certain pin of the control chip. The jitter control circuit comprises: The narrow pulse generation module comprises an inverter INV1, an inverter INV2, a constant current source IB2, a PMOS tube PM4, an NMOS tube NM5, a capacitor C2, a Schmitt inverter Smt1 and a NAND gate; the input end of the inverter INV1 is the input end of the narrow pulse generation module, used for inputting the enable signal ENP of the control chip, the output end of the inverter INV1 is connected to the input end of the inverter INV2, the gate of the PMOS tube PM4 and the gate of the NMOS tube NM4; the input end of the constant current source IB2 is used for inputting a supply voltage, the output end of the constant current source IB2 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4, the drain of the NMOS tube NM4 and the upper plate of the capacitor C2 are connected together, and the output end of the Schmitt inverter Smt1 is connected to one input end of the NAND gate; the output end of the inverter INV2 is connected to the other input end of the NAND gate, and the output end of the NAND gate is the output end of the narrow pulse generation module; The current source charging and discharging module comprises a constant current source IB1, a PMOS tube PM1, an NMOS tube NM1, a PMOS tube PM2, an NMOS tube NM2 and a capacitor C3; the gate of the PMOS tube PM2 is connected to the output end of the narrow pulse generation module and serves as the input of the current source charging and discharging module; the drain of the PMOS tube PM2 and the input end of the constant current source IB1 are used for inputting the supply voltage, the source of the PMOS tube PM2 and the drain of the PMOS tube PM1 are connected together and serve as the detection end of the current source charging and discharging module, the gate of the PMOS tube PM1 inputs a first reference voltage Vref_2VRC; the gate of the NMOS tube NM1, the gate of the NMOS tube NM2 and the drain of the NMOS tube NM1 are connected to the output end of the constant current source IB1, the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are used for being connected to the ground, and the drain of the PMOS tube PM1 and the drain of the NMOS tube NM2 are connected together and serve as the output end of the current source charging and discharging module 112; The level shift module comprises a resistor R1 and an NMOS tube NM3; one end of the resistor R1 is used for inputting the supply voltage, the gate of the NMOS tube NM3 is the input end of the level shift module, the other end of the resistor R1 and the drain of the NMOS tube NM3 are connected together and serve as the output end of the level shift module, and the source of the NMOS tube NM3 is used for being connected to the ground. The jitter frequency switching module comprises a Schmitt inverter Smt2, a D flip-flop DFF, an inverter INV3, an inverter INV4, an inverter INV5, a PMOS tube PM3 and an NMOS tube NM4; the input end of the Schmitt inverter Smt2 is the first input end of the jitter frequency switching module, and is connected to the output end of the level shift module; the input end of the inverter INV3 is the second input end of the jitter frequency switching module, and is connected to the output end of the narrow pulse generation module; the output end of the Schmitt inverter Smt2 is connected to the D end of the D flip-flop DFF; the Clr_L end of the D flip-flop DFF is the third input end of the jitter frequency switching module, and is connected to the input end of the narrow pulse generation module; the CP_L end of the D flip-flop DFF is connected to the output end of the inverter INV3; the Q end of the D flip-flop DFF is connected to the input end of the inverter INV4; the output end of the inverter INV4 is connected to the gate of the NMOS tube NM4 and the input end of the inverter INV5; the gate of the PMOS tube PM3 is connected to the output end of the inverter INV5; the source of the PMOS tube PM3 and the drain of the NMOS tube NM4 are connected together as the first output end of the jitter frequency switching module, i.e. the first end IRI_IN of the transmission gate; and the drain of the PMOS tube PM3 and the source of the NMOS tube NM4 are connected together as the second output end of the jitter frequency switching module, i.e. the second end IRI_jitter of the transmission gate.

8. A frequency jitter control circuit applied to a switching power supply, the switching power supply comprising a control chip, the switching power supply, when in use, realizing selection of whether to add a frequency jitter function by selecting whether to connect a capacitor to a certain pin of the control chip. The jitter frequency control circuit comprises: The narrow pulse generation module comprises an inverter INV1, an inverter INV2, a constant current source IB2, a PMOS tube PM4, an NMOS tube NM5, a capacitor C2, a Schmitt inverter Smt1 and a NAND gate; the input end of the inverter INV1 is the input end of the narrow pulse generation module, and is used for inputting the enable signal ENP of the control chip; the output end of the inverter INV1 is connected to the input end of the inverter INV2, the gate of the PMOS tube PM4 and the gate of the NMOS tube NM4; the input end of the constant current source IB2 is used for inputting a supply voltage; the output end of the constant current source IB2 is connected to the source of the PMOS tube PM4; the drain of the PMOS tube PM4, the drain of the NMOS tube NM4, the upper plate of the capacitor C2 and the input end of the Schmitt inverter Smt1 are connected together; the output end of the Schmitt inverter Smt1 is connected to one input end of the NAND gate; the output end of the inverter INV2 is connected to the other input end of the NAND gate; and the output end of the NAND gate is the output end of the narrow pulse generation module. The current source charging and discharging module comprises a constant current source IB1, a PMOS tube PM1, an NMOS tube NM1, a PMOS tube PM2, an NMOS tube NM2 and a capacitor C3; a gate of the PMOS tube PM2 is connected with an output end of the narrow pulse generation module as an input of the current source charging and discharging module; a drain of the PMOS tube PM2 and an input end of the constant current source IB1 are used for inputting the power supply voltage; a source of the PMOS tube PM2 and a drain of the PMOS tube PM1 are connected together as a detection end of the current source charging and discharging module, and a gate of the PMOS tube PM1 inputs a first reference voltage Vref_2VRC; a gate of the NMOS tube NM1, a gate of the NMOS tube NM2 and a drain of the NMOS tube NM1 are connected with an output end of the constant current source IB1, a source of the NMOS tube NM1 and a source of the NMOS tube NM2 are used for being connected to the ground, and a drain of the PMOS tube PM1 and a drain of the NMOS tube NM2 are connected together as an output end of the current source charging and discharging module 112; The level shift module comprises an inverter INV6, a PMOS tube PM3, an NMOS tube NM3, a PMOS tube PM4 and an NMOS tube NM4; an input end of the inverter INV6 and a gate of the NMOS tube NM4 are connected together as an input end of the level shift module, an output end of the inverter INV6 and a gate of the NMOS tube NM3 are connected, a drain of the PMOS tube PM3 and a drain of the PMOS tube PM4 are connected together for inputting the power supply voltage, a source of the PMOS tube PM3, a gate of the PMOS tube PM3, a drain of the NMOS tube NM3, a source of the PMOS tube PM4, a gate of the PMOS tube PM4 and a drain of the NMOS tube NM3 are connected together as an output end of the level shift module, and a source of the NMOS tube NM3 and a source of the NMOS tube NM4 are connected to the ground; The jitter switch module comprises a Schmitt inverter Smt2, a D flip-flop DFF, an inverter INV3, an inverter INV4, an inverter INV5, a PMOS tube PM3 and an NMOS tube NM4; the input end of the Schmitt inverter Smt2 is the first input end of the jitter switch module, and is connected with the output end of the level shift module; the input end of the inverter INV3 is the second input end of the jitter switch module, and is connected with the output end of the narrow pulse generation module; the output end of the Schmitt inverter Smt2 is connected with the D end of the D flip-flop DFF; the Clr_L end of the D flip-flop DFF is the third input end of the jitter switch module, and is connected with the input end of the narrow pulse generation module; the CP_L end of the D flip-flop DFF is connected with the output end of the inverter INV3; the Q end of the D flip-flop DFF is connected with the input end of the inverter INV4; the output end of the inverter INV4 is connected with the gate of the NMOS tube NM4 and the input end of the inverter INV5; the gate of the PMOS tube PM3 is connected with the output end of the inverter INV5; the source of the PMOS tube PM3 and the drain of the NMOS tube NM4 are connected together as the first output end of the jitter switch module, i.e. the first end IRI_IN of the transmission gate; and the drain of the PMOS tube PM3 and the source of the NMOS tube NM4 are connected together as the second output end of the jitter switch module, i.e. the second end IRI_jitter of the transmission gate.

9. A control chip applied to a switching power supply, when in use, whether to add a frequency jitter function is realized by selecting whether to connect a capacitor to a certain pin of the control chip. The control chip comprises the jitter control circuit according to any one of claims 1-8. 10.A switching power supply comprising a control chip, wherein when in use, whether to add a jitter function is realized by selecting whether to connect a capacitor at a certain pin of the control chip, and the switching power supply comprises the jitter control circuit according to any one of claims 1-8.

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