Low-noise amplifiers and RF chips

Abstract

The present invention provides a low-noise amplifier and radio frequency chip. The low-noise amplifier includes a signal input terminal, a common-source and common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, a signal output terminal, a first switch, a third switch, a fourth switch, a bypass matching circuit, a transistor bias access circuit, and a control logic circuit; the output matching network includes a first output matching circuit and a second output matching circuit; the common-source and common-gate low-noise amplifier link includes a first inductor, a second switch, a first capacitor, a first transistor, a second transistor, a second inductor, and a third inductor; and the control logic circuit is used to control the on / off switching actions of the transistor bias access circuit, the first switch, the second switch, the third switch, and the fourth switch, respectively. Compared with related technologies, the technical solution of the present invention has diverse modes and functions, effectively achieves out-of-band narrowband suppression in a single frequency band, and has strong anti-interference capabilities and high sensitivity.

Description

Technical Field

[0001] The present invention relates to the field of amplifier circuits, and in particular to a low-noise amplifier and a radio frequency chip. Background Art

[0002] As humanity enters the information age, wireless communication technology has developed rapidly. From mobile phones to wireless LANs and Bluetooth, these technologies have become an integral part of social life and development. The advancement of wireless communication technology is inseparable from the development of radio frequency circuits. In wireless transceiver systems, the radio frequency low-noise amplifier (LNA) is a crucial component. The LNA amplifies the signal power, obtaining sufficient RF power before the signal is fed to the antenna for radiation. Among these, the LNA's gain and return loss are crucial performance indicators.

[0003] Related art low-noise amplifiers typically include an input matching circuit, a cascode amplifier, and an output matching circuit. The low-noise amplifier processes the power signal input from the input matching circuit through the cascode amplifier and then outputs it through the output matching circuit, thereby achieving low noise.

[0004] However, the related art low-noise amplifier uses a common-gate cascode amplifier to amplify signals, outputting a fixed low-noise power signal. This results in limited functionality and poor reliability. Furthermore, while the low-noise amplifier's receive path can be used in both the 5GHz and 2.4GHz WiFi bands, when used in the 5GHz WiFi band, the related art low-noise amplifier is unable to suppress the 2.4GHz WiFi band, resulting in poor anti-interference capabilities in the receive link and low downlink sensitivity.

[0005] Therefore, it is necessary to provide a new low noise amplifier and radio frequency chip to solve the above problems. Summary of the Invention

[0006] In view of the above shortcomings of the existing technology, the present invention proposes a low-noise amplifier and radio frequency chip with diverse modes and functions, which can effectively achieve out-of-band narrowband suppression of a single frequency band, have strong anti-interference ability and high sensitivity.

[0007] In order to solve the above technical problems, in a first aspect, an embodiment of the present invention provides a low-noise amplifier, which includes a signal input terminal, a common-source common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, and a signal output terminal connected in sequence.

[0008] The low-noise amplifier further includes a first switch, a third switch, a fourth switch, a bypass matching circuit, and a transistor bias access circuit; the output matching network includes a first output matching circuit for implementing filtering of a separate frequency band and a second output matching circuit for converting the output impedance to a preset target output impedance; the cascode low-noise amplifier link includes a first inductor, a second switch, a first capacitor, a first transistor, a second transistor, a second inductor, and a third inductor;

[0009] The signal input terminal is connected to the first terminal of the first inductor; the second terminal of the first inductor is connected to the first terminal of the first switch and the first terminal of the second switch respectively;

[0010] The second end of the first switch is connected to the input end of the bypass matching circuit and the first end of the fourth switch respectively; the second end of the fourth switch is grounded;

[0011] The output end of the bypass matching circuit is connected to the first end of the third switch; the second end of the third switch is connected to the output end of the first output matching circuit and the input end of the second output matching circuit respectively;

[0012] The second end of the second switch is connected to the first end of the first capacitor; the second end of the first capacitor is connected to the gate of the first transistor;

[0013] The source of the first transistor is connected to the first end of the second inductor; the second end of the second inductor is connected to the first end of the transistor bias access circuit; the second end of the transistor bias access circuit is grounded; the third end of the transistor bias access circuit is used to connect to an external control logic circuit, and the control logic circuit is used to control the operations of the transistor bias access circuit, the first switch, the second switch, the third switch, and the fourth switch respectively;

[0014] The drain of the first transistor is connected to the source of the second transistor; the gate of the second transistor is grounded;

[0015] The drain of the second transistor is connected to the input terminal of the first output matching circuit and the first terminal of the third inductor respectively; the second terminal of the third inductor is used to be connected to the power supply voltage;

[0016] The output end of the second output matching circuit is connected to the first end of the output resistance attenuation network; the second end of the output resistance attenuation network is connected to the signal output end; and the third end of the output resistance attenuation network is grounded.

[0017] Preferably, the low noise amplifier further includes a third capacitor; a first end of the third capacitor is connected to the gate of the second transistor; and a second end of the third capacitor is grounded.

[0018] Preferably, the low noise amplifier further includes a second resistor; a first end of the second resistor is connected to the gate of the second transistor; and a second end of the second resistor is used to be connected to a second bias voltage.

[0019] Preferably, the low noise amplifier further includes a first resistor; a first end of the first resistor is connected to the gate of the first transistor; and a second end of the first resistor is used to be connected to a first bias voltage.

[0020] Preferably, the bypass matching circuit includes a second capacitor; a first end of the second capacitor serves as an input end of the bypass matching circuit, and a second end of the second capacitor serves as an output end of the bypass matching circuit.

[0021] Preferably, the first output matching circuit includes a third resistor, a fifth capacitor, a sixth capacitor, a fifth switch, a sixth switch, and a seventh switch; and the second output matching circuit includes a seventh capacitor, an eighth capacitor, an eighth switch, and a ninth switch;

[0022] The first end of the fifth capacitor serves as an input end of the first output matching circuit, and the first end of the fifth capacitor is respectively connected to the first end of the third resistor, the first end of the sixth capacitor, and the first end of the eighth capacitor; the second end of the third resistor is connected to the first end of the fifth switch, and the second end of the fifth switch is grounded; the second end of the sixth capacitor is connected to the first end of the sixth switch, and the second end of the sixth switch is grounded;

[0023] The second end of the fifth capacitor is connected to the second end of the seventh switch; the first end of the seventh switch serves as the output end of the first output matching circuit, and the first end of the seventh switch is connected to the first end of the seventh capacitor; the first end of the seventh capacitor serves as the input end of the second output matching circuit;

[0024] The second end of the seventh capacitor is connected to the first end of the eighth switch; the second end of the eighth switch serves as the output end of the second output matching circuit, and the second end of the eighth switch is connected to the first end of the ninth switch;

[0025] The second end of the ninth switch is connected to the second end of the eighth capacitor.

[0026] Preferably, the output resistance attenuation network includes a tenth switch, an eleventh switch, a twelfth switch, a ninth capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0027] The first end of the fourth resistor serves as the first end of the output resistance attenuation network, and the first end of the fourth resistor is connected to the first end of the twelfth switch and the first end of the ninth capacitor respectively;

[0028] The second end of the ninth capacitor is connected to the first end of the tenth switch; the second end of the tenth switch is grounded;

[0029] The second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the sixth resistor respectively;

[0030] The second end of the fifth resistor serves as the second end of the output resistance attenuation network, and the second end of the fifth resistor is connected to the second end of the twelfth switch;

[0031] The second end of the sixth resistor is connected to the first end of the eleventh switch;

[0032] The second end of the eleventh switch serves as the third end of the output resistance attenuation network, and the second end of the eleventh switch is grounded.

[0033] Preferably, the transistor bias access circuit includes a third transistor; the source of the third transistor serves as the second end of the transistor bias access circuit; the drain of the third transistor serves as the first end of the transistor bias access circuit; and the gate of the third transistor serves as the third end of the transistor bias access circuit.

[0034] Preferably, the first transistor, the second transistor and the third transistor are all NMOS transistors.

[0035] In a second aspect, an embodiment of the present invention further provides a radio frequency chip, wherein the radio frequency chip includes the low noise amplifier provided in the embodiment of the present invention.

[0036] Compared to related art, the low-noise amplifier and RF chip of the present invention are provided with a cascode low-noise amplifier link including a source-level negative feedback inductor, a first switch, a second switch, a third switch, a fourth switch, a transistor bias access circuit, and a bypass matching circuit; by connecting the bypass matching circuit to both ends of the cascode low-noise amplifier link, and controlling the on / off of the bypass matching circuit by turning on or off the transistor bias access circuit, the first switch, the second switch, the third switch, and the fourth switch, multiple bypass mode functions and amplification mode functions are achieved, resulting in low return loss at the operating frequency of the low-noise amplifier and high reliability. In addition, the low-noise amplifier and RF chip of the present invention are provided with a first output matching circuit for filtering a single frequency band and a second output matching circuit for converting the output impedance to a preset target output impedance; the first output matching circuit generates a low impedance point at a low frequency, thereby achieving filtering of a single frequency band, for example, achieving channel suppression of the 2.4 GHz WiFi band in the 5 GHz WiFi receiving path, effectively achieving out-of-band narrowband suppression of a single frequency band. More preferably, within the operating frequency band, after the signal passes through the first output matching circuit and the second output matching circuit in sequence, the output impedance is converted to a preset target output impedance, so that the low-noise amplifier and the radio frequency chip of the present invention reduce the return loss, thereby making the low-noise amplifier and the radio frequency chip of the present invention have strong anti-interference ability and high sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings.

[0038] Figure 1 A circuit module structure diagram of a low noise amplifier according to an embodiment of the present invention;

[0039] Figure 2 is a circuit diagram of a low noise amplifier according to an embodiment of the present invention;

[0040] Figure 3 is an equivalent circuit diagram of a low noise amplifier in bypass mode according to an embodiment of the present invention;

[0041] Figure 4 is a graph showing the relationship between S21 and frequency in the bypass mode of a low noise amplifier in the related art;

[0042] Figure 5 FIG. 4 is a graph showing the relationship between S21 and frequency in the bypass mode of the low noise amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] The specific embodiments / examples described herein are specific embodiments of the present invention and are used to illustrate the concept of the present invention. They are illustrative and exemplary and should not be construed as limiting the embodiments of the present invention or the scope of the present invention. In addition to the examples described herein, those skilled in the art can also adopt other obvious technical solutions based on the claims and the disclosure of the specification. These technical solutions, including any obvious replacements and modifications of the embodiments described herein, are all within the scope of protection of the present invention.

[0045] The present invention provides a low noise amplifier 100 .

[0046] Please also refer to Figures 1 to 2 As shown, Figure 1 FIG1 is a circuit module structure diagram of a low noise amplifier 100 according to an embodiment of the present invention; Figure 2 FIG. 1 is a circuit diagram of a low noise amplifier 100 according to an embodiment of the present invention.

[0047] Specifically, the low noise amplifier 100 includes a signal input terminal RFin, a common source and common gate low noise amplifier link 1 including a source-level negative feedback inductor, an output matching network 4, an output resistance attenuation network 5 and a signal output terminal RFout, which are connected in sequence.

[0048] The low noise amplifier 100 further includes a first switch S1 , a third switch S3 , a fourth switch S4 , a bypass matching circuit 2 , and a transistor bias access circuit 3 control logic circuit.

[0049] The cascode low-noise amplifier link 1 includes a first inductor L1, a second switch S2, a first capacitor C1, a first transistor M1, a second transistor M2, a second inductor L2, and a third inductor L3. The first inductor L1 and the second inductor L2 are both commonly used in the art. The third inductor L3 is an RF choke inductor used to provide a DC operating point. The first transistor M1 is a common-source amplifier, and the second transistor M2 is a common-gate amplifier. The first capacitor C1 is a DC blocking capacitor used to isolate DC current from passing through.

[0050] In this embodiment, the first transistor M1 and the second transistor M2 are both NMOS transistors. Of course, the present invention is not limited thereto. The first transistor M1 and the second transistor M2 may also be PMOS transistors. The corresponding circuit structure may be modified according to the circuit of the PMOS transistor and adjusted according to the specific design requirements. Detailed description is omitted here.

[0051] The bypass matching circuit 2 includes a second capacitor C2. A first end of the second capacitor C2 serves as an input end of the bypass matching circuit 2. A second end of the second capacitor C2 serves as an output end of the bypass matching circuit 2.

[0052] The transistor bias connection circuit 3 includes a third transistor M3. The source of the third transistor M3 serves as the second terminal of the transistor bias connection circuit 3. The drain of the third transistor M3 serves as the first terminal of the transistor bias connection circuit 3. The gate of the third transistor M3 serves as the third terminal of the transistor bias connection circuit 3. The third terminal of the transistor bias connection circuit 3 is connected to an external control logic circuit. The control logic circuit is used to control the operation of the transistor bias connection circuit 3, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4.

[0053] In this embodiment, the third transistor M3 is an NMOS transistor.

[0054] The control logic circuit is used to control the on / off switching actions of the transistor bias access circuit 3, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, respectively. The control logic circuit is a digital logic circuit. It should be noted that the specific circuit is designed and generated according to the design requirements. This process uses existing technology and does not require improvements in circuit algorithms or methods or software improvements. Of course, without limitation to this, the control logic circuit can also be implemented using a processor. In another embodiment, the low-noise amplifier 100 is connected to the control logic circuit and manufactured into a module circuit.

[0055] The output matching network 4 includes a first output matching circuit 41 for implementing filtering of a single frequency band and a second output matching circuit 42 for converting the output impedance to a preset target output impedance.

[0056] Specifically, the first output matching circuit 41 includes a third resistor R3, a fifth capacitor C5, a sixth capacitor C6, a fifth switch S5, a sixth switch S6, and a seventh switch S7. The second output matching circuit 42 includes a seventh capacitor C7, an eighth capacitor C8, an eighth switch S8, and a ninth switch S9. The control logic circuit is further configured to control the on / off switching of the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, and the ninth switch S9, respectively.

[0057] The internal circuit connection relationship of the output matching network 4 is:

[0058] The first end of the fifth capacitor C5 serves as the input end of the first output matching circuit 41, and the first end of the fifth capacitor C5 is respectively connected to the first end of the third resistor R3, the first end of the sixth capacitor C6, and the first end of the eighth capacitor C8. The second end of the third resistor R3 is connected to the first end of the fifth switch S5, and the second end of the fifth switch S5 is grounded to GND. The second end of the sixth capacitor C6 is connected to the first end of the sixth switch S6, and the second end of the sixth switch S6 is grounded to GND.

[0059] The second end of the fifth capacitor C5 is connected to the second end of the seventh switch S7. The first end of the seventh switch S7 serves as the output end of the first output matching circuit 41, and the first end of the seventh switch S7 is connected to the first end of the seventh capacitor C7. The first end of the seventh capacitor C7 serves as the input end of the second output matching circuit 42.

[0060] The second end of the seventh capacitor C7 is connected to the first end of the eighth switch S8 , the second end of the eighth switch S8 serves as the output end of the second output matching circuit 42 , and the second end of the eighth switch S8 is connected to the first end of the ninth switch S9 .

[0061] A second end of the ninth switch S9 is connected to a second end of the eighth capacitor C8 .

[0062] In this embodiment, the node where the first output matching circuit 41, the second output matching circuit 42, and the third switch S3 are interconnected is connected in a Y-type connection. Of course, the present invention is not limited to this. In another embodiment, the node where the first output matching circuit 41, the second output matching circuit 42, and the third switch S3 are interconnected is connected in a Δ-type connection, that is, in another embodiment, the first output matching circuit 41 and the second output matching circuit 42 can be combined.

[0063] The output resistance attenuation network 5 includes a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a ninth capacitor C9, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The eleventh switch S11, the twelfth switch S12, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 form a resistance attenuation network to achieve a resistance attenuation function. The tenth switch S10 and the twelfth switch S12 are turned on in the amplification mode and turned off in the bypass mode; the eleventh switch S11 is turned off in the amplification mode and turned on in the bypass mode. The control logic circuit is further configured to control the on / off switching actions of the tenth switch S10, the eleventh switch S11, and the twelfth switch S12, respectively.

[0064] The internal circuit connection relationship of the output resistance attenuation network 5 is:

[0065] The first end of the fourth resistor R4 serves as the first end of the output resistance attenuation network 5 , and the first end of the fourth resistor R4 is respectively connected to the first end of the twelfth switch S12 and the first end of the ninth capacitor C9 .

[0066] A second end of the ninth capacitor C9 is connected to a first end of the tenth switch S10 . A second end of the tenth switch S10 is grounded GND.

[0067] The second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5 and the first end of the sixth resistor R6 respectively.

[0068] The second end of the fifth resistor R5 serves as the second end of the output resistance attenuation network 5 , and the second end of the fifth resistor R5 is connected to the second end of the twelfth switch S12 .

[0069] The second end of the sixth resistor R6 is connected to the first end of the eleventh switch S11 .

[0070] The second end of the eleventh switch S11 serves as the third end of the output resistance attenuation network 5 , and the second end of the eleventh switch S11 is grounded GND.

[0071] The circuit connection relationship of the low noise amplifier 100 is:

[0072] The signal input terminal RFin is connected to a first terminal of the first inductor L1 , and a second terminal of the first inductor L1 is connected to a first terminal of the first switch S1 and a first terminal of the second switch S2 .

[0073] The second end of the first switch S1 is connected to the input end of the bypass matching circuit 2 and the first end of the fourth switch S4 respectively. The second end of the fourth switch S4 is grounded GND.

[0074] The output end of the bypass matching circuit 2 is connected to the first end of the third switch S3. The second end of the third switch S3 is connected to the output end of the first output matching circuit 41 and the input end of the second output matching circuit 42 respectively.

[0075] A second end of the second switch S2 is connected to a first end of the first capacitor C1 . A second end of the first capacitor C1 is connected to a gate of the first transistor M1 .

[0076] The source of the first transistor M1 is connected to the first end of the second inductor L2. The second end of the second inductor L2 is connected to the first end of the transistor bias circuit 3. The second end of the transistor bias circuit 3 is grounded GND. The third end of the transistor bias circuit 3 is connected to the output of the external control logic circuit.

[0077] The drain of the first transistor M1 is connected to the source of the second transistor M2 , and the gate of the second transistor M2 is grounded GND.

[0078] The drain of the second transistor M2 is connected to the input terminal of the first output matching circuit 41 and the first terminal of the third inductor L3 respectively. The second terminal of the third inductor L3 is used to be connected to the power supply voltage VDD.

[0079] The output terminal of the second output matching circuit 42 is connected to the first terminal of the output resistance attenuation network 5. The second terminal of the output resistance attenuation network 5 is connected to the signal output terminal RFout. The third terminal of the output resistance attenuation network 5 is grounded GND.

[0080] In this embodiment, the low-noise amplifier 100 further includes a third capacitor C3. A first end of the third capacitor C3 is connected to the gate of the second transistor M2. A second end of the third capacitor C3 is grounded to GND. The third capacitor C3 isolates the gate of the second transistor M2 from direct current, thereby ensuring stable operation of the second transistor M2.

[0081] In this embodiment, the low-noise amplifier 100 further includes a first resistor R1. A first end of the first resistor R1 is connected to the gate of the first transistor M1. A second end of the first resistor R1 is connected to a first bias voltage Vb1. Connecting the first bias voltage Vb1 through the first resistor R1 allows the first bias voltage Vb1 to be stepped down by the first resistor R1 and then output to the gate of the first transistor M1, resulting in high overall circuit stability.

[0082] In this embodiment, the low-noise amplifier 100 further includes a second resistor R2. A first end of the second resistor R2 is connected to the gate of the second transistor M2. A second end of the second resistor R2 is connected to a second bias voltage Vb2. Connecting the second bias voltage Vb2 via the second resistor R2 allows the second bias voltage Vb2 to be stepped down by the second resistor R2 and then output to the gate of the second transistor M2, resulting in high overall circuit stability.

[0083] The working principle of the low noise amplifier 100 is:

[0084] The RF signal input from the signal input terminal RFin enters through the first inductor L1. When the low-noise amplifier 100 operates in amplification mode, the first switch S1 and the third switch S3 are disconnected; the second switch S2 and the fourth switch S4 are turned on, and the gate of the third transistor M3 is set to a high level, enabling the cascode amplifier of the cascode low-noise amplifier chain 1 to operate normally. The signal is input to the first transistor M1, which functions as a common-source amplifier, via the first capacitor C1, which functions as a DC blocking capacitor. After being amplified by the first transistor M1, the signal is amplified by the second transistor M2, which functions as a common-gate amplifier, and then output. The third inductor L3, which functions as an RF choke inductor, provides a DC operating point and forces the RF signal to enter the first output matching circuit 41 and the second output matching circuit 42. Finally, the signal reaches the signal output terminal RFout through the output resistor attenuation network 5.

[0085] When the low-noise amplifier 100 operates in bypass mode, the first switch S1 and the third switch S3 are turned on, while the second switch S2 and the fourth switch S4 are turned off. The gate of the third transistor M3 is set to a low level, disconnecting the cascode amplifier circuit of the cascode low-noise amplifier chain 1 and reducing the parasitic capacitance to ground after the first inductor L1. The RF signal is input into the bypass matching circuit 2 via the first inductor L1. After bypass matching by the bypass matching circuit 2, the first output matching circuit 41 operates in bypass mode and resonates with the third inductor L3, creating a low impedance point at a low frequency. This achieves filtering for a specific frequency band. For example, a 5 GHz WiFi receive path suppresses the 2.4 GHz WiFi band. Within the operating frequency band, the series connection of the first output matching circuit 41 and the third inductor L3 is equivalent to an inductor to ground. Finally, after passing through the second output matching circuit 42, the output impedance is converted to a predetermined target output impedance, thereby reducing return loss. The signal is then output through the output resistor attenuation network 5 and the signal output terminal RFout.

[0086] Please refer to Figure 3 As shown, Figure 3 This is an equivalent circuit diagram of the bypass mode of the low-noise amplifier 100 according to an embodiment of the present invention. The branch formed by the fifth capacitor C5 and the third inductor L3 presents a low impedance in the suppression frequency band and an inductive impedance in the operating frequency band. This provides a bypass path that suppresses a fixed low frequency point while conducting current in the operating frequency band.

[0087] Specifically, when the low-noise amplifier 100 operates in the amplification mode, the first switch S1, the third switch S3, the seventh switch S7, the eighth switch S8, and the eleventh switch S11 are all disconnected, while the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6, the ninth switch S9, the tenth switch S10, and the twelfth switch S12 are all turned on. The first bias voltage Vb1 and the second bias voltage Vb2 are normally output to provide correct bias voltages for the first transistor M1 and the second transistor M2. The gate of the third transistor M3 is set to a high level to enable the first transistor M1 and the second transistor M2 to operate normally. The RF signal reaches the gate of the first transistor M1 via the first inductor L1 and the first capacitor C1, and is amplified by the first transistor M1 serving as a common-source amplifier, and then amplified again by the second transistor M2 serving as a common-gate amplifier. The second inductor L2, serving as a source-level negative feedback inductor, provides the real part of the input impedance as part of the input matching. The third inductor L3, third resistor R3, sixth capacitor C6, seventh capacitor C7, and ninth capacitor C9, serving as the RF choke inductor, together form the output matching, transmitting the signal from the drain of the second transistor M2 to the signal output terminal RFout.

[0088] When the low-noise amplifier 100 operates in the bypass mode, the first switch S1, the third switch S3, the seventh switch S7, the eighth switch S8, and the eleventh switch S11 are all turned on, while the second switch S2, the fourth switch S4, the fifth switch S5, the sixth switch S6, the ninth switch S9, the tenth switch S10, and the twelfth switch S12 are all turned off. The first bias voltage Vb1 and the second bias voltage Vb2 are set to a low level, and the gate of the third transistor M3 is set to a low level, turning off the cascode low-noise amplifier chain 1. At this time, the first transistor M1 and the second transistor M2 enter the cut-off region, and the input signal sequentially passes through the first inductor L1 and the second capacitor C2 to reach the middle node between the seventh switch S7 and the seventh capacitor C7. The fifth capacitor C5 and the third inductor L3 together form an LC series resonant branch. The resonant frequency is set in the out-of-band suppression frequency band, and the inductance behaves as an inductor in the passband. Finally, the signal is output to the signal output terminal RFout via the seventh capacitor C7.

[0089] In order to verify the performance of the bypass mode of the low noise amplifier 100, a simulation comparison is performed with the performance of the bypass mode of the low noise amplifier of the related art. Figures 4 and 5 As shown, Figure 4 is a graph showing the relationship between S21 and frequency in the bypass mode of a low noise amplifier in the related art; Figure 5 FIG. 4 is a graph showing the relationship between S21 and frequency in the bypass mode of the low noise amplifier 100 according to an embodiment of the present invention. S21 is the insertion loss, in dB.

[0090] Figure 4The curve in the figure is the insertion loss curve of the low noise amplifier of the related art when it is configured in bypass mode at 5-6GHz. The value of point A1 is 2.45GHZ, -20.0452dB. The value of point A2 is 5.5GHZ, -2.30987dB. Figure 4 It can be obtained that the passband attenuation of the low noise amplifier in the related art is about 2.3-2.7dB, and the attenuation in the 2.4-2.5GHz frequency band is about 20dB.

[0091] Figure 5 The curve in FIG is the insertion loss curve of the low noise amplifier of the present invention when it is configured in bypass mode at 5-6 GHz. The value at point A3 is 2.45 GHZ, -35.8599 dB. The value at point A4 is 5.5 GHZ, -2.75073 dB. Figure 5 It can be obtained that the passband attenuation is between about 2.7-3.4dB, and the attenuation in the 2.4-2.5GHz frequency band is about 35dB. It can be seen that the low-noise amplifier of the present invention provides an additional 15dB out-of-band interference suppression capability based on the low-noise amplifier in the related art, which can greatly improve the anti-interference ability and high sensitivity.

[0092] An embodiment of the present invention further provides a radio frequency chip, which includes the low noise amplifier 100 .

[0093] The radio frequency chip provided in the embodiment of the present invention can realize various implementations and corresponding beneficial effects in the embodiment of the low noise amplifier 100, which will not be described again here to avoid repetition.

[0094] It should be pointed out that the relevant circuit modules, resistors, capacitors, inductors and transistors used in the present invention are all commonly used circuit modules and components in this field. The corresponding specific indicators and parameters are adjusted according to actual applications and are not described in detail here.

[0095] Compared to related art, the low-noise amplifier and RF chip of the present invention are provided with a cascode low-noise amplifier link including a source-level negative feedback inductor, a first switch, a second switch, a third switch, a fourth switch, a transistor bias access circuit, and a bypass matching circuit; by connecting the bypass matching circuit to both ends of the cascode low-noise amplifier link, and controlling the on / off of the bypass matching circuit by turning on or off the transistor bias access circuit, the first switch, the second switch, the third switch, and the fourth switch, multiple bypass mode functions and amplification mode functions are achieved, resulting in low return loss at the operating frequency of the low-noise amplifier and high reliability. In addition, the low-noise amplifier and RF chip of the present invention are provided with a first output matching circuit for filtering a single frequency band and a second output matching circuit for converting the output impedance to a preset target output impedance; the first output matching circuit generates a low impedance point at a low frequency, thereby achieving filtering of a single frequency band, for example, achieving channel suppression of the 2.4 GHz WiFi band in the 5 GHz WiFi receiving path, effectively achieving out-of-band narrowband suppression of a single frequency band. More preferably, within the operating frequency band, after the signal passes through the first output matching circuit and the second output matching circuit in sequence, the output impedance is converted to a preset target output impedance, so that the low-noise amplifier and the radio frequency chip of the present invention reduce the return loss, thereby making the low-noise amplifier and the radio frequency chip of the present invention have strong anti-interference ability and high sensitivity.

[0096] It should be noted that the various embodiments described above with reference to the accompanying drawings are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Those skilled in the art should understand that any modifications or equivalent substitutions to the present invention that do not depart from the spirit and scope of the present invention are intended to be encompassed within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include the plural form, and vice versa. Furthermore, unless otherwise specified, all or part of any embodiment may be used in combination with all or part of any other embodiment.

Claims

1. A low-noise amplifier comprising a signal input terminal, a common-source and common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, and a signal output terminal connected in sequence, characterized in that: The low-noise amplifier further includes a first switch, a third switch, a fourth switch, a bypass matching circuit, and a transistor bias access circuit; the output matching network includes a first output matching circuit for implementing filtering of a separate frequency band and a second output matching circuit for converting the output impedance to a preset target output impedance; the cascode low-noise amplifier link includes a first inductor, a second switch, a first capacitor, a first transistor, a second transistor, a second inductor, and a third inductor; The signal input terminal is connected to the first terminal of the first inductor; the second terminal of the first inductor is connected to the first terminal of the first switch and the first terminal of the second switch respectively; The second end of the first switch is connected to the input end of the bypass matching circuit and the first end of the fourth switch respectively; the second end of the fourth switch is grounded; The output end of the bypass matching circuit is connected to the first end of the third switch; the second end of the third switch is connected to the output end of the first output matching circuit and the input end of the second output matching circuit respectively; The second end of the second switch is connected to the first end of the first capacitor; the second end of the first capacitor is connected to the gate of the first transistor; The source of the first transistor is connected to the first end of the second inductor; the second end of the second inductor is connected to the first end of the transistor bias access circuit; the second end of the transistor bias access circuit is grounded; the third end of the transistor bias access circuit is used to connect to an external control logic circuit, and the control logic circuit is used to control the operations of the transistor bias access circuit, the first switch, the second switch, the third switch, and the fourth switch respectively; The drain of the first transistor is connected to the source of the second transistor; the gate of the second transistor is grounded; The drain of the second transistor is connected to the input terminal of the first output matching circuit and the first terminal of the third inductor respectively; the second terminal of the third inductor is used to be connected to the power supply voltage; The output end of the second output matching circuit is connected to the first end of the output resistance attenuation network; the second end of the output resistance attenuation network is connected to the signal output end; and the third end of the output resistance attenuation network is grounded.

2. The low noise amplifier according to claim 1, wherein The low noise amplifier further includes a third capacitor; a first end of the third capacitor is connected to the gate of the second transistor; and a second end of the third capacitor is grounded.

3. The low noise amplifier according to claim 2, wherein: The low noise amplifier further includes a second resistor; a first end of the second resistor is connected to the gate of the second transistor; and a second end of the second resistor is used to be connected to a second bias voltage.

4. The low noise amplifier according to claim 1, wherein: The low noise amplifier further includes a first resistor; a first end of the first resistor is connected to the gate of the first transistor; and a second end of the first resistor is used to be connected to a first bias voltage.

5. The low noise amplifier according to claim 1, wherein: The bypass matching circuit includes a second capacitor; a first end of the second capacitor serves as an input end of the bypass matching circuit, and a second end of the second capacitor serves as an output end of the bypass matching circuit.

6. The low noise amplifier according to claim 1, wherein: The first output matching circuit includes a third resistor, a fifth capacitor, a sixth capacitor, a fifth switch, a sixth switch, and a seventh switch; the second output matching circuit includes a seventh capacitor, an eighth capacitor, an eighth switch, and a ninth switch; The first end of the fifth capacitor serves as an input end of the first output matching circuit, and the first end of the fifth capacitor is respectively connected to the first end of the third resistor, the first end of the sixth capacitor, and the first end of the eighth capacitor; the second end of the third resistor is connected to the first end of the fifth switch, and the second end of the fifth switch is grounded; the second end of the sixth capacitor is connected to the first end of the sixth switch, and the second end of the sixth switch is grounded; The second end of the fifth capacitor is connected to the second end of the seventh switch; the first end of the seventh switch serves as the output end of the first output matching circuit, and the first end of the seventh switch is connected to the first end of the seventh capacitor; the first end of the seventh capacitor serves as the input end of the second output matching circuit; The second end of the seventh capacitor is connected to the first end of the eighth switch; the second end of the eighth switch serves as the output end of the second output matching circuit, and the second end of the eighth switch is connected to the first end of the ninth switch; The second end of the ninth switch is connected to the second end of the eighth capacitor.

7. The low noise amplifier according to claim 6, wherein: The output resistance attenuation network includes a tenth switch, an eleventh switch, a twelfth switch, a ninth capacitor, a fourth resistor, a fifth resistor, and a sixth resistor; The first end of the fourth resistor serves as the first end of the output resistance attenuation network, and the first end of the fourth resistor is connected to the first end of the twelfth switch and the first end of the ninth capacitor respectively; The second end of the ninth capacitor is connected to the first end of the tenth switch; the second end of the tenth switch is grounded; The second end of the fourth resistor is connected to the first end of the fifth resistor and the first end of the sixth resistor respectively; The second end of the fifth resistor serves as the second end of the output resistance attenuation network, and the second end of the fifth resistor is connected to the second end of the twelfth switch; The second end of the sixth resistor is connected to the first end of the eleventh switch; The second end of the eleventh switch serves as the third end of the output resistance attenuation network, and the second end of the eleventh switch is grounded.

8. The low noise amplifier according to claim 1, wherein: The transistor bias access circuit includes a third transistor; the source of the third transistor serves as the second end of the transistor bias access circuit; the drain of the third transistor serves as the first end of the transistor bias access circuit; and the gate of the third transistor serves as the third end of the transistor bias access circuit.

9. The low noise amplifier according to claim 8, wherein: The first transistor, the second transistor and the third transistor are all NMOS transistors.

10. A radio frequency chip, characterized in that: The radio frequency chip includes the low noise amplifier according to any one of claims 1 to 9.

Images