Data transmission system and data transmission method

Abstract

The application provides a data transmission system and a data transmission method, a first control module is used for framing a first sideband electrical signal, converting into a first differential signal and encrypted transmission, and transmitting to a PCIe remote device through two optical modules and a second control module; the second control module is used for framing a second sideband electrical signal, converting into a second differential signal and encrypted transmission, and transmitting to a PCIe host device through two optical modules and the first control module; the PCIe host device and the PCIe remote device transmit data signals to each other through a first switching module, two optical modules and a second switching module. In the system, the first sideband electrical signal and the second sideband electrical signal can be transmitted at the same time when the data signal is transmitted, and the first sideband electrical signal, the second sideband electrical signal and the data signal can share the first optical module and the second optical module, so that the occupied area of the PCB is smaller, and additional hardware is not needed, thereby reducing the hardware cost.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data transmission system and a data transmission method. Background Art

[0002] PCIe (Peripheral Component Interconnect express) is a point-to-point high-speed transmission bus. Usually, the PCIe bus is connected through PCB routing or through an external coaxial cable. It includes other low-speed sideband signals such as reset signal (PERST#) and wake-up signal (WAKE#). The transmission of the reset signal can ensure that the devices at both ends of the PCIe link can be reset synchronously, and the wake-up signal can achieve remote wake-up. These signals are very valuable. In the related technology, SFP+ optical modules can be used to realize PCIe data transmission and reset signal transmission, but wake-up signals cannot be transmitted. QSFP+ optical modules can also be used to transmit PCIe data signals, but reset signals and wake-up signals cannot be transmitted. Moreover, if PCIe x4 or PCIe x8 is to be implemented and other sideband signals such as reset signals and wake-up signals need to be transmitted, multiple SFP+ optical modules or multiple QSFP+ optical modules are required, which occupy a large area of ​​PCB and require the addition of related hardware, increasing hardware costs. Summary of the Invention

[0003] The object of the present invention is to provide a data transmission system and a data transmission method, so as to simultaneously transmit data signals and other sideband signals such as reset signals and wake-up signals without increasing the PCB occupied area and hardware cost.

[0004] The present invention provides a data transmission system, comprising: a PCIe master device, a first control module, a first optical module and a second optical module for transmitting multi-channel signals, a second control module, and a PCIe remote device connected in sequence; the PCIe master device is communicatively connected to the first optical module via a first switching module; the PCIe remote device is communicatively connected to the second optical module via a second switching module; the first control module is used to frame a first sideband electrical signal from the PCIe master device, and then convert the first sideband electrical signal into a first differential signal and encrypt it for transmission, and send it to the second control module in sequence through the first optical module and the second optical module; the second control module is used to parse the encrypted first differential signal and send the parsed first sideband electrical signal to the second control module. The first optical module is used to transmit the encrypted second differential signal to the PCIe master device, thereby controlling the PCIe master device to execute the action corresponding to the first sideband electrical signal. The second control module is used to frame the second sideband electrical signal from the PCIe remote device, and then convert the second sideband electrical signal into a second differential signal and encrypt it for transmission, which is then sent to the first control module via the second optical module and the first optical module in sequence. The first control module is used to parse the encrypted second differential signal and send the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to execute the action corresponding to the second sideband electrical signal. The PCIe master device and the PCIe remote device transmit data signals to each other through the first switching module, the first optical module, the second optical module, and the second switching module.

[0005] Furthermore, the first sideband electrical signal is a reset electrical signal; the first control module is used to frame the reset electrical signal from the PCIe master device according to a preset protocol; and / or, the second sideband electrical signal is a wake-up electrical signal; the second control module is used to frame the wake-up electrical signal from the PCIe remote device according to a preset protocol.

[0006] Furthermore, the first optical module is used to convert the received framed reset electrical signal into a reset optical signal, and send the reset optical signal to the second optical module via the optical fiber; the second optical module is used to convert the reset optical signal into a framed reset electrical signal, and send the framed reset electrical signal to the second control module; and / or, the second optical module is used to convert the received framed wake-up electrical signal into a wake-up optical signal, and send the wake-up optical signal to the first optical module via the optical fiber; the first optical module is used to convert the wake-up optical signal into a framed wake-up electrical signal, and send the framed wake-up electrical signal to the first control module.

[0007] Furthermore, the second control module is also used to parse the reset electrical signal after framing, and send the resolved reset electrical signal to the PCIe remote device to reset the PCIe remote device; when the reset time of the PCIe remote device reaches a preset time, the PCIe remote device is de-reset; wherein, the de-reset time of the PCIe remote device is controlled by the second control module.

[0008] Furthermore, the first switching module is used to preprocess the data electrical signal obtained from the PCIe master device and send the preprocessed data electrical signal to the first optical module; the first optical module is used to convert the received preprocessed data electrical signal into a data optical signal and send the data optical signal to the second optical module through the optical fiber; the second optical module is used to convert the data optical signal into a preprocessed data electrical signal and send it to the PCIe remote device through the second switching module.

[0009] Furthermore, the first control module includes a first framing module, a first mode conversion module and a first parsing module; the second control module includes a second framing module, a second mode conversion module and a second parsing module; the first framing module is used to frame and encrypt the first sideband electrical signal from the PCIe master device to obtain the encrypted first framing signal, and send the encrypted first framing signal to the first mode conversion module; the first mode conversion module is used to convert the encrypted first framing signal from the current parallel mode to the serial mode to obtain the encrypted first differential signal; and is also used to receive the encrypted second differential signal, convert the encrypted second differential signal from the current serial mode to the parallel mode to obtain the encrypted second framing signal, and send the encrypted second framing signal to the first parsing module; the The first parsing module is used to parse the encrypted second frame signal to obtain the second sideband electrical signal; the second framing module is used to frame and encrypt the second sideband electrical signal from the PCIe remote device to obtain the encrypted second frame signal, and send the encrypted second frame signal to the second mode conversion module; the second mode conversion module is used to convert the encrypted second frame signal from the current parallel mode to the serial mode to obtain the encrypted second differential signal; it is also used to receive the encrypted first differential signal, convert the encrypted first differential signal from the current serial mode to the parallel mode to obtain the encrypted first frame signal, and send the encrypted first frame signal to the second parsing module; the second parsing module is used to parse the encrypted first frame signal to obtain the first sideband electrical signal.

[0010] The present invention provides a data transmission method, which includes: framing a received first sideband electrical signal, converting the first sideband electrical signal into a first differential signal and encrypting it for transmission; sending the signal to a PCIe remote device via a first optical module and a second optical module in sequence; receiving and parsing the encrypted second differential signal sent by the PCIe remote device to obtain a second sideband electrical signal; and sending the second sideband electrical signal to a PCIe master device to control the PCIe master device to execute an action corresponding to the second sideband electrical signal.

[0011] The present invention provides a data transmission method, which includes: receiving and parsing an encrypted first differential signal sent by a PCIe master device to obtain a first sideband electrical signal; sending the first sideband electrical signal to a PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; framing the received second sideband electrical signal, and then converting the second sideband electrical signal into a second differential signal and encrypting it for transmission; and sending the second sideband electrical signal to the PCIe master device via a second optical module and a first optical module in sequence.

[0012] Furthermore, the first sideband electrical signal is a reset electrical signal; the method also includes: parsing the reset electrical signal after framing, and sending the reset electrical signal obtained by parsing to the PCIe remote device to reset the PCIe remote device; when the reset time of the PCIe remote device reaches a preset time, the PCIe remote device is reset.

[0013] The present invention provides a data transmission method, which includes: a first control module framing a first sideband electrical signal from a PCIe master device, further converting the first sideband electrical signal into a first differential signal and encrypting the signal for transmission, which is then sent to a second control module via a first optical module and a second optical module in sequence; a second control module parsing the encrypted first differential signal and sending the parsed first sideband electrical signal to a PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; a second control module framing a second sideband electrical signal from the PCIe remote device, further converting the second sideband electrical signal into a second differential signal and encrypting the signal for transmission, which is then sent to the first control module via a second optical module and a first optical module in sequence; the first control module parsing the encrypted second differential signal and sending the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to perform an action corresponding to the second sideband electrical signal; and data signals are transmitted between the PCIe master device and the PCIe remote device via the first switching module, the first optical module, the second optical module, and the second switching module.

[0014] Furthermore, the first sideband electrical signal is a reset electrical signal; the second sideband electrical signal is a wake-up electrical signal; and framing is to encode the collected first sideband electrical signal or the second sideband electrical signal and add a header and a tail.

[0015] The data transmission system and data transmission method provided by the present invention include a first control module for framing a first sideband electrical signal from a PCIe master device, converting the first sideband electrical signal into a first differential signal and encrypting the signal for transmission, which is then sent to a second control module via a first optical module and a second optical module in sequence; a second control module for parsing the encrypted first differential signal and sending the parsed first sideband electrical signal to a PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; a second control module for framing a second sideband electrical signal from the PCIe remote device, converting the second sideband electrical signal into a second differential signal and encrypting the signal for transmission, which is then sent to the first control module via a second optical module and a first optical module in sequence; the first control module for parsing the encrypted second differential signal and sending the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to perform an action corresponding to the second sideband electrical signal; and data signals are transmitted between the PCIe master device and the PCIe remote device via the first switching module, the first optical module, the second optical module, and the second switching module. In this system, a first sideband electrical signal and a second sideband electrical signal can be transmitted simultaneously with a data signal, and the first sideband electrical signal, the second sideband electrical signal and the data signal can share a first optical module and a second optical module. Therefore, a smaller area is occupied on the PCB, and no additional hardware is required, thereby reducing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic structural diagram of a data transmission system provided by an embodiment of the present invention;

[0018] Figure 2 A PCIe x8 fiber optic communication CXP interface diagram provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a functional module provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of PCIe x8 optical fiber communication based on a CXP optical module provided in an embodiment of the present invention;

[0021] Figure 5 A reset transmission timing diagram provided by an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of the internal functional block diagram of a switching module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical solutions of the present invention are described clearly and completely below with reference to the embodiments. It is obvious that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are also within the scope of protection of the present invention.

[0024] Currently, PCIe is a point-to-point high-speed transmission bus. Usually, the PCIe bus is connected through PCB traces or external coaxial cables. It includes differential data lines, reset signals (PERST#), wake-up signals (WAKE#), SMBUS (optional signal), and other low-speed sideband signals. The transmission of reset signals can ensure that devices at both ends of the PCIe link can be reset synchronously, and the WAKE# signal can achieve remote wake-up. These signals are also very valuable.

[0025] The existing technology uses two methods to achieve this:

[0026] 1. The existing technology can only use SFP+ optical modules to transmit reset signals, but not wake-up signals (WAKE# signals). Furthermore, there is a problem with reset signal transmission delay. The reset signal validity period of the PCIe device is exactly the same as the motherboard reset signal. The effective time of the reset can only be synchronized or delayed, not advanced. This may cause the PCIe host device to have already released the reset and started scanning for PCIe EP devices, while the PCIe EP devices have not yet completed reset and initialization, resulting in the PCIe EP devices not being scanned. Furthermore, for multi-channel transmission that requires reset signal transmission (such as PCIe x4 or PCIex8), the PCB area occupied is too large.

[0027] 2. Adding other external hardware to implement the transmission of other signals such as the reset signal PERST# and the wake-up signal WAKE# also has the problem of occupying too much PCB area.

[0028] None of the existing solutions involve the wake-up signal WAKE#. In low-power design scenarios, the PCIe host needs to sleep and the main power supply is turned off to save power. Since the PCIe device cannot detect the WAKE# signal, it cannot wake up the PCIe host device.

[0029] Based on this, an embodiment of the present invention provides a data transmission system and a data transmission method. This technology can be applied to scenarios where PCIe signal and sideband signal transmission need to be implemented.

[0030] To facilitate understanding of this embodiment, a data transmission system disclosed in an embodiment of the present invention is first described in detail; Figure 1 As shown, it includes: a PCIe main device 10, a first control module 11, a first optical module 12 and a second optical module 13 for transmitting multiple signals, a second control module 14 and a PCIe remote device 15 connected in sequence; the PCIe main device 10 is communicated with the first optical module 12 via a first switching module 16; the PCIe remote device 15 is communicated with the second optical module 13 via a second switching module 17; the first control module 11 is used to frame the first sideband electrical signal from the PCIe main device 10, and then convert the first sideband electrical signal into a first differential signal and encrypt it for transmission, and send it to the second control module 14 in sequence through the first optical module 12 and the second optical module 13; the second control module 14 is used to parse the encrypted first differential signal and send the parsed first sideband electrical signal to the PCIe main device 10. Ie remote device 15, to control the PCIe remote device 15 to perform the action corresponding to the first sideband electrical signal; the second control module 14 is used to frame the second sideband electrical signal from the PCIe remote device 15, and then convert the second sideband electrical signal into a second differential signal and encrypt it for transmission, and send it to the first control module 11 via the second optical module 13 and the first optical module 12 in sequence; the first control module 11 is used to parse the encrypted second differential signal, and send the parsed second sideband electrical signal to the PCIe main device 10 to control the PCIe main device 10 to perform the action corresponding to the second sideband electrical signal; the PCIe main device 10 and the PCIe remote device 15 transmit data signals to each other through the first switching module 16, the first optical module 12, the second optical module 13 and the second switching module 17.

[0031] The first control module 11, the first optical module 12 and the first switching module 16 are components on the PCIe master device 10 side; the second optical module 13, the second control module 14 and the second switching module 17 are components on the PCIe remote device 15 side; the first sideband electrical signal can be understood as other management signals other than data signals sent by the PCIe master device 10 to the PCIe remote device 15, such as a reset signal; in actual implementation, the PCIe master device 10 can send a first sideband electrical signal, collect the first sideband electrical signal through the first control module 11, and frame the collected first sideband electrical signal and encrypt it for transmission. The frame can be understood as encoding the collected first sideband electrical signal and adding a header and a tail to encapsulate it into a frame. Specifically, the first sideband electrical signal can be converted into a first differential signal and encrypted for transmission; the first control module 11 sends the encrypted first differential signal to the second control module 14 through the first optical module 12 and the second optical module 13. The second control module 14 can parse the received encrypted first differential signal to obtain the first sideband electrical signal and send it to the PCIe remote device 15. Through this process, the transmission of the first sideband electrical signal can be completed, and the PCIe remote device 15 performs corresponding actions based on the received first sideband electrical signal.

[0032] The above-mentioned second sideband electrical signal can be understood as other management signals, such as a wake-up signal, sent by the PCIe remote device 15 to the PCIe master device 10. In actual implementation, the PCIe remote device 15 can send a second sideband electrical signal, which is collected by the second control module 14, and the collected second sideband electrical signal is framed and encrypted for transmission. The framing can be understood as encoding the collected second sideband electrical signal and adding a header and a trailer to encapsulate it into a frame. Specifically, the second sideband electrical signal can be converted into a second differential signal and encrypted for transmission. The second control module 14 sends the encrypted second differential signal to the first control module 11 through the second optical module 13 and the first optical module 12. The first control module 11 can parse the received encrypted second differential signal to obtain a second sideband electrical signal and send it to the PCIe master device 10. Through this process, the transmission of the second sideband electrical signal can be completed, and the PCIe master device 10 performs corresponding actions based on the received second sideband electrical signal.

[0033] In this embodiment, the first control module 11 and the second control module 14 are Field Programmable Gate Arrays (FPGAs). However, those skilled in the art will appreciate that the first control module 11 and the second control module 14 are not limited to FPGAs, as long as they can frame the received first sideband electrical signal or the second sideband electrical signal and parse the framed first sideband electrical signal or the framed second sideband electrical signal. The first optical module 12 and the second optical module 13 can be CXP optical modules, or other types of optical modules, as long as they can transmit multiple signals.

[0034] The following takes the implementation of PCIe x8 as an example. Figure 2 The figure shows a CXP interface diagram for PCIe x8 optical fiber communication. There are 12 pairs of full-duplex differential lanes inside the CXP optical module. Eight pairs of lanes can be used to achieve PCIe physical channel x8 connection. According to the CXP specification, the signal attenuation of the middle lane is smaller than that of the outer lanes. For applications that do not use 12 lanes, the middle lane can be used as the priority. Therefore, lanes 2 to 9 can be selected to transmit PCIe data. Each pair of lanes supports QDR (Quad Data Rate) with a rate of up to 10Gbps. Some CXP optical modules support a wide range of rates, from 1Gbps to 12Gbps. Therefore, using one CXP optical module can fully meet the bandwidth requirements of PCIe Gen3 x8, that is, using one CXP optical module can complete PCIe x8 data communication. The first sideband electrical signal, the second sideband electrical signal, and the PCIe data signal share the CXP optical module. Specifically, they can use any one of lanes 0, lane 1, lane 10, and lane 11 in the CXP optical module for transmission. In this way, both the master device and the remote device only need to use lanes 2 to 9 in one CXP optical module to complete PCIe Gen3 x8 bus data communication, saving single-board area.

[0035] In the above-mentioned data transmission system, the first control module 11 is used to frame the first sideband electrical signal from the PCIe master device 10, and then convert the first sideband electrical signal into a first differential signal and encrypt it for transmission, and then send it to the second control module 14 through the first optical module 12 and the second optical module 13 in sequence; the second control module 14 is used to parse the encrypted first differential signal and send the parsed first sideband electrical signal to the PCIe remote device 15 to control the PCIe remote device 15 to perform the action corresponding to the first sideband electrical signal; the second control module 14 is used to parse the second sideband electrical signal from the PCIe remote device 15 The electrical signal is framed, and the second sideband electrical signal is converted into a second differential signal and encrypted for transmission, which is then sent to the first control module 11 via the second optical module 13 and the first optical module 12. The first control module 11 is used to parse the encrypted second differential signal and send the parsed second sideband electrical signal to the PCIe master device 10 to control the PCIe master device 10 to perform the action corresponding to the second sideband electrical signal. Data signals are transmitted between the PCIe master device 10 and the PCIe remote device 15 via the first switching module 16, the first optical module 12, the second optical module 13, and the second switching module 17. In this system, the first sideband electrical signal and the second sideband electrical signal can be transmitted simultaneously with the data signal, and the first sideband electrical signal, the second sideband electrical signal, and the data signal can share the first optical module and the second optical module. Therefore, the PCB area occupied is small, and no additional hardware is required, thereby reducing hardware costs.

[0036] Furthermore, the first sideband electrical signal is a reset electrical signal; the first control module 11 is used to frame the reset electrical signal from the PCIe master device 10 according to a preset protocol; and / or, the second sideband electrical signal is a wake-up electrical signal; the second control module 14 is used to frame the wake-up electrical signal from the PCIe remote device 15 according to a preset protocol.

[0037] In actual implementation, the PCIe master device 10 can send a single-ended reset electrical signal (i.e., the above-mentioned reset electrical signal), the first control module 11 collects the single-ended reset electrical signal, and frames the single-ended reset electrical signal according to some commonly used protocols, such as the Aurora protocol; wherein the Aurora protocol is a scalable lightweight link layer protocol for moving data between point-to-point serial links.

[0038] The PCIe remote device 15 can send a wake-up electrical signal, and the second control module 14 collects the wake-up electrical signal and frames the wake-up electrical signal according to some commonly used protocols, such as the Aurora protocol. In actual implementation, since each pair of Serdes lanes in the CXP optical module includes both a sending interface and a receiving interface, the CXP optical module on the PCIe remote device side can use the sending interface to send the framed wake-up electrical signal to the first control module 11 on the PCIe master device 10 side while receiving the reset differential data.

[0039] Preferably, the first control module 11 and the second control module 14 both use FPGA. After the reset / WAKE# signal (corresponding to the above-mentioned reset electrical signal / wake-up electrical signal) is framed by FPGA, it is transmitted through the CXP optical module and optical fiber, which can greatly reduce the reset / WAKE# transmission delay. In addition, the reset time of the PCIe remote device can be controlled by the corresponding FPGA, and the application is more flexible.

[0040] Furthermore, the first optical module 12 is used to convert the received framed reset electrical signal into a reset optical signal, and send the reset optical signal to the second optical module 13 via optical fiber; the second optical module 13 is used to convert the reset optical signal into a framed reset electrical signal, and send the framed reset electrical signal to the second control module 14; and / or, the second optical module 13 is used to convert the received framed wake-up electrical signal into a wake-up optical signal, and send the wake-up optical signal to the first optical module 12 via optical fiber; the first optical module 12 is used to convert the wake-up optical signal into a framed wake-up electrical signal, and send the framed wake-up electrical signal to the first control module 11.

[0041] like Figure 3 A schematic diagram of a functional module is shown; wherein, the Host device corresponds to the above-mentioned PCIe main device, and the EP device corresponds to the above-mentioned PCIe remote device. After the CXP optical module on the Host device side receives the framed reset electrical signal, it converts the framed reset electrical signal into a corresponding framed reset optical signal through an internal photoelectric conversion circuit, and transmits it to the CXP optical module on the EP device side through an optical fiber; after the CXP optical module on the EP device side receives the framed reset optical signal, it converts the framed reset optical signal back into a corresponding framed reset electrical signal through an internal photoelectric conversion circuit, and sends it to the FPGA on the EP device side.

[0042] Below Figure 3In the figure, other functional modules on the host device side are described. The power module on the host device side is used to power each functional module on the host device side. The local clock is used to provide a reference clock source for the PLL clock chip. The PLL clock chip is used to output multiple clock signals based on the reference clock source provided by the local clock, thereby providing corresponding clock signals for the FPGA and PCIe switch module. For example, if the local clock is a 10 MHz reference clock source, the PLL clock chip can generate clock signals of various frequencies such as 100 MHz and 200 MHz based on this 10 MHz reference clock source. The configuration file storage can be used to store FPGA programs, etc.

[0043] Below Figure 3 In the figure, other functional modules on the EP device side are described. The power module on the EP device side is used to supply power to each functional module on the EP device side; the local clock is used to provide a reference clock source for the PLL clock chip; the PLL clock chip is used to output multiple clock signals based on the reference clock source provided by the local clock, thereby providing corresponding clock signals for the FPGA and EP device respectively; the configuration file storage can be used to store FPGA programs, etc.

[0044] After the CXP optical module on the EP device receives the framed wake-up electrical signal, it uses its internal optoelectronic conversion circuit to convert the framed wake-up electrical signal into a corresponding framed wake-up optical signal, which is then transmitted to the CXP optical module on the host device via optical fiber. After the CXP optical module on the host device receives the framed wake-up optical signal, it uses its internal optoelectronic conversion circuit to convert the framed wake-up optical signal back into a corresponding framed wake-up electrical signal, which is then sent to the FPGA on the host device. In actual applications, in low-power design scenarios, the host device needs to go into sleep mode. In this case, the main power supply is turned off to save power. After detecting a wake-up event, the EP device needs to wake up the host device through the WAKE# signal.

[0045] Furthermore, the second control module 14 is also used to parse the reset electrical signal after framing, and send the resolved reset electrical signal to the PCIe remote device 15 to reset the PCIe remote device 15; when the reset time of the PCIe remote device 15 reaches a preset time, the PCIe remote device 15 is de-reset; wherein, the de-reset time of the PCIe remote device 15 is controlled by the second control module, for example, earlier than the de-reset time of the PCIe main device 10.

[0046] like Figure 4The figure shows a schematic diagram of PCIe x8 fiber optic communication based on a CXP optical module. The host device corresponds to the above-mentioned PCIe master device, and the EP device corresponds to the above-mentioned PCIe remote device. Taking the reset single-ended signal as an example, the reset single-ended signal sent by the host device is collected by the FPGA on the host device side, framed according to some common protocols (such as the Aurora protocol), and transmitted to the FPGA on the EP device side via the SerDes transceiver, the CXP optical module on the host device side, the optical fiber, and the CXP optical module on the EP device side. The reset single-ended signal is then parsed and sent to the EP device.

[0047] The FPGA of the EP device can adjust the reset time of the EP device as needed, which can be earlier than the reset time of the host device; see Figure 5 The following figure shows a reset transmission timing diagram; t_rstdly is the delay between the EP device reset signal and the host device reset signal, t_rst is the minimum valid reset time of the EP device (corresponding to the preset duration mentioned above), and t_rising is the adjustable range of the rising edge of the EP device reset signal. After the FPGA reset time for the EP device reaches t_rst, it can pull the reset signal high, allowing the EP device to start initialization before the host device. Typically, the FPGA framing and deframing time is approximately 0.2us to 0.4us, the delay of a 10G optical module is 3ns, and the transmission delay over 100 meters of optical fiber is approximately 0.5us. Therefore, the maximum t_rstdly does not exceed 2us.

[0048] In this approach, a single CXP optical module is used on both the host and EP devices to simultaneously transmit PCIe data and sideband signals such as reset and WAKE#. After the reset signal is encoded by the host's FPGA, transmitted over optical fiber, and decoded by the EP's FPGA, the reset timing for the EP device can be flexibly adjusted.

[0049] Furthermore, the first switching module is used to preprocess the data electrical signal obtained from the PCIe master device and send the preprocessed data electrical signal to the first optical module; the first optical module is used to convert the received preprocessed data electrical signal into a data optical signal and send the data optical signal to the second optical module through the optical fiber; the second optical module is used to convert the data optical signal into a preprocessed data electrical signal and send it to the PCIe remote device through the second switching module 17.

[0050] The above pre-processing can be to read the address information of the data signal; see Figure 6The figure shows a schematic diagram of the internal functional block diagram of a switching module; taking the first switching module on the PCIe host device side as an example, the switching module includes one upstream port and multiple downstream ports, and the upstream port and each downstream port are connected through an internal virtual bus communication. The multiple downstream ports may correspond to different bandwidths; the host device side sends the data electrical signal to the upstream port in the switching module, the upstream port can read the address information carried in the data electrical signal, and send the data electrical signal to the downstream port corresponding to the address information, and then send it to the CXP optical module on the host device side.

[0051] Similarly, the second switching module 17 is used to preprocess the electrical data signals received from the PCIe remote device and transmit the preprocessed electrical data signals to the second optical module. The second optical module is used to convert the received preprocessed electrical data signals into optical data signals and transmit the optical data signals to the first optical module via optical fiber. The first optical module is used to convert the optical data signals into preprocessed electrical data signals and transmit them to the PCIe master device via the first switching module. The internal functions of the second switching module 17 on the PCIe remote device side can be referred to the relevant description of the internal functions of the first switching module above and will not be repeated here.

[0052] It should be noted that the PCIe 3.0 specification requires lane skew (channel deviation) at the receiver to not exceed 6ns. However, there are consistency issues between individual SFP+ or QSFP+ optical modules. The optical-to-electrical conversion latency (delay) of lanes in the optical modules, combined with the latency of the optical fiber, varies between optical modules, potentially causing lane skew to not meet the 6ns requirement. CXP optical modules, on the other hand, pose little risk. Some CXP optical modules can achieve lane skew of less than 220ps with a fiber length of 100 meters. The internal lane-to-lane skew of CXP optical modules can be less than 1ns, making the use of CXP optical modules for PCIe communication easier than ever before.

[0053] In addition, the CXP optical module integrates a 100nF AC coupling capacitor. Although this does not meet the requirements of the PCIe Gen3 specification, it only affects the PCIe signal SI (Signal Integrity) problem. Practice has proven that this can be solved through the pre-emphasis / de-emphasis and equalization technology of the PCIe switch module.

[0054] Furthermore, the first control module includes a first framing module, a first mode conversion module and a first parsing module; the second control module includes a second framing module, a second mode conversion module and a second parsing module; the first framing module is used to frame and encrypt the first sideband electrical signal from the PCIe master device to obtain a first framing signal, and send the first framing signal to the first mode conversion module; the first mode conversion module is used to convert the first framing signal from the current parallel mode to the serial mode to obtain the first differential signal; and is also used to receive the encrypted transmitted second differential signal, and send the second differential signal to the first parsing module block; the first parsing module is used to parse the second differential signal to obtain the second sideband electrical signal; the second framing module is used to frame and encrypt the second sideband electrical signal from the PCIe remote device to obtain a second frame signal, and send the second frame signal to the second mode conversion module; the second mode conversion module is used to convert the second frame signal from the current parallel mode to the serial mode to obtain the second differential signal; it is also used to receive the encrypted transmitted first differential signal, and send the first differential signal to the second parsing module; the second parsing module is used to parse the first differential signal to obtain the first sideband electrical signal.

[0055] like Figure 4 As shown, for the convenience of explanation, taking the first control module and the second control module as an example, the first frame module, the first mode conversion module and the first parsing module correspond to Figure 4 In the Host device side, FRAME_GEN, TXSerdes RX and FRAME_CHECK; the second framing module, the second mode conversion module and the second parsing module correspond to Figure 4 FRAME_GEN, TX Serdes RX and FRAME_CHECK on the EP device side.

[0056] The following describes each module in the FPGA on the host device side in detail. FRAME_GEN is used to frame and encrypt the reset single-ended signal to obtain a first frame signal, which is then sent to the TX Serdes RX. TXSerdes RX is used to convert the first frame signal from the current parallel mode to the serial mode, obtain the encrypted first differential signal corresponding to the reset single-ended signal, and send it to the corresponding CXP optical module. TX Serdes RX is also used to receive the encrypted second differential signal corresponding to the wake-up electrical signal, convert the encrypted second differential signal from the current serial mode to the parallel mode, and send it to FRAME_CHECK. FRAME_CHECK is used to parse the encrypted second differential signal in the parallel mode to obtain the wake-up single-ended signal.

[0057] The following is a detailed description of each module in the FPGA on the EP device side. FRAME_GEN is used to frame and encrypt the wake-up single-ended signal to obtain a second frame signal, which is then sent to the TX Serdes RX. TXSerdes RX is used to convert the second frame signal from the current parallel mode to the serial mode, obtain the encrypted second differential signal corresponding to the wake-up single-ended signal, and send it to the corresponding CXP optical module. TX Serdes RX is also used to receive the encrypted first differential signal corresponding to the reset single-ended signal, convert the encrypted first differential signal from the current serial mode to the parallel mode, and send it to FRAME_CHECK. FRAME_CHECK is used to parse the encrypted first differential signal in the parallel mode to obtain the reset single-ended signal.

[0058] An embodiment of the present invention further provides a data transmission method, which includes the following steps:

[0059] Step 1: framing the received first sideband electrical signal, converting the first sideband electrical signal into a first differential signal and encrypting the signal for transmission;

[0060] Step 2: sending the data to the PCIe remote device via the first optical module and the second optical module in sequence;

[0061] Step 3: Receive and analyze the encrypted second differential signal sent by the PCIe remote device to obtain a second sideband electrical signal;

[0062] Step 4: Send the second sideband electrical signal to the PCIe master device to control the PCIe master device to perform an action corresponding to the second sideband electrical signal.

[0063] The above-described data transmission method corresponds to the relevant processes executed by the first control module in the aforementioned embodiment. For details, please refer to the relevant description in the aforementioned system embodiment and will not be repeated here. This method ensures the security and accuracy of data transmission by converting the first sideband electrical signal into a first differential signal and encrypting it for transmission. By analyzing the encrypted second differential signal to obtain the second sideband electrical signal, accurate control of the PCIe master device can be achieved.

[0064] An embodiment of the present invention further provides another data transmission method, which includes the following steps:

[0065] Step 5: Receive and analyze the encrypted first differential signal sent by the PCIe master device to obtain a first sideband electrical signal;

[0066] Step 6: Send the first sideband electrical signal to the PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal;

[0067] Step 7: framing the received second sideband electrical signal, converting the second sideband electrical signal into a second differential signal and encrypting the signal for transmission;

[0068] Step 8: Send the signal to the PCIe master device via the second optical module and the first optical module in sequence.

[0069] The above-described data transmission method corresponds to the relevant processes performed by the second control module in the aforementioned embodiment. For details, please refer to the relevant description in the aforementioned system embodiment and will not be repeated here. This method ensures the security and accuracy of data transmission by converting the second sideband electrical signal into a second differential signal and encrypting it for transmission. By analyzing the encrypted first differential signal to obtain the first sideband electrical signal, accurate control of the PCIe remote device can be achieved.

[0070] Furthermore, the first sideband electrical signal is a reset electrical signal; the method further includes: parsing the framed reset electrical signal, sending the parsed reset electrical signal to the PCIe remote device to reset the PCIe remote device; and resetting the PCIe remote device when the reset duration of the PCIe remote device reaches a preset duration. For details, please refer to the relevant description in the aforementioned system embodiment and will not be repeated here.

[0071] An embodiment of the present invention further provides another data transmission method, which includes the following steps:

[0072] Step 9: The first control module frames the first sideband electrical signal from the PCIe master device, converts the first sideband electrical signal into a first differential signal, encrypts the signal for transmission, and sends the signal to the second control module via the first optical module and the second optical module. The second control module is configured to parse the encrypted first differential signal and send the parsed first sideband electrical signal to the PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal.

[0073] Step 10: The second control module frames the second sideband electrical signal from the PCIe remote device, converts the second sideband electrical signal into a second differential signal, encrypts the signal for transmission, and sends the signal to the first control module via the second optical module and the first optical module. The first control module parses the encrypted second differential signal and sends the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to execute an action corresponding to the second sideband electrical signal.

[0074] Step 11: The PCIe master device and the PCIe remote device transmit data signals to each other through the first switching module, the first optical module, the second optical module, and the second switching module.

[0075] The above-mentioned data transmission method can transmit the first sideband electrical signal and the second sideband electrical signal while transmitting the data signal. The first sideband electrical signal, the second sideband electrical signal and the data signal can share the first optical module and the second optical module. Therefore, the occupied area of ​​the PCB is small and no additional hardware is required, thereby reducing hardware costs.

[0076] Furthermore, the first sideband electrical signal is a reset electrical signal; the second sideband electrical signal is a wake-up electrical signal; and the framing is performed by encoding the collected first sideband electrical signal or the second sideband electrical signal and adding a header and a tail.

[0077] In practice, framing primarily determines the start and end of data. The first sideband signal is encoded and a header and trailer are added to the front and back of the signal. A frame consists of the header, the encoded first sideband signal, and the trailer. The second sideband signal is encoded and a header and trailer are added to the front and back of the signal. A frame consists of the header, the encoded second sideband signal, and the trailer. The header and trailer typically contain a variety of control information, such as a transmission sequence number, to ensure data order and accuracy.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission system, characterized in that: include: A PCIe master device, a first control module, a first optical module and a second optical module for transmitting multiple signals, a second control module, and a PCIe remote device connected in sequence; The PCIe host device is connected to the first optical module via the first switching module; the PCIe remote device is connected to the second optical module via the second switching module; The first control module is configured to frame the first sideband electrical signal from the PCIe master device, convert the first sideband electrical signal into a first differential signal, encrypt the signal for transmission, and sequentially send the signal to the second control module via the first optical module and the second optical module; The second control module is configured to parse the encrypted first differential signal and send the first sideband electrical signal obtained by parsing to the PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; The second control module is configured to frame the second sideband electrical signal from the PCIe remote device, convert the second sideband electrical signal into a second differential signal, encrypt the signal for transmission, and sequentially send the signal to the first control module via the second optical module and the first optical module; the first control module is configured to parse the encrypted second differential signal and send the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to execute an action corresponding to the second sideband electrical signal; The PCIe master device and the PCIe remote device transmit data signals to each other through the first switching module, the first optical module, the second optical module and the second switching module.

2. The system according to claim 1, wherein: The first sideband electrical signal is a reset electrical signal; The first control module is used to frame the reset electrical signal from the PCIe master device according to a preset protocol; and / or The second sideband electrical signal is a wake-up electrical signal; The second control module is used to frame the wake-up electrical signal from the PCIe remote device according to a preset protocol.

3. The system according to claim 2, characterized in that The first optical module is used to convert the received framed reset electrical signal into a reset optical signal, and send the reset optical signal to the second optical module through an optical fiber; The second optical module is used to convert the reset optical signal into the framed reset electrical signal, and send the framed reset electrical signal to the second control module; and / or, The second optical module is used to convert the received framed wake-up electrical signal into a wake-up optical signal, and send the wake-up optical signal to the first optical module through an optical fiber; The first optical module is configured to convert the wake-up optical signal into the framed wake-up electrical signal, and send the framed wake-up electrical signal to the first control module.

4. The system according to claim 2, wherein: The second control module is further configured to parse the framed reset electrical signal and send the parsed reset electrical signal to the PCIe remote device to reset the PCIe remote device; When the reset duration of the PCIe remote device reaches a preset duration, the PCIe remote device is de-reset; wherein the de-reset time of the PCIe remote device is controlled by the second control module.

5. The system according to claim 1, wherein: The first switching module is used to preprocess the data electrical signal obtained from the PCIe master device and send the preprocessed data electrical signal to the first optical module; The first optical module is used to convert the received pre-processed data electrical signal into a data optical signal, and send the data optical signal to the second optical module through an optical fiber; The second optical module is used to convert the data optical signal into the preprocessed data electrical signal and send it to the PCIe remote device through the second switching module.

6. The system according to claim 1, wherein: The first control module includes a first framing module, a first mode conversion module and a first parsing module; the second control module includes a second framing module, a second mode conversion module and a second parsing module; The first framing module is used to frame and encrypt the first sideband electrical signal from the PCIe master device to obtain an encrypted first frame signal, and send the encrypted first frame signal to the first mode conversion module; The first mode conversion module is used to convert the encrypted first group of frame signals from the current parallel mode to the serial mode to obtain an encrypted first differential signal; further configured to receive the encrypted second differential signal, convert the encrypted second differential signal from a current serial mode to a parallel mode to obtain an encrypted second set of frame signals, and send the encrypted second set of frame signals to the first parsing module; The first parsing module is used to parse the encrypted second frame signal to obtain the second sideband electrical signal; The second framing module is used to frame and encrypt the second sideband electrical signal from the PCIe remote device to obtain an encrypted second frame signal, and send the encrypted second frame signal to the second mode conversion module; The second mode conversion module is used to convert the encrypted second group of frame signals from the current parallel mode to the serial mode to obtain an encrypted second differential signal; further configured to receive the encrypted first differential signal, convert the encrypted first differential signal from a current serial mode to a parallel mode to obtain an encrypted first set of frame signals, and send the encrypted first set of frame signals to the second parsing module; The second parsing module is used to parse the encrypted first group of frame signals to obtain the first sideband electrical signal.

7. A data transmission method, characterized in that: The method comprises: framing the received first sideband electrical signal, converting the first sideband electrical signal into a first differential signal, and encrypting and transmitting the signal; Sending to the PCIe remote device via the first optical module and the second optical module in sequence; Receive and analyze the encrypted second differential signal sent by the PCIe remote device to obtain a second sideband electrical signal; The second sideband electrical signal is sent to a PCIe master device to control the PCIe master device to perform an action corresponding to the second sideband electrical signal.

8. A data transmission method, characterized in that: The method comprises: Receive and analyze the encrypted first differential signal sent by the PCIe master device to obtain a first sideband electrical signal; Sending the first sideband electrical signal to a PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; framing the received second sideband electrical signal, converting the second sideband electrical signal into a second differential signal and encrypting the signal for transmission; The signals are sequentially sent to the PCIe master device via the second optical module and the first optical module.

9. The method according to claim 8, characterized in that The first sideband electrical signal is a reset electrical signal; and the method further includes: Parse the reset electrical signal after the framing, and send the reset electrical signal obtained by the parsing to the PCIe remote device to reset the PCIe remote device; when the reset time of the PCIe remote device reaches a preset time, release the reset of the PCIe remote device.

10. A data transmission method, characterized in that: The method comprises: The first control module frames the first sideband electrical signal from the PCIe master device, converts the first sideband electrical signal into a first differential signal, encrypts the signal for transmission, and sends the signal to the second control module via the first optical module and the second optical module in sequence; the second control module is configured to parse the encrypted first differential signal and send the first sideband electrical signal obtained by parsing the signal to the PCIe remote device to control the PCIe remote device to perform an action corresponding to the first sideband electrical signal; The second control module frames the second sideband electrical signal from the PCIe remote device, converts the second sideband electrical signal into a second differential signal, encrypts the signal for transmission, and sequentially sends the signal to the first control module via the second optical module and the first optical module; the first control module is configured to parse the encrypted second differential signal and send the parsed second sideband electrical signal to the PCIe master device to control the PCIe master device to execute an action corresponding to the second sideband electrical signal; The PCIe master device and the PCIe remote device transmit data signals to each other through the first switching module, the first optical module, the second optical module and the second switching module.

11. The method according to claim 10, characterized in that The first sideband electrical signal is a reset electrical signal; the second sideband electrical signal is a wake-up electrical signal; The framing is to encode the collected first sideband electrical signal or the second sideband electrical signal and add a header and a tail.

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