A method, network architecture and network device for reducing the bit error rate of an Ethernet network

Abstract

The present specification provides a method, network architecture and network device for reducing the error rate of Ethernet, the method comprising: setting a FlexE shim layer between an Ethernet media access control (MAC) layer and a physical (PHY) layer, performing first forward error correction (FEC) calculation on encoded traffic through interleaving multiplexing using the 5G slot of the FlexE shim layer to obtain first traffic after error correction, and performing second FEC calculation on the first traffic using the PHY layer to obtain second traffic after error correction. Through the method, the error rate of Ethernet can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a method, network architecture, and network device for reducing Ethernet bit error rate. Background Technology

[0002] Forward error correction (FEC) is a technique used to control errors when transmitting data in unreliable or noisy channels. Forward error correction coding (FEC) features gain coding techniques such as concatenated channel coding and can automatically correct transmission errors.

[0003] During physical layer link transmission, as the frequency of electrical signals increases, noise has a more severe impact on data transmission. Simply relying on channel encoding and decoding is no longer sufficient to guarantee the transmission quality of SerDes. Therefore, after the SerDes rate increased to 56G PAM4, IEEE 802.3 defined RS-FEC (544, 514) error correction code technology to improve the bit error rate in high-speed communication. Due to the openness of the Ethernet standard and the good interoperability of Ethernet technology, this error correction coding technology is also the preferred technology for high-capacity transmission network equipment. Considering that Ethernet design prioritizes economy and sacrifices some quality requirements, the link error correction capability is a compromise. The OIF has compared FEC technologies for electrical signals and found that RS (544 / 514) still lags significantly behind ITU G.975.119 used in high-speed interfaces of OTN equipment. This directly results in Ethernet's weaker optical layer adaptation capability compared to traditional OTN for long-distance link transmission. This manifests in the fact that during a 48-hour code table test, the bit error rate of the Ethernet link remains relatively high, failing to achieve absolute zero packet loss. Summary of the Invention

[0004] To reduce Ethernet bit error rate during traffic transmission, this disclosure provides a method, network architecture, and network device for reducing Ethernet bit error rate.

[0005] This disclosure provides a method for reducing Ethernet bit error rate, the method comprising:

[0006] A FlexE shim layer is set between the Ethernet Media Access Control (MAC) layer and the physical PHY layer;

[0007] Using the 5G slot of the FlexE shim layer, the first forward error correction (FEC) calculation is performed on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0008] The second FEC is calculated on the first flow using the PHY layer to obtain the error-corrected second flow.

[0009] The step of using the 5G slot of the FlexE shim layer to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing includes:

[0010] According to the FlexE protocol, obtain the slot of the Ethernet interface with the corresponding bandwidth;

[0011] Perform the first FEC calculation for the encoded traffic data of each slot.

[0012] The first FEC calculation for the encoded traffic data of each slot includes:

[0013] The encoded traffic data of each slot is grouped together to construct RS codes for the first FEC calculation.

[0014] The process of obtaining the first traffic after error correction includes:

[0015] The first traffic after error correction includes encoded traffic data and redundant code blocks calculated by the first FEC.

[0016] Each slot is configured to carry the first N bits of encoded traffic data and the next N+1 bits of redundant code blocks, where N is a number greater than 0.

[0017] The method further includes:

[0018] The FlexE shim layer receives the decoded traffic sent by the physical layer. The decoded traffic is the traffic after the physical layer performs a second FEC calculation on the decoded traffic data. When the physical layer performs FEC calculation on the decoded traffic data, it does not replace the bit errors with error code blocks.

[0019] The FlexE shim layer utilizes 5G slots and performs the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0020] As can be seen from the above embodiments, the scheme based on FlexE extension to support FlexE layer FEC, combined with Ethernet layer FEC, achieves dual-layer superimposed error correction, effectively improving error correction capability and reducing Ethernet bit error rate.

[0021] Based on the above method, this disclosure also provides a network architecture, which includes: MAC, FlexE shim, PCS, PMA, and PMD, wherein PCS, PMA, and PMD constitute the physical layer PHY;

[0022] The FlexE shim layer uses 5G slots to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0023] The PCS in the physical layer PHY performs a second FEC calculation on the first flow to obtain the error-corrected second flow.

[0024] The FlexE shim layer obtains the slot of the Ethernet interface with the corresponding bandwidth according to the FlexE protocol.

[0025] Perform the first FEC calculation for the encoded traffic data of each slot.

[0026] The FlexE shim layer receives the decoding traffic sent by the PCS. The decoding traffic is the traffic after the PCS performs a second FEC calculation on the decoding traffic data. When the PCS performs FEC calculation on the decoding traffic data, it does not replace the bit errors with error code blocks.

[0027] The FlexE shim layer utilizes 5G slots and performs the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0028] This disclosure also provides a network device, which includes: a memory, a processor, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements any of the above-described method embodiments.

[0029] This disclosure also provides a computer-readable storage medium storing a program that, when executed by a processor, implements any of the above-described method embodiments. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0031] Figure 1 This is a flowchart illustrating a method for reducing Ethernet bit error rate according to an embodiment of this disclosure.

[0032] Figure 2 This is a schematic diagram of a network model provided in an embodiment of the present disclosure. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0034] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0035] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0036] Different FEC algorithms introduce redundancy code regions of varying lengths, directly causing changes in the frequency of hardware SerDes and ultimately disrupting the existing Ethernet ecosystem, thus rendering this approach impractical. Currently, low-error-rate bearers still require OTN, achieved by connecting the Ethernet interface to an OTN device's board, encapsulating it into OTUk frames with stronger FEC capabilities, and then transmitting them over long distances.

[0037] The following problems will also arise accordingly:

[0038] 1. Using OTN as the carrier method results in a relatively closed OTN industry that cannot leverage the mature ecosystem of Ethernet, leading to higher costs.

[0039] 2. Currently, OTN equipment manufacturers' equipment cannot be decoupled, resulting in closed networks. Network construction is exclusive and easily controlled by a single manufacturer, leading to high networking costs.

[0040] 3. The deployment scope of OTN equipment is limited, and the return on investment is low when building an OTN network for a single low bit error rate service.

[0041] To address the aforementioned technical challenges, the inventors creatively extended FEC technology at the SHIM layer based on FlexE technology, enabling Ethernet services to adapt to low bit error rate links, achieving bit error correction capabilities close to OTN, supporting longer transmission distances, and solving the problem of Ethernet packet loss.

[0042] This disclosure provides a method for reducing Ethernet bit error rate, such as... Figure 1 As shown, the method includes:

[0043] S101 sets up a FlexE shim layer between the Ethernet Media Access Control (MAC) layer and the physical PHY layer;

[0044] S102 utilizes the 5G slot of the FlexE shim layer to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0045] S103 uses the PHY layer to perform a second FEC calculation on the first flow to obtain the error-corrected second flow.

[0046] It should be noted that, in this embodiment, the encoded traffic refers to the traffic from MAC to PCS (i.e., the direction of traffic encoding), and the decoded traffic refers to the traffic from PCS to MAC (i.e., the direction of traffic decoding).

[0047] like Figure 2 As shown, the standard external network model includes: MAC layer, PCS layer, PMA layer, and PMD layer (where the combination of PCS layer, PMA layer, and PMD layer can also be called physical layer PHY). In this embodiment, the FlexE model is adopted, and a FlexE shim layer is set between the MAC layer and the PCS layer.

[0048] In step S102, the first forward error correction (FEC) calculation is performed on the encoded traffic using the 5G slot of the FlexE shim layer through interleaved multiplexing, including: obtaining the slot of the Ethernet interface with the corresponding bandwidth according to the FlexE protocol.

[0049] Perform the first FEC calculation for the encoded traffic data of each slot.

[0050] In practical applications, Ethernet interfaces can have various bandwidths, such as 50G, 100G, 200G, and 400G Ethernet interfaces. For example, based on the FlexE protocol, a 100G Ethernet interface can use 20 slots as a cycle (the specification defined by the 100G FlexE protocol is 20*1023), while a 50G Ethernet interface can use 10 slots as a cycle (the specification defined by the 50G FlexE protocol is 10*2*1023).

[0051] In this embodiment, after obtaining the 5G slot, the coded traffic data of each slot is grouped together to construct RS codes for the first FEC calculation.

[0052] For example, taking a 100G Ethernet interface as an example, with 20 slots as a cycle, referring to the implementation of OTUk, the 66-bit boundary of the slot is broken, and an 8-bit RS code block is constructed to perform the FEC calculation of RS(255,239) (i.e., the first FEC calculation).

[0053] In this embodiment, redundant code blocks can be obtained through FEC calculation. At this time, the first N bits of each slot can be set to carry the encoded traffic data, and the last N+1 bits can carry the redundant code blocks, where N is a number greater than 0.

[0054] For example, in a 100G external network interface, after the first FEC calculation, the first 956 blocks of each slot can be set as the data carrier, 957 to 1020 are used to store the redundant code blocks calculated by FEC, and 1021 to 1023 are reserved fields, set to all 0, and reserved for no use (N is 956).

[0055] By using the above method, FEC redundancy blocks are calculated independently for the data in each slot. This reduces the impact of continuous failures caused by noise, and continuous bit errors are evenly distributed across 20 slots, which can effectively reduce the bit error rate of Ethernet.

[0056] As can be seen from the above embodiments, for traffic that needs to be encoded, two FECs (with different FEC algorithms) are performed on the FlexE shim layer and the PCS layer, which can effectively reduce the bit error rate of traffic encoding. When the FlexE shim layer receives the decoded traffic sent by the physical layer, the decoded traffic is the traffic after the physical layer performs the second FEC calculation on the decoded traffic data. The FlexE shim layer uses the 5G slot and performs the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the error-corrected first traffic. That is, the traffic that needs to be decoded is subjected to two FECs to reduce the bit error rate of traffic decoding.

[0057] Specifically, redundant codes are decoded and restored in the receiving direction. The specific encoding and decoding process refers to the standard Ethernet specification. Multiple algorithms can be used, and different algorithms result in different bandwidth utilization rates. Taking RS(255,239) as an example, the bandwidth utilization rate of a single FlexE slot is 93%, and the bandwidth utilization of a single slot of a 100G FlexE interface is reduced from 5G to 4.65G.

[0058] In this embodiment, to prevent packet loss, the Physical Layer (PCS) needs to configure itself when performing a second FEC on the traffic to be decoded. For ETH blocks, the error code blocks specified in the 802.3 protocol will be replaced, and the blocks will be passed through to the FlexE shim layer instead of being directly passed through. This allows the FlexE shim layer to perform a second FEC on the traffic to be decoded through the first FEC to continue error correction, thereby reducing the Ethernet bit error rate.

[0059] As can be seen from the above embodiments, this disclosure implements enhanced FEC for the FlexE interface. By supporting FlexE FEC on the Ethernet port, the FEC function of the Ethernet standard is enhanced, giving Ethernet a powerful FEC capability similar to OTN, enabling the replacement of OTN in Ethernet scenarios. Furthermore, it solves the inherent packet loss problem of Ethernet, providing the ability to support independent networking of lossless Ethernet leased lines over medium to long distances, thus eliminating dependence on OTN devices.

[0060] Based on the above method embodiments, this disclosure also provides a network architecture, which includes: MAC, FlexE shim, PCS, PMA, and PMD, wherein PCS, PMA, and PMD constitute the physical layer PHY.

[0061] The FlexE shim layer uses 5G slots to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0062] The PCS in the physical layer PHY performs a second FEC calculation on the first flow to obtain the error-corrected second flow.

[0063] The FlexE shim layer obtains the slot of the Ethernet interface with the corresponding bandwidth according to the FlexE protocol.

[0064] Perform the first FEC calculation for the encoded traffic data of each slot.

[0065] The FlexE shim layer receives the decoding traffic sent by the PCS. The decoding traffic is the traffic after the PCS performs a second FEC calculation on the decoding traffic data. When the PCS performs FEC calculation on the decoding traffic data, it does not replace the bit errors with error code blocks.

[0066] The FlexE shim layer utilizes 5G slots and performs the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the first traffic after error correction.

[0067] This disclosure also provides a network device that enables the network architecture described above. The network device includes a memory, a processor, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements any of the above embodiments.

[0068] This disclosure also provides a computer-readable storage medium storing a program that, when executed by a processor, implements any of the above embodiments.

[0069] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0070] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0071] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0072] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A method for reducing Ethernet bit error rate, characterized in that, The method includes: Set up a FlexE shim layer between the Ethernet Media Access Control (MAC) layer and the physical PHY layer; Using the 5G slot of the FlexE shim layer, the first forward error correction (FEC) calculation is performed on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction. The second FEC calculation is performed on the first flow using the PHY layer to obtain the error-corrected second flow. The FlexE shim layer receives the decoding traffic sent by the physical layer. The decoding traffic is the traffic after the physical layer performs a second FEC calculation on the decoding traffic data. When the physical layer performs FEC calculation on the decoding traffic data, it does not replace the bit errors with error code blocks. The FlexE shim layer utilizes 5G slots to perform the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the error-corrected first traffic. In this case, the FEC redundant code block is calculated independently for the data in each slot.

2. The method according to claim 1, characterized in that, The method of utilizing the 5G slot of the FlexE shim layer to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing includes: According to the FlexE protocol, obtain the slot of the Ethernet interface with the corresponding bandwidth; Perform the first FEC calculation for the encoded traffic data of each slot.

3. The method according to claim 2, characterized in that, The first FEC calculation for the encoded traffic data for each slot includes: The encoded traffic data of each slot is grouped together to construct RS codes for the first FEC calculation.

4. The method according to claim 1, characterized in that, The process of obtaining the first corrected data stream includes: The first traffic after error correction includes encoded traffic data and redundant code blocks calculated by the first FEC. Each slot is configured to carry the first N bits of encoded traffic data and the next N+1 bits of redundant code blocks, where N is a number greater than 0.

5. A network architecture, characterized in that, The network architecture includes: MAC, FlexE shim, PCS, PMA, and PMD, wherein PCS, PMA, and PMD constitute the physical layer PHY. The FlexE shim layer uses 5G slots to perform the first forward error correction (FEC) calculation on the coded traffic through interleaved multiplexing to obtain the first traffic after error correction. The PCS in the physical layer PHY performs a second FEC calculation on the first flow to obtain the error-corrected second flow. The FlexE shim layer receives the decoding traffic sent by the physical layer. The decoding traffic is the traffic after the physical layer performs a second FEC calculation on the decoding traffic data. When the physical layer performs FEC calculation on the decoding traffic data, it does not replace the bit errors with error code blocks. The FlexE shim layer utilizes 5G slots to perform the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the error-corrected first traffic. In this case, the FEC redundant code block is calculated independently for the data in each slot.

6. The network architecture according to claim 5, characterized in that, The FlexE shim layer obtains the slot of the Ethernet interface with the corresponding bandwidth according to the FlexE protocol; Perform the first FEC calculation for the encoded traffic data of each slot.

7. The network architecture according to claim 5, characterized in that, The FlexE shim layer receives the decoding traffic sent by the PCS. The decoding traffic is the traffic after the PCS performs a second FEC calculation on the decoding traffic data. When the PCS performs FEC calculation on the decoding traffic data, it does not replace the bit errors with error code blocks. The FlexE shim layer utilizes 5G slots and performs the first FEC calculation on the decoded traffic through interleaved multiplexing to obtain the first traffic after error correction.

8. A network device, characterized in that, The network device includes: a memory, a processor, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the method steps as described in any one of claims 1 to 4.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program that, when executed by a processor, implements the method steps as described in any one of claims 1 to 4.

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