Control device and control method for transmitting video data using double-edge flip-flop

Abstract

The application relates to a control device and a control method for transmitting video data by using double-edge flip-flop, which comprises a video decoder chip and a video display interface chip, and a video signal selection device is arranged between the video decoder chip and the video display interface chip; the video signal selection device comprises a double-edge flip-flop and two two-way data selectors; a positive edge input end of the double-edge flip-flop is connected with an output end of the first two-way data selector; a negative edge input end of the double-edge flip-flop is connected with an output end of the second two-way data selector; and selection signal input ends of the two two-way data selectors are connected with sel signals. The control device and the control method for transmitting video data by using double-edge flip-flop adopt the double-edge flip-flop to generate DDR and SDR signals; no matter the DDR or the SDR signal, the last stage logic of the data output is fixed, the determinacy of input and output timing is ensured, the circuit is simplified, the transmission cost is reduced, and the video data transmission efficiency is improved.

Description

Technical Field

[0001] This invention relates to a video data processing method, specifically, to a control device and control method for transmitting video data using a dual-edge trigger. Background Technology

[0002] In the digital video industry, the chips responsible for generating video, such as video decoder chips (hereinafter referred to as source chips), and the chips that push the video to computer monitors or television screens (video display interface chips) are often separate. A common format for video data interaction between these two types of chips is control signals such as horizontal and vertical sync signals (hs, vs, de), data signals such as video data (rgb / yuv), and a video clock (pixel_clk). For different resolutions, the video clock will change, but the format of the interface signals will remain the same. For example, standard definition (720x576@60fps) resolution corresponds to a 27MHz video clock, while high definition (1920x1080@60fps) resolution corresponds to a 148.5MHz video clock.

[0003] This video interaction solution typically relies on LVCMOS for its underlying interface, characterized by point-to-point, single-ended transmission. This interface standard has proven effective and has remained popular in the industry for many years. However, in recent years, as video resolution has shifted from traditional standard definition and high definition to 4K, this interface standard has begun to face challenges. If the goal is to reuse existing video data interaction interfaces, a natural approach would be to further increase the video clock frequency. For example, 4K@30fps corresponds to a clock frequency of 297MHz. If the video clock could be increased to 297MHz, the problem would be solved. Unfortunately, the physical interface level standard (LVCMOS) makes it extremely difficult to support interface signals exceeding 200MHz. To reuse existing standards without increasing clock frequency, most common video display interface chips in the industry support so-called DDR mode in their receivers. This means the video clock frequency doesn't need to reach 297MHz, but only half that, 148.5MHz. Video data is transmitted simultaneously on both the rising and falling edges of the clock. The bandwidth of this video data is equivalent to SDR (single-edge mode) transmission at 297MHz. This is an excellent idea, but the challenge lies in the fact that the source chip must also support DDR signals for resolutions above 4K, while using SDR signals for lower resolutions.

[0004] For signal source chips, generating DDR interface signals generally requires the use of a dual-edge flip-flop (DDR flop), while generating SDR interface signals generally only requires a single-edge flip-flop (SDR flop). This is common knowledge in the engineering field.

[0005] Therefore, DDR (4K resolution) and SDR (resolution below 4K) modes must use combinational logic (such as a multiplexer) to select between them before outputting I / O. If the delay from the clock to the data output of the last-stage register is denoted as t0 (commonly referred to in the industry as clk-to-q delay), the delay from the data output to the chip pad is denoted as t1, and the delay of the pad itself is denoted as t2, then the total delay of the video data can be expressed as t = t0 + t1 + t2.

[0006] For existing technologies, data at different resolutions must first pass through two sets of registers of different types. Considering that the delay from the terminal to the data output terminal (clk-to-q delay) of different types of registers cannot be exactly the same, that is to say, t0 is related to the resolution (even for registers of the same type, there will be some differences in the clk-to-q delay between individual registers).

[0007] In addition, there are two paths from the data output terminal to the chip pad (see [reference]). Figure 3 The delay t1 of the 4k_path and 1080p_path (labeled) will also differ (mainly due to the difference in the connection lengths of the two paths, and the difference in the delays of the 0 and 1 terminals of the multiplexer). Therefore, under the traditional method, the total delay of data output cannot remain constant for different resolutions. This leads to at least two different I / O timing scenarios, which inevitably poses a considerable challenge to the timing constraints of inter-chip interconnects. If the timing of the interconnected interfaces is not met, data cannot be transmitted normally. Summary of the Invention

[0008] To address the shortcomings of the prior art, this invention provides a control method for transmitting video data using a dual-edge flip-flop, which simplifies the circuit, reduces transmission costs, and improves the efficiency and reliability of video data transmission.

[0009] The technical solution adopted in this invention is:

[0010] A control device for transmitting video data using a dual-edge flip-flop includes a video decoder chip and a video display interface chip. A video signal selection device is disposed between the video decoder chip and the video display interface chip. The video signal selection device includes a dual-edge flip-flop and two dual-channel data selectors. The positive edge input terminal of the dual-edge flip-flop is connected to the output terminal of the first dual-channel data selector; the negative edge input terminal of the dual-edge flip-flop is connected to the output terminal of the second dual-channel data selector; the selection signal input terminals of the two dual-channel data selectors are connected to a sel signal.

[0011] The first input of the first dual-channel data selector is connected to the 4K data positive edge data;

[0012] The second input of the first dual-channel data selector is connected to the 1080p data output.

[0013] The first input of the second dual-channel data selector is connected to the 4K negative edge data.

[0014] The second input of the second dual-channel data selector is connected to the 1080p data input.

[0015] The second input terminal of the first dual-channel data selector is connected in parallel with the second input terminal of the second dual-channel data selector.

[0016] The CLK terminal of the dual-edge trigger is connected to the pixel_clk signal.

[0017] A method for controlling the transmission of video data using a device that transmits video data using a dual-edge flip-flop includes the following steps:

[0018] Step S101, Begin;

[0019] Step S102: Input video signal;

[0020] Step S103: Determine if the video signal resolution is 4K30. If it is 4K30, proceed to step S104; otherwise, proceed to step S107.

[0021] Step S104: Set the dual-channel data selector sel to 1;

[0022] Step S105: Configure the clock frequency corresponding to the pixel_clk resolution;

[0023] Step S106: Different video data are input to the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop, respectively;

[0024] Step S107: Set the dual-channel data selector sel to 0;

[0025] Step S108: Configure the clock frequency corresponding to the pixel_clk resolution;

[0026] Step S109: Input the same video data into the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop.

[0027] Step S110: The output terminal of the dual-edge flip-flop outputs video data;

[0028] Step S111, End.

[0029] The advantages of this invention over the prior art are:

[0030] This invention utilizes a control method for transmitting video data using a dual-edge flip-flop, which simplifies the circuit, reduces transmission costs, improves video data transmission efficiency, and enhances the stability and reliability of transmitted data.

[0031] This invention utilizes a control method for transmitting video data using dual-edge flip-flops. Dual-edge flip-flops are used to generate DDR and SDR signals. Regardless of whether it is a DDR or SDR signal, the last stage of its data output logic is fixed, ensuring the determinism of input / output (IO) timing. IO timing is an unavoidable pain point in the inter-chip interconnection of video systems.

[0032] This invention utilizes a control method for transmitting video data using a dual-edge flip-flop, which is particularly important for designs that use FPGAs to generate video and also has considerable value for ASIC video output designs.

[0033] While the practical problem solved by this invention is the data exchange method between the source chip and the video interface chip, it can also be extended to all situations where DDR and SDR need to be used simultaneously. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of data transmission between existing video decoder chips and video display interface chips.

[0035] Figure 2 This is a schematic diagram of DDR and SDR data transmission of existing video decoder chips and video display interface chips.

[0036] Figure 3 This is a schematic diagram of the structure for transmitting video data between existing video decoder chips and video display interface chips.

[0037] Figure 4 This is a schematic diagram of the structure of the control device for transmitting video data using a dual-edge flip-flop, which is a control device for transmitting video data according to the present invention, between the video decoder chip and the video display interface chip.

[0038] Figure 5 This is a control flowchart of the control method for transmitting video data using a dual-edge trigger, as described in this invention. Detailed Implementation

[0039] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0040] Appendix Figure 1-5It is known that a control device for transmitting video data using a dual-edge flip-flop includes a video decoder chip and a video display interface chip. A video signal selection device is provided between the video decoder chip and the video display interface chip. The video signal selection device includes a dual-edge flip-flop and two dual-channel data selectors. The positive edge input terminal of the dual-edge flip-flop is connected to the output terminal of the first dual-channel data selector; the negative edge input terminal of the dual-edge flip-flop is connected to the output terminal of the second dual-channel data selector; and the selection signal input terminals of the two dual-channel data selectors are connected to the sel signal.

[0041] The first input of the first dual-channel data selector is connected to the 4K data positive edge data;

[0042] The second input of the first dual-channel data selector is connected to the 1080p data output.

[0043] The first input of the second dual-channel data selector is connected to the 4K negative edge data.

[0044] The second input of the second dual-channel data selector is connected to the 1080p data input.

[0045] The second input terminal of the first dual-channel data selector is connected in parallel with the second input terminal of the second dual-channel data selector.

[0046] The CLK terminal of the dual-edge trigger is connected to the pixel_clk signal.

[0047] A method for controlling the transmission of video data using a control device that transmits video data via a dual-edge trigger includes the following steps:

[0048] Step S101, Begin;

[0049] Step S102: Input video signal;

[0050] Step S103: Determine if the video signal resolution is 4K30. If it is 4K30, proceed to step S104; otherwise, proceed to step S107.

[0051] Step S104: Set the dual-channel data selector sel to 1;

[0052] Step S105: Configure the clock frequency corresponding to the pixel_clk resolution;

[0053] Step S106: Different video data are input to the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop, respectively;

[0054] Step S107: Set the dual-channel data selector sel to 0;

[0055] Step S108: Configure the clock frequency corresponding to the pixel_clk resolution;

[0056] Step S109: Input the same video data into the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop.

[0057] Step S110: The output terminal of the dual-edge flip-flop outputs video data;

[0058] Step S111, End.

[0059] This invention utilizes a control method for transmitting video data using a dual-edge flip-flop. Since the data path selection logic precedes the register data input, as long as the arrival time of the video data at the register input satisfies timing constraints such as setup and hold times (known in the industry as setup-hold timing), then even if different branches of the multiplexer result in differences in the arrival time of video data at the register data input (see...), the method will work. Figure 4 However, these differences will not affect any of t0 / t1 / t2 at all.

[0060] This invention utilizes a control method for transmitting video data using a dual-edge flip-flop, which is particularly important for FPGA implementations because the dual-edge registers in an FPGA are typically designed near the pad, and there is no way to insert a multiplexer on the path from the dual-edge register output to the pad.

[0061] by Figure 4 For example, a typical video output process is as follows: First, it should be clear that the video resolution can only be one type at any given time: either 1080p, 4K30, or another resolution lower than 1080p, such as 576p. Application software designers should set the resolution according to user needs (e.g., the user selects the current output resolution via command line or graphical interface). If the user needs to output 1080p or lower resolution, the application software must set sel to 0; if 4K30 is required, sel should be set to 1.

[0062] The software then configures pixel_clk to the clock frequency corresponding to the resolution (e.g., 148.5MHz for 1080p and 4K30, 74.25MHz for 720p, and 27MHz for 576p) and enables the clock. Finally, it outputs 1080p_data (if it is a 1080p resolution) or 4k30_data_p / 4k30_data_n (if it is a 4K30 resolution) and the hs / vs / de control signals corresponding to the resolution.

[0063] like Figure 4If the multiplexer's sel value is 0, it selects the 1080p data channel; if the sel value is 1, it selects the 4K30 data channel.

[0064] The control system differentiates based on user needs, which requires the user to determine the current resolution; for example, the monitor resolution is adjusted manually.

[0065] Both 1080p and 4K30 use a clock frequency of 148.5MHz, but the former only uses the positive edge (SDR), while the latter uses both the positive and negative edges (DDR).

[0066] For other resolutions such as 720p and 576p, the pixel_clk frequency is reduced; for example, 720p commonly uses 74.25MHz while 576p commonly uses 27MHz pixel_clk. This is how it is done in this invention and existing technologies.

[0067] This invention utilizes a control method for transmitting video data using dual-edge flip-flops. Dual-edge flip-flops are used to generate DDR and SDR signals. Regardless of whether it is a DDR or SDR signal, the last stage of its data output logic is fixed, ensuring the determinism of input / output (IO) timing. IO timing is an unavoidable pain point in the inter-chip interconnection of video systems.

[0068] This invention utilizes a control method for transmitting video data using a dual-edge flip-flop, which is particularly important for designs that use FPGAs to generate video and also has considerable value for ASIC video output designs.

[0069] While the practical problem solved by this invention is the data exchange method between the source chip and the video interface chip, it can also be extended to all situations where DDR and SDR need to be used simultaneously.

[0070] This invention utilizes a control method for transmitting video data using dual-edge flip-flops. For 4K resolution, the positive edge input (Dp) and negative edge input (Dn) of the dual-edge flip-flop are connected to different inputs. For resolutions below 4K, the positive edge input and negative edge input of the dual-edge register are connected to the same input. In this case, its net effect is equivalent to a single-edge register. This invention leverages this principle to achieve the goal of sharing the last stage circuit for multi-resolution images. The advantage is that regardless of the resolution, the last stage path is exactly the same, and the board level does not need to consider various cases.

[0071] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the structure of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. A control device for transmitting video data using a dual-edge flip-flop, comprising a video decoder chip and a video display interface chip, wherein a video signal selection device is provided between the video decoder chip and the video display interface chip, characterized in that: The video signal selection device includes a dual-edge flip-flop and two dual-channel data selectors. The dual-edge flip-flop serves as the last-stage register unit for data output to the video display interface chip. The positive edge input of the dual-edge flip-flop is connected to the output of the first dual-channel data selector. The negative edge input of the dual-edge flip-flop is connected to the output of the second dual-channel data selector. The selection signal inputs of the two dual-channel data selectors are connected to the sel signal. The first input of the first dual-channel data selector is connected to the 4K data positive edge data; The second input of the first dual-channel data selector is connected to the 1080p data output. The first input of the second dual-channel data selector is connected to the 4K negative edge data. The second input terminal of the second dual-channel data selector is connected in parallel with the second input terminal of the first dual-channel data selector to receive data of the same resolution of 1080p and below; The CLK terminal of the dual-edge trigger is connected to the pixel_clk signal.

2. A method for controlling the transmission of video data using the control device for transmitting video data with a dual-edge trigger as described in claim 1, characterized in that: Includes the following steps: Step S101, Begin; Step S102: Input video signal; Step S103: Determine if the video signal resolution is 4K30. If it is 4K30, proceed to step S104; otherwise, proceed to step S107. Step S104: Set the dual-channel data selector sel to 1; Step S105: Configure the clock frequency corresponding to the pixel_clk resolution; Step S106: Different video data are input to the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop, respectively; Step S107: Set the dual-channel data selector sel to 0; Step S108: Configure the clock frequency corresponding to the pixel_clk resolution; Step S109: Input the same video data into the positive edge input terminal Dp and the negative edge input terminal Dn of the dual-edge flip-flop. Step S110: The output terminal of the dual-edge flip-flop outputs video data; Step S111, End.

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