A circuit structure for improving the frame rate of high-precision ADC image sensor

Abstract

The present invention relates to a circuit structure for improving the frame rate of a high-precision ADC image sensor, and belongs to the technical field of CMOS image sensors. The circuit structure includes a pixel module, a variable gain amplifier, a sampling and holding circuit, an ADC module, a detection control module, a digital control processing module and a ramp generator. In a row cycle, the detection control module detects the output signal of the comparator in each column of the ADC module. When all column signals are detected, the generated signal controls the ramp generated by the ramp generator, and also controls the data readout of the digital control processing module; the digital control processing module processes the data generated by the ADC module, and triggers the data to be output to the outside of the chip according to the signal generated by the detection control module. The present invention can reduce the processing time of the high-precision ADC and improve the frame rate of the image sensor when working in the high-precision ADC mode.

Description

Technical Field

[0001] The invention belongs to the technical field of CMOS image sensors and relates to a circuit structure for improving the frame rate of a high-precision ADC image sensor. Background Art

[0002] With the vigorous development of CMOS image sensors, in order to meet the needs of different applications, when designing image sensor chips, the function of ADC precision switching will be built-in, such as integrating 10bit, 12bit, 14bit, etc.

[0003] In the working process of CMOS image sensor, when using high-precision ADC, the maximum working frequency cannot be changed, which often causes the chip working frame rate to drop. At the same time, as the working frame rate drops, it will inevitably have a certain impact on the imaging effect. The main reason for the drop in frame rate is that the high-precision ADC requires a longer processing time, which is longer than the data readout time required by the chip. Therefore, for the same chip, in order to increase the frame rate when the high-precision ADC is working, it is necessary to reduce the processing time of the high-precision ADC according to the different pixel signals and reset signals. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a circuit structure for improving the frame rate of a high-precision ADC image sensor, so as to solve the problem of a decrease in the working frame rate of the same chip due to the high-precision ADC, that is, to improve the frame rate of the high-precision ADC when it is working and reduce the processing time of the high-precision ADC.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A circuit structure for improving the frame rate of a high-precision ADC image sensor includes a pixel module, a column parallel readout circuit structure, a detection control module, a digital control processing module and a ramp generator. Each column in the column parallel readout circuit structure includes a variable gain amplifier, a sampling and holding circuit and an ADC module connected in sequence. The ADC module, the ramp generator and the detection control module are connected to each other. The pixel signal and reset signal generated by the pixel module are amplified, sampled and held, analog-to-digital converted, counted to the final output.

[0007] The pixel module is mainly used to generate a pixel signal and a reset signal. The variable gain amplifier amplifies the signal generated by the pixel module and transmits it to the sample-and-hold circuit. The sample-and-hold circuit samples the amplified pixel signal and reset signal and stores them in the capacitor, and transmits them to the ADC module.

[0008] The ADC module of each column includes a comparator and a counter, which are used to complete analog-to-digital conversion and count. The comparator compares the ramp signal generated by the ramp generator with the processed reset signal and pixel signal, and then outputs it to the detection control module.

[0009] Within a row cycle, the detection control module detects the output signal of the comparator in each column of the ADC module. When all column signals are detected, the generated signal controls the slope generated by the ramp generator, and also controls the data readout of the digital control processing module; the digital control processing module processes the data generated by the ADC module, and triggers the data output to the outside of the chip according to the signal generated by the detection control module.

[0010] The digital control processing module receives the signal from the detection control module and uses it to trigger the subsequent data reading work, so that the processed data can meet the chip reading requirements and external acquisition requirements, and be output.

[0011] Furthermore, the detection control module is located between the ADC module and the ramp generator, and detects changes in the output of the comparator in each column of the ADC module. When the change in the output of the last column is detected (that is, all the comparators in each column of the ADC module are flipped), the detection control module will generate a signal to control the ramp generator to end the ramp generation of the ramp generator; at the same time, the signal generated by the detection control module is also transmitted to the digital control processing module for triggering subsequent data reading work.

[0012] Furthermore, the detection control module is a collection of multiple NAND gate circuits, and the output end of each comparator is connected to the input end of a NAND gate circuit, so that the output of the comparator in each column of ADC modules can be detected.

[0013] Furthermore, the detection control module performs an “AND” logic process on the outputs of the comparators in all the ADC modules.

[0014] Furthermore, the ramp generator includes an enable switch capable of independently controlling the generation of the large ramp signal, and the switch is controlled by the output signal of the detection control module.

[0015] Furthermore, the detection control module is enabled only when the ramp generator generates a large ramp, and is in a disabled state at other times.

[0016] Furthermore, the ramp generator generates two ramp signals, one small and one large, for the ADC module, which are used for comparison between the reset signal and the pixel signal respectively.

[0017] Furthermore, the counter can meet the counting requirements of different ADC precisions.

[0018] The beneficial effect of the present invention is that: in view of the situation that the same chip has different ADC precision application requirements, the detection control module designed by the present invention can control the end of the large slope in the high-precision ADC mode, and trigger the subsequent readout timing of the circuit, thereby reducing the time occupied by the preparation idle period in the line cycle. The circuit structure proposed by the present invention that can improve the frame rate of the chip high-precision ADC image sensor can reduce the unnecessary time in the line cycle and improve the working frame rate when the chip works in the high-precision ADC mode.

[0019] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 The readout timing of the chip in ADC precision 10-bit and 12-bit modes;

[0022] Figure 2 A circuit structure for improving the frame rate of a high-precision ADC image sensor in the present invention;

[0023] Figure 3 To detect the specific structure of the control module;

[0024] Figure 4 The figure is a comparison of the relationship between the slope and the readout timing after applying the frame rate increasing circuit of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0026] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0027] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0028] See also Figure 1 to Figure 4 , Figure 1 It reflects the readout timing relationship of the chip in 10-bit and 12-bit ADC precision modes. For a chip with a maximum operating frequency of 480MHz, 128 columns of data are set as a group during readout and output from the same LVDS channel. Therefore, the total readout time of the chip in 10-bit mode is 1290 clock cycles, of which 1280 (128*10) clock cycles are data readout cycles and 10 clock cycles are preparation spare cycles. The preparation spare cycle is the reserved time cycle required for the normal operation of the chip and cannot be eliminated. At the same time, the cycle of the large slope and the small slope is 1290 clock cycles. When switching to 12-bit mode, the maximum operating frequency cannot be increased, and the output readout cycle is 1536 (128*12) clock cycles. In order to meet the accuracy requirements, the cycle of the large and small slopes in the 12-bit mode is about 4 times that of the large and small slopes in the 10-bit mode, so the preparation spare cycle in the 12-bit mode is very long, resulting in a decrease in the overall frame rate of the chip.

[0029] Figure 2 The circuit structure for improving the frame rate of the high-precision ADC image sensor of the present invention is different from the existing image sensor readout circuit. The structure adds a detection control module, which is connected to the ADC module, the ramp generator, and the digital control processing module. The input signal of the detection control module is the output value of all comparators in the ADC module, and the output signal of the detection control module will act on the ramp generator and the digital control processing module respectively.

[0030] Figure 3The specific structure and function of the detection control module are shown in detail. The detection control module is a collection of multiple NAND gate circuits. The output of each comparator is connected to the input of a NAND gate circuit. In practical applications, since the image sensor array is large, it will be divided into multiple NAND gate circuit arrays for normal circuit function. In this embodiment, each NAND gate is composed of a P-NOMS tube and an N-NOMS tube. The input of each level of NAND gate circuit is the output of the four previous level NAND gate circuits. Figure 3 Pins 1 to 4 of the detection module correspond to the gates of the NOMS and PMOS tubes. This can meet the needs of circuit functions and greatly reduce the number of NAND gate circuits and the layout area. The function of this module is: within a row cycle, it determines the value of the comparator output in the large slope stage. When the values ​​of all comparators in the column-level circuit are flipped, the detection control module will output a control signal to the ramp generator to stop the generation of the large slope; at the same time, the detection control module also outputs this control signal to the digital control processing module to start the subsequent data reading work.

[0031] Figure 4 For the comparison of the relationship between the slope and the readout timing after the frame rate enhancement circuit of the present invention is applied, when the ordinary circuit works normally, due to the constant relationship between the large and small slopes, all the preparation idle periods are also constant; and the frame rate enhancement circuit will stop the generation of the large slope and perform the readout processing according to the flipping of the last column comparator in a row cycle, this operation can effectively reduce the time of the preparation idle period. Figure 4 As shown in the figure, it is shown that within two line cycles, when the pixel signals are completely consistent, by checking the discrimination output of the control module, the stop of the large slope and the subsequent readout timing are triggered, so that the working time of the frame rate improvement circuit structure is reduced by △T compared with the ordinary conventional circuit structure. It can be inferred that when the chip works normally, the time required for each frame will be reduced and the frame rate can be improved.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A circuit structure for improving the frame rate of a high-precision ADC image sensor, comprising a pixel module, a column parallel readout circuit structure and a digital control processing module connected in sequence, wherein: Each column of the column parallel readout circuit structure includes a variable gain amplifier, a sampling and holding circuit and an ADC module connected in sequence; the pixel module is used to generate a pixel signal and a reset signal; the variable gain amplifier amplifies the signal generated by the pixel module and transmits it to the sampling and holding circuit; the sampling and holding circuit samples the amplified pixel signal and reset signal and stores them in a capacitor, and transmits them to the ADC module; it is characterized in that: the circuit structure also includes a detection control module and a ramp generator; the detection control module is connected to the ADC module, the ramp generator and the digital control processing module; the ramp generator is used to generate a ramp signal and transmit it to the ADC module; the ADC module of each column includes a comparator and a counter, which are used to complete analog-to-digital conversion and perform counting; In a row cycle, the detection control module detects the output signal of the comparator in each column of the ADC module. When all column signals are detected, the generated signal controls the slope generated by the slope generator, and also controls the data reading of the digital control processing module; the detection control module is located between the ADC module and the slope generator, and detects the change of the output of the comparator in each column of the ADC module. When the change of the output of the last column is detected, the detection control module will generate a signal to control the slope generator to end the slope generation of the slope generator; at the same time, the signal generated by the detection control module is also transmitted to the digital control processing module for triggering the subsequent data reading work; The digital control processing module processes the data generated by the ADC module and triggers the data to be output to the outside of the chip according to the signal generated by the detection control module.

2. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 1, characterized in that: The detection control module is a collection of multiple NAND gate circuits, and the output end of each comparator is connected to the input end of a NAND gate circuit to detect the output of the comparator in each column of ADC modules.

3. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 2, characterized in that: The detection control module performs an AND logic process on the outputs of the comparators in all ADC modules.

4. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 1, characterized in that: The ramp generator includes an enabling switch capable of independently controlling the generation of a large ramp signal, and the switch is controlled by an output signal of a detection control module.

5. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 4, characterized in that: The detection control module is enabled only when the ramp generator generates a large ramp, and is in a closed state at other times.

6. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 1 or 4, characterized in that: The ramp generator generates two ramp signals, one small and one large, for the ADC module, which are used for comparison between the reset signal and the pixel signal respectively.

7. The circuit structure for improving the frame rate of a high-precision ADC image sensor according to claim 1, characterized in that: The counter can meet the counting requirements of different ADC precisions.

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