A display panel and a display module

Abstract

This disclosure provides a display panel and a display module. The display panel includes a display area and a peripheral area surrounding the display area. The peripheral area includes at least an overlap area, which includes a plurality of overlap pins arranged sequentially along a first direction. Each overlap pin includes at least an effective overlap portion and an insulating portion. The effective overlap portions of two adjacent overlap pins are staggered along the first direction. This disclosure, by dividing each overlap pin into an effective overlap portion and an insulating portion, and implementing a staggered design between the effective overlap portions of adjacent overlap pins, ensures that even if a conductive foreign object in the overlap area contacts any one of the effective overlap portions, it cannot simultaneously contact other adjacent effective overlap portions. This effectively avoids display defects caused by foreign object overlap without adjusting the overlap pin spacing.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and a display module. Background Technology

[0002] In current display product manufacturing, MDL Bonding is a crucial process. Its main function is to effectively connect the display panel to the driver IC or flexible printed circuit (FPC) to facilitate subsequent signal supply. However, due to increasingly stringent precision requirements for display products, the spacing between Bonding Pins (i.e., Bonding Pin Pitch) is becoming smaller. If conductive foreign objects are present in the bonding area during bonding, they can cause adjacent pins to rub against each other, resulting in poor LED illumination and affecting the display performance. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel and a display module to solve the problem in the prior art where foreign objects affect the display effect due to the reduced spacing between the overlapping pins.

[0004] The embodiments of this disclosure adopt the following technical solution: a display panel, comprising: a display area and a peripheral area surrounding the display area, the peripheral area including at least an overlapping area, the overlapping area including a plurality of overlapping pins arranged sequentially along a first direction, each overlapping pin including at least an effective overlapping portion and an insulating portion; wherein, the two effective overlapping portions of two adjacent overlapping pins are staggered along the first direction.

[0005] In some embodiments, the length of the effective overlap is 20% to 50% of the length of the overlap pin.

[0006] In some embodiments, the spacing between adjacent lap pins is 40 micrometers to 50 micrometers.

[0007] In some embodiments, each of the overlapping pins comprises at least: a substrate; a buffer layer disposed on one side surface of the substrate; a first metal layer disposed on the side surface of the buffer layer away from the substrate; a first insulating layer covering the side surface of the first metal layer away from the buffer layer; and a second metal layer covering a portion of the side surface of the first insulating layer away from the first metal layer, wherein the second metal layer is the effective overlapping portion, and the portion of the first insulating layer not covering the second metal layer is the insulating portion; wherein the first metal layer and the second metal layer are connected by a first via penetrating the first insulating layer.

[0008] In some embodiments, a first conductive layer is further provided on the surface of the second metal layer on the side away from the first insulating layer.

[0009] In some embodiments, the first conductive layer is a metal oxide conductive layer.

[0010] In some embodiments, the first metal layer is disposed on the same layer as the gate metal line in the display area, and the second metal layer is disposed on the same layer as the source and drain metal lines in the display area.

[0011] In some embodiments, the effective overlap portion is located on the side of the overlap pin closer to the display area, and the second metal layer is directly connected to the gate metal line.

[0012] In some embodiments, the effective overlap portion is located on the side of the overlap pin away from the display area, and the first metal layer and the source-drain metal line are connected through a second via penetrating the first insulating layer, so that the second metal layer is connected to the source-drain metal line through the first metal layer.

[0013] This disclosure also provides a display module, characterized in that it includes at least a display panel as described above, and a binding component, wherein the binding component is connected to the overlapping area of ​​the display panel.

[0014] The beneficial effects of this disclosure are as follows: by dividing each overlapping pin into an effective overlapping portion and an insulating portion, and implementing a staggered design between the effective overlapping portions of adjacent overlapping pins, even if a conductive foreign object in the overlapping area comes into contact with any one of the effective overlapping portions, it cannot simultaneously come into contact with other adjacent effective overlapping portions. Thus, without adjusting the spacing between the overlapping pins, the display defects caused by foreign object overlapping are effectively avoided. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of foreign object overlap in existing technology;

[0017] Figure 2 This is a top view of the display panel in the first embodiment of this disclosure;

[0018] Figure 3This is an enlarged schematic diagram of the overlapping area in the first embodiment of this disclosure;

[0019] Figure 4 This is the first embodiment of the present disclosure. Figure 3 Schematic diagram of the cross section at point AA';

[0020] Figure 5 This is the first embodiment of the present disclosure. Figure 3 Schematic diagram of the cross section at point BB';

[0021] Figure 6 This is the first embodiment of the present disclosure. Figure 3 Another cross-sectional diagram at point AA'. Detailed Implementation

[0022] Various embodiments and features of this disclosure are described herein with reference to the accompanying drawings.

[0023] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this disclosure will be apparent to those skilled in the art.

[0024] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.

[0025] These and other features of this disclosure will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0026] It should also be understood that although this disclosure has been described with reference to some specific examples, many other equivalent forms of this disclosure can be definitively implemented by those skilled in the art, which have the features of the claims and are therefore within the scope of protection defined herein.

[0027] The above and other aspects, features and advantages of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0028] Specific embodiments of this disclosure are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this disclosure, which may be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure this disclosure. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use this disclosure in a variety of substantially any suitable detailed structures.

[0029] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in still another embodiment,” all of which may refer to one or more of the same or different embodiments according to this disclosure.

[0030] In current display product manufacturing, MDL Bonding is a crucial process. Its main function is to effectively connect the display panel to the driver IC or flexible printed circuit board (FPC), facilitating subsequent signal supply to the display product. However, due to increasingly stringent precision requirements for current display products, the spacing between bonding pins (i.e., bonding pin pitch) is becoming smaller. If conductive foreign objects are present in the bonding area during bonding, they can cause adjacent pins to overlap, resulting in poor LED illumination and affecting the display effect. Figure 1 As shown. In actual module bonding, it usually refers to the bonding operation of COF / FPC / FOP on the display panel. For example, when performing COF bonding of flip-chip films, the presence of conductive foreign objects between the bonding pins will generally cause dark lines (X-shaped lines) because the conductive foreign objects cause the adjacent data signals output by the driver IC to interfere with each other. When performing FPC / FOP bonding, conductive foreign objects cause the adjacent signals input to the FPC to interfere with each other, which in turn leads to display abnormalities and affects the yield of display products.

[0031] It should be noted that the conductive foreign matter mentioned in the embodiments of this disclosure mainly refers to conductive particles such as metal particles or metal oxide particles generated during the manufacturing process of the display panel, and their size is usually less than 50 micrometers. Foreign matter larger than 50 micrometers is generally intercepted by AOI detection before the bonding operation.

[0032] To address the aforementioned problems, the first embodiment of this disclosure provides a display panel, such as... Figure 2 As shown, the display panel includes at least a display area 100 for displaying images and a peripheral area 200 around the display area 100 for wiring. One side of the peripheral area 200 has an overlap area 300, in which multiple overlap pins 400 are arranged sequentially along a first direction, and none of the overlap pins 400 overlap. Figure 2The first direction shown is the horizontal direction within the display panel. Each overlapping pin 400 extends along a second direction perpendicular to the first direction (i.e., a vertical direction perpendicular to the horizontal direction within the plane of the display panel). This facilitates the connection of each overlapping pin 400 to a unique corresponding data line in the display area 100. After the driver IC or FPC is connected to the display panel through the overlapping area 300, the connection between the overlapping pin 400 and the data line can be used to drive the display panel. It should be understood that... Figure 2 The shape, size, spacing, number, and number of rows of the overlapping pins 400 shown are for illustrative purposes only. In actual production, they can be designed and implemented according to the requirements.

[0033] Furthermore, Figure 2 The diagram also shows data lines (Data) and gate lines (Gate) arranged in a crisscross pattern within the display area 100. The gate lines are driven by gate driver integrated circuits (GOAs) located on both sides of the peripheral area 200. The data lines (Data) are connected to connection pins 400 in the connection area 300. After the connection pins 400 are connected to a driver IC or FPC, the driver IC or FPC can write corresponding data signals to the data lines (Data). Specifically, the display area 100 includes multiple pixels arranged in an array, which can correspond to... Figure 2 The area enclosed between two adjacent data lines and two adjacent gate lines is the smallest unit for displaying an image, used to display a single red, green, or blue color. Each pixel is driven and controlled by a pixel driving circuit, which typically includes multiple thin-film transistors (TFTs) and at least one capacitor. The TFT is turned on and off by controlling the driving signal applied to its gate.

[0034] Each pixel corresponds to a light-emitting unit, and the light emission of the light-emitting unit is controlled by a pixel driving circuit connected to the light-emitting unit. Specifically, the light-emitting unit includes an anode layer AND, a light-emitting layer EML, and a cathode layer CTD arranged sequentially along the direction away from the substrate. The light-emitting layer EML includes multiple spaced effective light-emitting parts, which are used to emit light. For example, the effective light-emitting parts include electroluminescent materials. Electroluminescence refers to the phenomenon where organic semiconductor materials emit light through carrier injection, transport, and the combination of electrons and holes to form excitons under the drive of an electric field, which then leads to radiative recombination. Some of the multiple effective light-emitting parts are used to emit red light, another part is used to emit green light, and yet another part is used to emit blue light. For example, different electroluminescent materials can be selected so that the effective light-emitting parts can emit light of different colors. Furthermore, the effective light-emitting parts that emit red light, green light, and blue light can be mixed and arranged in an array. By emitting different light intensities from the effective light-emitting parts, different intensities of red, green, and blue light can be obtained. By mixing red, green, and blue light of different intensities, the display panel can display a color image.

[0035] By further integrating the pixel driving circuit design, the effect of driving the emissive layer (EML) to emit light can be achieved. In some embodiments, one pixel driving circuit is electrically connected to one effective light-emitting unit via the anode layer AND, allowing each pixel driving circuit to provide driving current to each effective light-emitting unit through the anode layer AND. This enables multiple effective light-emitting units to emit light independently, reducing mutual interference between them and improving the display effect of the display panel. Furthermore, by adjusting the driving current provided by the pixel driving circuit to the effective light-emitting unit, the brightness of the effective light-emitting unit can be adjusted.

[0036] In addition, the display panel should also include traces and drive control components for related signals such as reset signal Vint, operating voltage VDD, and cathode drive voltage VSS, and may also include test pins, etc. Figure 2 Not shown in the diagram, it can be implemented according to the conventional display panel design based on actual needs. In the actual product manufacturing process, other functional film layers can also be set on the display side of the display area 100, including but not limited to touch function layer, anti-reflection layer, anti-fingerprint layer, hardening layer, and encapsulation cover, to enable the display panel to achieve different functions and provide a better user experience.

[0037] Figure 3 An enlarged schematic diagram of the overlap area 300 is shown, illustrating the arrangement of some of the overlap pins 400 within the overlap area 300. Specifically, as... Figure 3As shown, each lap pin 400 includes an effective lap portion 401 and an insulating portion 402, wherein the effective lap portion 401 is in Figure 3 The shading is used to indicate the connection. In this embodiment, the effective contact portion 401 refers to the exposed gold finger portion, which is the area that makes electrical connection with the driver IC or FPC, while the insulating portion 402 is the non-conductive part of the contact pin 400, and its surface is usually covered with an insulating layer to achieve the insulation function. For a single lap pin 400, when setting the effective lap portion 401, it can be set on the side of the lap pin 400 closer to the display area 100 or on the side of the lap pin 400 farther from the display area 100. The effective lap portions 401 between adjacent lap pins 400 are arranged in an alternating design so that the two effective lap portions 401 of two adjacent lap pins 400 do not overlap in the orthographic projection in the first direction. This ensures that when a conductive foreign object comes into contact with the effective lap portion 401 of any lap pin 400, even if the size of the conductive foreign object is larger than the distance between the lap pins 400, the other side of the foreign object will only contact the insulating part 402 of the adjacent lap pin 400, and no effective lap will occur. Thus, without adjusting the lap pin spacing, the display malfunction caused by foreign object lap is effectively avoided.

[0038] It should be noted that in this embodiment, the spacing between adjacent overlapping pins 400 is generally between 40 and 50 micrometers. A spacing smaller than 40 micrometers cannot meet the fabrication requirements of the overlapping pins, while a spacing greater than 50 micrometers, even with conventional overlapping pin 400 arrangement, usually prevents conductive foreign objects from simultaneously contacting two adjacent overlapping pins 400. Therefore, there is no need for improvement. In actual fabrication, although the spacing between overlapping pins 400 is decreasing due to the high precision requirements of display products, the pin length of the overlapping pins 400 does not change significantly. Especially for the pin length corresponding to COF / FPC / FOP Bonding, the length is generally in the millimeter range, usually around 1 millimeter. Therefore, even if a portion of the overlapping pins 400 is provided as an insulated part 402 that cannot be connected, the area occupied by the effective overlapping part 401 can still meet the effective connection between the display panel and the driver IC or FPC.

[0039] In some embodiments, the width of the effective overlap portion 401 and the insulating portion 402 are both the width of the overlap pin 400, while the length of the effective overlap portion 401 is between 20% and 50% of the length of the overlap pin 400. If the length of the effective overlap portion 401 is less than 20% of the length of the overlap pin 400, an effective connection cannot be formed between the effective overlap portion 401 and the gold finger of the driver IC or FPC, which can easily lead to disconnection. If the length of the effective overlap portion 401 is greater than 50% of the length of the overlap pin 400, there is an overlap between the orthographic projections of the effective overlap portions 401 of two adjacent overlap pins 400 in the first direction. If a conductive foreign object happens to fall on the overlapping part, an abnormal overlap problem may still occur. Therefore, in this embodiment, the length of the effective overlap portion 401 is limited to between 20% and 50% of the length of the overlap pin 400, which can prevent abnormal overlap from occurring while ensuring an effective connection. It should be understood that the specific value of the length of the effective overlap portion 401 in the length of the overlap pin 400 can be determined by combining the length of the overlap pin 400, the length of the gold fingers of the driver IC or FPC, the concentration of conductive particles contained in the conductive adhesive (referring to the adhesive used to fix the connection between the overlap pin 400 and the gold fingers of the driver IC or FPC), and the actual required connection effect. Generally, the length of the effective overlap portion 401 is set to between 35% and 45% of the length of the overlap pin 400.

[0040] Figure 4 for Figure 3 The cross-sectional schematic diagram at point AA' shows the film structure of an overlap pin 400 in the overlap area 300 of the display panel, where side A is the side closer to the display area 100, and side A' is the side farther from the display area 100. Figure 4 As shown, its film structure includes at least a substrate 10 and a film disposed on one side surface of the substrate 10 (corresponding to...). Figure 4 The buffer layer 20 on the upper surface of the substrate 10, and the surface of the buffer layer 20 away from the substrate 10 (corresponding to) Figure 4 The first metal layer 30 (upper surface of the middle buffer layer 20) and the surface covering the first metal layer 30 away from the buffer layer 20 (corresponding to) Figure 4 The first insulating layer 40 (on the upper surface of the first metal layer 30) and the portion of the surface of the first insulating layer 40 disposed on the side away from the first metal layer 30 (corresponding to) Figure 4 The second metal layer 50 (on the upper surface of the first insulating layer 40). Corresponding to Figure 4 In the structure shown, the second metal layer 50 is the effective overlap portion 401. The actual overlap portion is the surface of the second metal layer 50 away from the first insulating layer 40 (corresponding to...). Figure 4The upper surface of the second metal layer 50, and the portion of the first insulating layer 40 that does not cover the second metal layer 50 is the insulating part 402.

[0041] Generally, display panels mainly refer to organic light-emitting diode (OLED) display panels or quantum dot (QLED) electroluminescent display panels. Substrate 10 refers to the substrate that provides support, and its material is typically any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC). In actual fabrication, corresponding to the portion of substrate 10 in the display area 100, multiple layers of conductive layers are typically stacked together on its surface, and insulating layers (including but not limited to gate insulating layers, passivation layers, planarization layers, etc.) are disposed between the conductive layers to provide electrical isolation between adjacent conductive layers. For example, the pixel driving circuit can be disposed in a multilayer conductive layer, mainly including an active layer, a gate layer, a first source-drain metal layer SD1, and a second source-drain metal layer SD2, etc., sequentially away from the substrate 10, for forming a portion of the multiple thin-film transistors (one, two, or more). The active layer and the second gate metal layer Gate2 can be used to form another portion of the multiple thin-film transistors (one, two, or more). The gate layer can also be divided into a first gate metal layer Gate1 and a second gate metal layer Gate2, for forming at least one capacitor. The layers within the display area 100 are simultaneously fabricated in the peripheral area 200 during the manufacturing process, but not all film layers are implemented in the peripheral area 200. Generally, metal layers such as the active layer and gate layer do not need to be fabricated in the peripheral region 200. However, in order to ensure that the surface height of the film layers between the display region 100 and the peripheral region 200 is consistent, the insulating layer between each conductive layer is fabricated simultaneously in the display region 100 and the peripheral region 200. In this embodiment, the buffer zone 20 refers to each insulating film layer fabricated in the peripheral region 200. The specific film layers included include, but are not limited to, the PI layer between the gate layer and the active layer, the GI layer between the first gate layer and the second gate layer, and the ILD layer between the gate and the source / drain metal layers. The specific film layers fabricated in the display region 100 are determined according to the fabrication requirements of the pixel driving circuit, which will not be elaborated here in this embodiment.

[0042] It is important to note that Figure 4 The effective contact portion 401 of the corresponding contact pin 400 is located on the side closer to the display area 100, that is... Figure 4The second metal layer 50 is disposed near the right side, while the first metal layer 30 is disposed near the left side. The first metal layer 30 and the second metal layer 50 have an overlapping area between their orthogonal projections on the substrate 10. A first via 41 penetrating the first insulating layer 40 is disposed in the overlapping area so that the second metal layer 50 is connected to the first metal layer 30 through the first via 41.

[0043] Figure 4 The diagram also shows the film structure of a portion of the display area 100. In actual display panel manufacturing, each film layer within the display area 100 is fabricated in the same layer as the corresponding film layer in the peripheral area 200, i.e., in the same process. Figure 4 The substrate 10 shown is actually a common substrate for the display area 100 and the peripheral area 200. The buffer layer 20 is fabricated corresponding to each buffer level in the display area 100. This embodiment does not describe or show the specific levels contained in the buffer layer 20; it can be fabricated according to actual needs. The first metal layer 30 is disposed on the same layer as the gate metal line in the display area 100. Specifically, it can be the second gate layer in the pixel driving circuit. The first insulating layer 40 covering it is on the same layer as the interlayer insulating layer (ILD) in the display area 100. The second metal layer 50 is on the same layer as the source-drain metal (SD) line in the display area 100, and can also be called the data line. A planarization layer PLN is also covered on the SD layer in the display area 100. It is necessary to ensure that the second metal layer 50, as the effective overlap portion 401, has an effective connection with the source-drain metal line. This is to ensure that the display panel can be driven after the effective overlap portion 401 is connected to the driver IC or FPC.

[0044] for Figure 4 The shown lap pin 400 has an effective lap portion 401 disposed on the side near the display area 100, as shown in the reference. Figure 4 The film structure shown can be directly connected to the source and drain metal lines in the display area 100. That is, in actual fabrication, the second metal layer 50 and the corresponding source and drain metal lines are integrated based on the same process. After connecting the driver IC or FPC, the connection between the driver IC or FPC and the data line can be directly realized. At this time, the first metal layer 30 is connected to the second metal layer 50 through the first via 41. In fact, it can also be connected to other metal layers in the same layer in the peripheral area 200 to realize signal transmission.

[0045] Figure 5 This shows Figure 3A cross-sectional schematic diagram at BB' shows the film structure of another overlapping pin 400 in the overlapping area 300 of the display panel, where side B is the side closer to the display area 100, and side B' is the side farther from the display area 100. Distinguished from... Figure 4 The lap pin 400 shown is... Figure 5 The effective overlap portion 401 of the shown overlap pin 400 is configured on the side away from the display area 100, that is, near the second metal layer 50. Figure 5 The left side is not directly connected to the source and drain metal lines in the display area 100 (i.e., it cannot be integrated into the fabrication). In this case, the first metal layer 30 can be used as a jumper. The first via 41 between the first metal layer 30 and the second metal layer 50, combined with the second via 42 that penetrates the first insulating layer 40 between the first metal layer 30 and the source and drain metal lines, can achieve the switching connection between the second metal layer 50 and the source and drain metal lines, thereby ensuring the effective connection between the driver IC or FPC and the data lines.

[0046] It is important to note that, generally, each source-drain metal line (data line) is used to indicate the display status of a column or row of pixels in the display area 100. The second metal layer 50 of each lap pin 400 is connected to only one source-drain metal line in the display area 100. Different lap pins 400 are connected to different source-drain metal lines, and the number of lap pins 400 is always greater than or equal to the number of source-drain metal lines to ensure that each row or column of pixels can be controlled by the driver IC or FPC. In actual fabrication, no changes to the fabrication process are required. Simply refer to the pattern to be formed in the peripheral area 200 when fabricating the gate metal layer, interlayer insulating layer, and source-drain metal layer, and use a mask with the corresponding pattern to perform the fabrication and etching operations for each layer.

[0047] In the display panel provided in this embodiment, by dividing each overlapping pin into an effective overlapping portion and an insulating portion, and implementing a staggered design between the effective overlapping portions, even if a conductive foreign object in the overlapping area comes into contact with any one of the effective overlapping portions, it cannot simultaneously come into contact with other adjacent effective overlapping portions. Therefore, without adjusting the overlapping pin spacing, it effectively avoids display defects caused by foreign object overlap. The above-described display panel is suitable for various commonly used electronic devices, especially small-to-medium-sized devices with high resolution such as smartphones and tablets. These devices, in order to achieve higher resolution in a smaller size, need to reduce the spacing between overlapping pins to accommodate more overlapping pins.

[0048] In practical use, the display panel provided in this embodiment can also be used in a vehicle environment. However, the operating environment of the display panel, as a central control device in a vehicle, is much harsher. High temperatures, low temperatures, bumps, and even impacts can all cause problems with the connection between the display panel and the driver IC or FPC. Therefore, in some embodiments, it is also possible to... Figure 4 or Figure 5 Based on the film structure of the overlapping pins shown, a first conductive layer 60 is prepared on the surface of the second metal layer 50 away from the first insulating layer 40, as shown. Figure 6 As shown. The first conductive layer 60 mainly refers to a metal oxide conductive layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO). While protecting the metal layer of the effective overlap portion 401, the first conductive layer 60 also enhances the connection strength with the gold fingers of the driver IC or FPC, allowing the display panel to be used under more extreme conditions, thereby ensuring stable operation of the display panel in the automotive environment. It should be noted that... Figure 6 In fact, in Figure 4 The schematic diagram shows the film structure after adding the first conductive layer 60 to the film structure of the corresponding overlapping pin 400. Specifically, the effective overlapping portion 401 in the overlapping pin 400 is set closer to the display area 100; when the effective overlapping portion 401 in the overlapping pin 400 is set farther from the display area 100, it can be directly applied to the display area 100. Figure 5 Based on the film structure shown, a first conductive layer 60 can be additionally provided on the upper surface of the second metal layer 50, which is not shown in this embodiment.

[0049] The second embodiment of this disclosure provides a display module, which includes at least the display panel provided in the first embodiment of this disclosure, and also includes a bonding component. The bonding component is connected to the overlapping area of ​​the display panel to complete the bonding process between the bonding component and the display panel. By dividing the overlapping pins in the overlapping area of ​​the display panel into effective overlapping parts and insulating parts, a staggered design is achieved between the effective overlapping parts of adjacent overlapping pins. This ensures that the impact of foreign object overlapping problems caused by conductive foreign objects can be avoided during the bonding process of the module, and a stable display effect can be achieved without adjusting the spacing of the overlapping pins.

[0050] Generally, the display module in this embodiment mainly refers to the module used in small-to-medium-sized devices with high resolution, such as smartphones and tablets. To achieve higher resolution in a smaller size, these modules require reducing the spacing between the overlapping pins to accommodate more overlapping pins. Additionally, the display module can also be used in in-vehicle central control equipment. Corresponding to the harsh operating environment of vehicles, including high and low temperatures, bumps, and even impacts, each overlapping pin in the display panel includes a first conductive layer to protect the effective overlapping portion and improve subsequent bonding performance. Bonding components include, but are not limited to, chip-on-film capacitors (COF), flexible printed circuit boards (FPC), and driver ICs. The specific number, bonding position, and bonding method of these bonding components can be set according to actual needs, and this embodiment does not impose any limitations.

[0051] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. A display panel, characterized by, The display panel comprises: a display area and a peripheral area surrounding the display area, the peripheral area comprising at least a lapping area, the lapping area comprising a plurality of lapping pins arranged in a first direction, each of the lapping pins comprising at least an effective lapping part and an insulation part; wherein the effective lapping parts of two adjacent lapping pins are staggered in the first direction; each of the lapping pins comprises at least: a substrate; a buffer layer disposed on one side surface of the substrate; a first metal layer disposed on a side surface of the buffer layer away from the substrate; a first insulating layer covering a side surface of the first metal layer away from the buffer layer; a second metal layer covering a part of a side surface of the first insulating layer away from the first metal layer, the second metal layer being the effective lapping part, and the part of the first insulating layer not covered by the second metal layer being the insulation part; wherein the first metal layer and the second metal layer are connected by a first via hole penetrating through the first insulating layer.

2. The display panel of claim 1, wherein, The length of the effective lapping part is 20% to 50% of the length of the lapping pin.

3. The display panel of claim 1, wherein, The distance between two adjacent lapping pins is 40 microns to 50 microns.

4. The display panel of claim 1, wherein, A first conductive layer is further disposed on a side surface of the second metal layer away from the first insulating layer.

5. The display panel of claim 4, wherein, The first conductive layer is a metal oxide conductive layer.

6. The display panel of claim 1, wherein, The first metal layer is disposed in the same layer as a gate metal line in the display area, and the second metal layer is disposed in the same layer as a source / drain metal line in the display area.

7. The display panel of claim 6, wherein, The effective lapping part is located on a side of the lapping pin close to the display area, and the second metal layer is directly connected to the gate metal line.

8. The display panel of claim 6, wherein, The effective lapping part is located on a side of the lapping pin away from the display area, and the first metal layer is connected to the source / drain metal line through a second via hole penetrating through the first insulating layer, so that the second metal layer is connected to the source / drain metal line through the first metal layer.

9. A display module, characterized by The display panel comprises at least any one of the display panels according to claims 1 to 8, and a binding assembly connected to the lapping area of the display panel.

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